TI TIBPAL22V10ACNT

TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
•
•
•
•
•
•
•
•
•
•
Choice of Operating Speeds
TIBPAL22V10AC . . . 25 ns Max
TIBPAL22V10AM . . . 30 ns Max
TIBPAL22V10C . . . 35 ns Max
CLK/I
I
I
I
I
I
I
I
I
I
I
GND
Increased Logic Power – Up to 22 Inputs
and 10 Outputs
Increased Product Terms – Average of 12
Per Output
Variable Product Term Distribution
Allows More Complex Functions to Be
Implemented
Each Output Is User Programmable for
Registered or Combinational Operation,
Polarity, and Output Enable Control
Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features
Dependable Texas Instruments Quality and
Reliability
I
I
I
NC
I
I
I
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Functionally Equivalent to AMDs
AMPAL22V10 and AMPAL22V10A
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
TTL-Level Preload for Improved Testability
Fast Programming, High Programming
Yield, and Unsurpassed Reliability Ensured
Using Ti-W Fuses
1
I
I
CLK/I
NC
VCC
I/O/Q
I/O/Q
•
C SUFFIX . . . NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
Second-Generation PLD Architecture
4
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
I
I
GND
NC
I
I/O/Q
I/O/Q
•
•
NC – No internal connection
Pin assignments in operating mode
description
The TIBPAL22V10 and TIBPAL22V10A are programmable array logic devices featuring high speed and
functional equivalency when compared to presently available devices. They are implemented with the familiar
sum-of-products (AND-OR) logic structure featuring the new concept “Programmable Output Logic Macrocell”.
These IMPACT circuits combine the latest Advanced Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered
and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are
enabled through the use of individual product terms.
These devices are covered by U.S. Patent 4,410,987.
IMPACT is a trademark of Texas Instruments Incorporated.
Copyright  1992, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
description (continued)
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This
variable allocation of terms allows far more complex functions to be implemented than in previously available
devices.
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22V10 and TIBPAL22V10A offer quick design and development of custom LSI functions with
complexities of 500 to 800 equivalent gates. Since each of the ten output pins may be individually configured
as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or
down to 12 inputs and 10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered
outputs selected as active-high power up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will appear to be open.
The TIBPAL22V10C and TIBPAL22V10AC are characterized for operation from 0°C to 75°C. The
TIBPAL22V10AM is characterized for operation over the full military temperature range of –55°C to125°C.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
functional block diagram (positive logic)
C1
Set
&
1S
Reset
44 x 132
8
R
1
Output
Logic
Macrocell
I/O/Q
EN
10
I/O/Q
22
CLK/I
EN
12
I/O/Q
EN
14
I/O/Q
EN
16
I/O/Q
EN
16
I/O/Q
I
11
22
10
EN
14
I/O/Q
EN
12
I/O/Q
EN
10
I/O/Q
EN
8
I/O/Q
EN
10
10
10
denotes fused inputs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
1
Increments
0
First
Fuse
Numbers
4
8
12
16
20
24
28
32
36
40
Asynchronous Reset
(to all registers)
0
Macrocell
23
I/O/Q
396
P = 5808
R = 5809
440
Macrocell
22
I/O/Q
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880
I
2
P = 5810
R = 5811
924
Macrocell
21
I/O/Q
• DALLAS, TEXAS 75265
1452
I
3
P = 5812
R = 5813
1496
Macrocell
20
I/O/Q
2112
I
4
P = 5814
R = 5815
2156
Macrocell
2860
I
5
P = 5816
R = 5817
19
I/O/Q
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
CLK/I
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
4
logic symbol (positive logic)
2904
Macrocell
18
I/O/Q
I
P = 5818
R = 5819
3652
Macrocell
17
I/O/Q
POST OFFICE BOX 655303
4268
I
7
P = 5820
R = 5821
4312
Macrocell
16
I/O/Q
I
P = 5822
R = 5823
4884
Macrocell
15
I/O/Q
5324
I
9
P = 5824
R = 5825
5368
Macrocell
14
I/O/Q
5720
I
10
P = 5826
R = 5827
Synchronous Set
(to all registers)
5764
I
11
5
Fuse number = First fuse number + Increment
Inside each MACROCELL the ”P” fuse is the polarity fuse and the ”R” fuse is the register fuse.
13
I
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
• DALLAS, TEXAS 75265
4840
8
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
3608
6
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
output logic macrocell diagram
Output Logic Macrocell
MUX
2
AR
R I=0
3
1D
0
C1
SS
1
1S
0
From Clock Buffer
S0
MUX
1
1
G1
S1
AR = asynchronous reset
SS = synchronous set
6
0
1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
G
3
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
R
R
1D
1D
C1
C1
1S
1S
S1 = 0
S0 = 0
S1 = 0
S0 = 1
REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT
REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
S1 = 1
S1 = 1
S0 = 0
S0 = 1
I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT
I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
FUSE SELECT
S1
S0
FEEDBACK AND OUTPUT CONFIGURATION
0
0
Register feedback
Registered
Active low
0
1
Register feedback
Registered
Active high
1
0
I/O feedback
Combinational
Active low
1
1
I/O feedback
Combinational
Active high
0 = unblown fuse, 1 = blown fuse
S1 and S0 are select-function fuses as shown in the output logic macrocell
diagram.
Figure 1. Resultant Macrocell Feedback and Output Logic After Programming
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TIBPAL22V10C, TIBPAL22V10AC
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.5 V
Voltage range applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
TIBPAL22V10C
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
fclock
tw
UNIT
NOM
MAX
MIN
NOM
MAX
4.75
5
5.25
4.75
5
5.25
V
5.5
2
5.5
V
High-level input voltage
2
0.8
0.8
High-level output current
– 3.2
– 3.2
mA
Low-level output current
Clock frequency†
16
16
mA
28.5
MHz
Pulse duration
18
Clock high or low
25
15
Asynchronous reset high or low
35
25
Input
30
20
Feedback
30
20
Synchronous set
30
25
Asynchronous reset low (inactive)
35
25
tsu
Setup time before clock↑
th
TA
Hold time, input, set, or feedback after clock↑
0
Operating free-air temperature
0
† fclock (with feedback) =
8
TIBPAL22V10AC
MIN
t su
)
t
1
,f
(without feedback) =
(CLK to Q) clock
t w(low)
pd
POST OFFICE BOX 655303
)
ns
ns
0
75
1
t w(high)
• DALLAS, TEXAS 75265
0
V
ns
75
°C
TIBPAL22V10C, TIBPAL22V10AC
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
II = – 18 mA
IOH = – 3.2 mA
VOL
IOZH
VCC = 4.75 V,
VCC = 5.25 V,
IOL = 16 mA
VO = 2.7 V
VCC = 5.25 V,
VI = 0.4 V
II
IIH
VCC = 5.25 V,
VCC = 5.25 V,
VI = 5.5 V
VI = 2.7 V
IIL
IOS‡
VCC = 5.25 V,
VCC = 5.25 V,
VI = 0.4 V
VO = 0.5 V
ICC
VCC = 5.25 V,
VI = GND,
Any output
IIL
Any I/O
TIBPAL22V10C
TYP†
MAX
TEST CONDITIONS
MIN
TIBPAL22V10AC
TYP†
MAX
MIN
– 1.2
2.4
3.5
0.35
– 1.2
2.4
0.5
3.5
0.35
Outputs open
V
V
0.1
0.1
mA
– 100
– 100
– 250
– 250
µA
1
1
mA
25
25
µA
– 0.25
mA
– 90
mA
180
mA
– 90
120
V
0.5
– 0.25
– 30
UNIT
– 30
180
120
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
fmax¶
tpd
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
With feedback
TIBPAL22V10C
TYP†
MAX
MIN
18
28.5
MIN
TIBPAL22V10AC
TYP†
MAX
UNIT
MHz
I, I/O
I/O
R1 = 300 Ω,
15
35
15
25
ns
tpd
tpd
I, I/O (reset)
Q
R2 = 390 Ω,
15
40
15
30
ns
CLK
Q
See Figure 4
10
25
10
15
ns
ten
tdis
I, I/O
I/O, Q
15
35
15
25
ns
I, I/O
I/O, Q
15
35
15
25
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
1
1
¶ fmax (with feedback) =
,f
(without feedback) =
t su
t (CLK to Q) max
t w(low)
t w(high)
pd
)
)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.5 V
Voltage range applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
5.5
V
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
–2
mA
IOL
fclock
Low-level output current
Clock frequency†
12
mA
22
MHz
tw
Pulse duration
High-level input voltage
2
tsu
Setup time before clock↑
th
TA
Hold time, input, set, or feedback after clock↑
20
Asynchronous reset high or low
30
Input
25
Feedback
25
Synchronous set
25
Asynchronous reset low (inactive)
30
t su
)
t
–55
1
,f
(without feedback) =
(CLK to Q) clock
t w(low)
pd
POST OFFICE BOX 655303
ns
ns
0
Operating free-air temperature
† fclock (with feedback) =
10
Clock high or low
)
1
t w(high)
• DALLAS, TEXAS 75265
ns
125
°C
TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V,
II = – 18 mA
IOH = –2 mA
VOL
IOZH
VCC = 4.5 V,
VCC = 5.5 V,
IOL = 12 mA
VO = 2.7 V
IOZL
II
VCC = 5.5 V,
VCC = 5.5 V,
VO = 0.4 V
VI = 5.5 V
IIH
IIL
VCC = 5.5 V,
VCC = 5.5 V,
VI = 2.7 V
VI = 0.4 V
IOS‡
ICC
VCC = 5.5 V,
VCC = 5.5 V,
VO = 0.5 V
VI = GND,
MIN
2.4
TYP†
UNIT
– 1.2
V
3.5
0.25
– 30
Outputs open
MAX
120
V
0.5
V
0.1
mA
– 100
µA
1
mA
25
µA
– 0.25
mA
– 90
mA
180
mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
fmax¶
tpd
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
With feedback
MIN
TYP†
MAX
22
UNIT
MHz
I, I/O
I/O
R1 = 390 Ω,
15
30
ns
tpd
tpd
I, I/O (reset)
Q
R2 = 750 Ω,
15
35
ns
CLK
Q
See Figure 4
10
20
ns
ten
tdis
I, I/O
I/O, Q
15
30
ns
I, I/O
I/O, Q
15
30
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
1
1
¶ fmax (with feedback) =
,f
(without feedback) =
t su
t (CLK to Q) max
t w(low)
t w(high)
pd
)
)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
preload procedure for registered outputs (see Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below:
Step 1.
Step 2.
Step 3.
Step 4.
With VCC at 5 V and pin 1 at VIL, raise pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1, clocking in preload data.
Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage level
at the output pin.
VIHH
Pin 13
VIL
td
tsu
tw
td
VIH
Pin 1
VIL
VIH
Registered I/O
Input
VOH
Output
VIL
VOL
Figure 2. Preload Waveforms
NOTES: 2. Pin numbers shown are for JT and NT packages only. If chip-carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
power-up reset
Following power up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be
monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and
feedback setup times are met.
VCC
5V
4V
tpd †
(600 ns typ, 1000 ns MAX)
Active High
Registered Output
VOH
State Unknown
1.5 V
VOL
Active Low
Registered Output
VOH
State Unknown
1.5 V
VOL
tsu ‡
VIH
CLK
1.5 V
1.5 V
VIL
tw
† This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡ This is the setup time for input or feedback.
Figure 3. Power-Up Reset Waveforms
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
5V
S1
R1
From Output
Under Test
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
Timing
Input
1.5 V
1.5 V
tw
th
(3.5 V) [3 V]
Data
Input
1.5 V
1.5 V
(0.3 V) [0]
1.5 V
(0.3 V) [0]
In-Phase
Output
1.5 V
VOH
1.5 V
VOL
tpd
tpd
1.5 V
1.5 V
(0.3 V) [0]
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(3.5 V) [3 V]
Output
Control
(low–level
enabling)
1.5 V
1.5 V
(0.3 V) [0]
ten
tpd
tpd
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
(3.5 V) [3 V]
1.5 V
(3.5 V) [3 V]
Low-Level
Pulse
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V
(0.3 V) [0]
(0.3 V) [0]
tsu
Out-of-Phase
Output
(see Note D)
(3.5 V) [3 V]
High-Level
Pulse
Waveform 1
S1 Closed
(see Note B)
tdis
1.5 V
≈ 3.3 V
VOL +0.5 V
VOL
tdis
ten
Waveform 2
S1 Open
(see Note B)
VOH
1.5 V
VOH –0.5 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ). PRR ≤ 1 MHz,
tr = tf ≤ 2 ns, duty cycle = 50%. For M suffix, use the voltage levels indicated in brackets [ ]. PRR ≤ 10 MHz, tr and tf ≤ 2 ns,
duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 4. Load Circuit and Voltage Waveforms
14
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