DAC6571 www.ti.com SLAS406 – DECEMBER 2003 +2.7 V to +5.5 V, I2C INTERFACE, VOLTAGE OUTPUT, 10-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • • • • • • • The DAC6571 is a low-power, single channel, 10-Bit buffered voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC6571 utilizes an I2C compatible two wire serial interface that operates at clock rates up to 3.4 Mbps with address support of up to two DAC6571s on the same data bus. • • • • Micropower Operation: 125 µA @ 3 V Fast Update Rate: 188 kSPS Power-On Reset to Zero +2.7 V to +5.5 V Power Supply Specified Monotonic by Design I2C™ Interface up to 3.4 Mbps On-Chip Output Buffer Amplifier, Rail-to-Rail Operation Double-Buffered Input Register Address Support for up to Two DAC6571s Small 6 Lead SOT 23 Package Operation From -40°C to 105°C APPLICATIONS • • • • • The output voltage range of the DAC is 0 V to VDD. The DAC6571 incorporates a power-on-reset circuit that ensures that the DAC output powers up at zero volts and remains there until a valid write to the device takes place. The DAC6571 contains a power-down feature, accessed via the internal control register, that reduces the current consumption of the device to 50 nA at 5 V. The low power consumption of this part in normal operation makes it ideally suited for portable battery operated equipment. The power consumption is less than 0.7 mW at VDD = 5 V reducing to 1 µW in power-down mode. Process Control Data Acquistion Systems Closed-Loop Servo Control PC Peripherals Portable Instrumentation DAC7571/6571/5571 are 12/10/8 bit single channel I2C DACs from the same family. DAC7574/6574/5574 and DAC7573/6573/5573 are 12/10/8 bit quad channel I2C DACs. Also see DAC8571/8574 for single/quad channel 16-bit I2C DACs. VDD GND Power-On Reset Ref (+) REF(−) 10-Bit DAC DAC Register I2C Control Logic A0 SCL Output Buffer Power Down Control Logic VOUT Resistor Network SDA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of Philips Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003, Texas Instruments Incorporated DAC6571 www.ti.com SLAS406 – DECEMBER 2003 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING DAC6571 SOT23-6 DBV -40°C to +105°C D671 (TOP VIEW) 2 3 D671 1 6 5 4 A0 SCL SDA (BOTTOM VIEW) 5 4 YMLL 6 TRANSPORT MEDIA DAC6571IDBVT 250 Piece Small Tape and Reel DAC6571IDBVR 3000 Piece Tape and Reel PIN DESCRIPTION (SOT23-6) PIN CONFIGURATIONS VOUT GND VDD ORDERING NUMBER PIN NAME 1 VOUT Analog output voltage from DAC 2 GND Ground reference point for all circuitry on the part 3 VDD Analog Voltage Supply Input 4 SDA Serial Data Input 5 SCL Serial Clock Input 6 A0 LOT TRACE CODE: 1 2 DESCRIPTION Device Address Select Year (3 = 2003); M onth (1–9 = JAN–SEP; A=OCT, B=NOV, C=DEC); LL– Random code generated when assembly is requested 3 Lot Trace Code ABSOLUTE MAXIMUM RATINGS (1) UNITS VDD to GND -0.3V to +6V Digital Input voltage to GND -0.3 V to +VDD + 0.3 V VOUT to GND -0.3 V to +VDD + 0.3 V Operating temperature range -40°C to + 105°C Storage temperature range -65°C to + 150°C Junction temperature range (TJ max) + 150°C Power dissipation (TJmax - TA)RΘJA Thermal impedance, RΘJA Lead temperature, soldering (1) 2 240°C/W Vapor phase (60s) 215°C Infrared (15s) 220°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. DAC6571 www.ti.com SLAS406 – DECEMBER 2003 ELECTRICAL CHARACTERISTICS VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C unless otherwise noted. PARAMETER CONDITIONS DAC6571 MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 10 Bits Relative accuracy Differential nonlinearity Assured monotonic by design ±2 LSB ±0.5 LSB Zero code error All zeroes loaded to DAC register 5 20 mV Full-scale error All ones loaded to DAC register -0.15 -1.25 % of FSR ±1.25 % of FSR Gain error Zero code error drift ±7 µV/°C Gain temperature coefficient ±3 ppm of FSR/°C OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time 0 1/4 Scale to 3/4 scale change (400H to C00H) ; RL = ∞ 7 Slew rate Capacitive load stability Code change glitch impulse 9 µs 1 V/µs pF RL = ∞ 470 1000 pF 1 LSB Change around major carry 20 nV-s 0.5 nV-s DC output impedance Power-up time V RL = 2kΩ Digital feedthrough Short-circuit current VDD VDD = +5V VDD = +3V 1 Ω 50 mA 20 mA Coming out of power-down mode, VDD = +5V 2.5 µs Coming out of power-down mode, VDD = +3V 5 µs LOGIC INPUTS (2) Input current VINL, Input low voltage VINH, Input high voltage VDD = +3V VDD = +5V ±1 µA 0.3×VDD V 0.7×VD V D Pin capacitance 3 pF 5.5 V POWER REQUIREMENTS VDD 2.7 IDD (normal operation) DAC active and excluding load current VDD = +3.6V to +5.5V VIH = VDD and VIL = GND 155 200 µA VDD = +2.7V to +3.6V VIH = VDD and VIL = GND 125 160 µA IDD (all power-down modes) VDD = +3.6 V to +5.5V VIH = VDD and VIL = GND 0.2 1 µA VDD = +2.7V to +3.6V VIH = VDD and VIL = GND 0.05 1 µA ILOAD = 2mA, VDD = +5V 93 POWER EFFICIENCY IOUT/IDD (1) (2) % Linearity calculated using a reduced code range of 12 to 1012; output unloaded. Specified by design and characterization, not production tested. 3 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 TIMING CHARACTERISTICS SYMBOL fSCL tBUF tHD; tSTA tLOW tHIGH tSU; tSTA tSU; tDAT tHD; tDAT tRCL tRCL1 tFCL PARAMETER SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Setup Time Data Hold Time Rise Time of SCL Signal Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT Fall Time of SCL Signal TEST CONDITIONS MAX UNITS Standard mode 100 kHz Fast mode 400 kHz High-speed mode, CB - 100pF max 3.4 MHz High-Speed mode, CB - 400pF max 1.7 Rise Time of SDA Signal MHz 4.7 µs Fast mode 1.3 µs Standard mode 4.0 µs Fast mode 600 ns High-speed mode 160 ns Standard mode 4.7 µs Fast mode 1.3 µs High-speed mode, CB - 100pF max 160 ns High-speed mode, CB - 400pF max 320 ns Standard mode 4.0 µs Fast mode 600 ns High-speed mode, CB - 100pF max 60 ns High-speed mode, CB - 400pF max 120 ns Standard mode 4.7 µs Fast mode 600 ns High-speed mode 160 ns Standard mode 250 ns Fast mode 100 ns High-speed mode 10 Standard mode 0 3.45 µs Fast mode 0 0.9 µs High-speed mode, CB - 100pF max 0 70 ns High-speed mode, CB - 400pF max 0 150 ns Standard mode 20 ×0.1CB 1000 ns Fast mode 4 Fall Time of SDA Signal ns 20 ×0.1CB 300 ns High-speed mode, CB - 100pF max 10 40 ns High-speed mode, CB - 400pF max 20 80 ns Standard mode 20 ×0.1CB 1000 ns Fast mode 20 ×0.1CB 300 ns High-speed mode, CB - 100pF max 10 80 ns High-speed mode, CB - 400pF max 20 160 ns Standard mode 20 ×0.1CB 300 ns Fast mode 20 ×0.1CB 300 ns 10 40 ns High-speed mode, CB - 100pF max 20 80 ns Standard mode 20 ×0.1CB 1000 ns Fast mode 20 ×0.1CB 300 ns 10 80 ns High-speed mode, CB - 100pF max High-speed mode, CB - 400pF max tFDA TYP Standard mode High-speed mode, CB - 400pF max tRDA MIN 20 160 ns Standard mode 20 ×0.1CB 300 ns Fast mode 20 ×0.1CB 300 ns High-speed mode, CB - 100pF max 10 80 ns High-speed mode, CB - 400pF max 20 160 ns DAC6571 www.ti.com SLAS406 – DECEMBER 2003 TIMING CHARACTERISTICS (continued) SYMBOL PARAMETER tSU; tSTO Setup Time for STOP Condition CB Capacitive Load for SDA and SCL tSP Pulse Width of Spike Suppressed VNH VNL Noise Margin at the HIGH Level for Each Connected Device (Including Hysteresis) Noise Margin at the LOW Level for Each Connected Device (Including Hysteresis) TEST CONDITIONS MIN Standard mode 4.0 TYP MAX UNITS µs Fast mode 600 ns High-speed mode 160 ns 400 pF Fast mode 50 ns High-speed mode 10 ns Standard mode Fast mode 0.2VDD V 0.1VDD V High-speed mode Standard mode Fast mode High-speed mode 5 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 TYPICAL CHARACTERISTICS: VDD = +5 V At TA = +25°C, +VDD = +5 V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (-40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25 ° C ) 2 2 0 −1 0 −1 −2 0.5 DLE − LSB −2 0.5 0.25 0 −0.25 0.25 0 −0.25 −0.5 −0.5 0 128 256 384 512 640 Digital Input Code 768 896 VDD = 5 V at 25°C 1 LE − LSB LE − LSB DLE − LSB VDD = 5 V at −40°C 1 1024 0 128 256 384 512 640 Digital Input Code Figure 1. 16 VDD = 5 V, TA = 25°C VDD = 5 V at 105°C 1 LE − LSB 1024 TYPICAL TOTAL UNADJUSTED ERROR 2 0 Output Error (mV) 8 −1 −2 0.5 DLE − LSB 896 Figure 2. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105° C) 0.25 0 −8 0 −0.25 −16 0 −0.5 0 128 256 384 512 640 768 896 1024 128 256 384 512 640 Digital Input Code Digital Input Code Figure 4. ZERO-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 896 1024 30 VDD = 5 V VDD = 5 V 20 Full-Scale Error − mV 20 Zero-Scale Error − mV 768 Figure 3. 30 10 0 −10 −20 10 0 −10 −20 −30 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 T − Temperature − C Figure 5. 6 768 −30 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 T − Temperature − C Figure 6. DAC6571 www.ti.com SLAS406 – DECEMBER 2003 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. IDD HISTOGRAM SOURCE AND SINK CURRENT CAPABILITY 2500 5 VDD = 5 V DAC Loaded with 3FF 4 1500 1000 H 3 V O U T (V) f − Frequency − Hz 2000 2 500 1 DAC Loaded with 00 H 200 190 180 170 160 150 140 130 120 110 100 90 80 0 0 0 IDD − Supply Current − A 5 10 15 ISOURCE/SINK (mA) Figure 7. Figure 8. SUPPLY CURRENT vs CODE SUPPLY CURRENT vs TEMPERATURE 500 300 VDD = 5 V I DD − Supply Current − µ A I DD − Supply Current − µ A VDD = 5 V 400 300 200 100 250 200 150 100 50 0 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 T − Temperature − C 0 0H BH 80H 100H 180H 200H 280H 300H 380H 3F3H 3FFH Code Figure 9. Figure 10. SUPPLY CURRENT vs SUPPLY VOLTAGE POWER-DOWN CURRENT vs SUPPLY VOLTAGE 300 90 80 200 70 150 IDD (nA) I DD − Supply Current − µ A 100 250 100 60 +105°C 50 –40°C 40 30 50 20 0 2.7 3.2 3.7 4.2 4.7 VDD − Supply Voltage − V 5.2 5.7 +25°C 10 0 2.7 3.2 3.7 4.2 4.7 5.2 5.7 VDD (V) Figure 11. Figure 12. 7 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE FULL-SCALE SETTLING TIME CLK (5V/div) 2500 IDD (µA) 2000 VOUT (1V/div) 1500 1000 Full−Scale Code Change 00H to 3FF H Output Loaded with 2 KΩ and 200pF to GND 500 0 Time (1µs/div) 0 1 2 3 4 5 VLOGIC (V) Figure 13. Figure 14. FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME CLK (5V/div) CLK (5V/div) VOUT (1V/div) Full−Scale Code Change 1023 to 0 Output Loaded with 2 k and 200 pF to GND Half−Scale Code Change 256 to 768 Output Loaded with 2kΩ and 200pF to GND VOUT (1V/div) Time 1 s/div Time (1µs/div) Figure 15. Figure 16. HALF-SCALE SETTLING TIME POWER-ON RESET TO 0V C LK (5 V/div) H alf−S ca le C o de C ha nge 768 to 256 Loaded with 2kΩ to VDD. O utpu t Lo ad ed w ith 2kΩ an d 20 0pF to G N D VDD (1V/div) V O U T (1V /div) VOUT (1V/div) Time (1µs /d iv) Time (20µs/div) Figure 17. 8 Figure 18. DAC6571 www.ti.com SLAS406 – DECEMBER 2003 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. EXITING POWER-DOWN (512 Loaded) CODE CHANGE GLITCH Loa ded w ith 2 kΩ and 2 00p F to G N D . C ode C hang e: 512 to 511 VOUT (20mV/div) CLK (5V/div) VOUT (1V/div) Time (0.5 µs/div) Time (5µs/div) Figure 19. Figure 20. 9 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, +VDD = +2.7V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (-40 °C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25 °C) 2 VDD = 2.7 V at 25°C VDD = 2.7 V at −40°C 1 LE − LSB LE − LSB 2 0 −1 0 −1 −2 −2 0.5 DLE − LSB 0.5 DLE − LSB 1 0.25 0 −0.25 0.25 0 −0.25 −0.5 −0.5 0 128 256 384 512 640 768 896 0 1024 128 256 640 Figure 22. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105 °C) OUTPUT ERROR vs CODE (+25 °C) 768 896 1024 16 VDD = 2.7 V at 105°C 1 VDD = 2.7 V, TA = 25°C 0 8 −1 Output Error (mV) LE − LSB 512 Figure 21. 2 −2 0.5 DLE − LSB 384 Digital Input Code Digital Input Code 0.25 0 0 −8 −0.25 −0.5 0 128 256 384 512 640 Digital Input Code Figure 23. 10 768 896 1024 −16 0 128 256 384 512 640 Digital Input Code Figure 24. 768 896 1024 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, +VDD = +2.7V, unless otherwise noted. ZERO-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 30 30 VDD = 2.7 V VDD = 2.7 V 20 Full-Scale Error − mV Zero-Scale Erro − mV 20 10 0 −10 −20 10 0 −10 −20 −30 −50 −40 −30 −20 −10 0 −30 10 20 30 40 50 60 70 80 90 100 110 −50 −40−30 −20 −10 0 T − Temperature − C 10 20 30 40 50 60 70 80 90 100 110 T − Temperature − C Figure 25. Figure 26. IDD HISTOGRAM SOURCE AND SINK CURRENT CAPABILITY 3 2500 VDD = 2.7 V V D D = + 3V D AC Lo ad ed w ith 3FFH 2 1500 VOUT (V) f − Frequency − Hz 2000 1000 1 500 190 200 180 170 160 150 140 130 120 110 90 80 0 100 D AC Lo ade d w ith 000 H 0 IDD − Supply Current − A 0 5 10 15 I S O U R C E /S IN K (m A) Figure 27. Figure 28. SUPPLY CURRENT vs CODE SUPPLY CURRENT vs 9 TEMPERATURE 500 300 VDD = 2.7 V 250 I DD − Supply Current − µ A I DD − Supply Current − µ A VDD = 2.7 V 400 300 200 100 0 0H BH 80H 100H 180H 200H 280H 300H 380H 3F3H 3FFH Code Figure 29. 200 150 100 50 0 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 T − Temperature − C Figure 30. 11 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, +VDD = +2.7V, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE FULL SCALE SETTLING TIME 2500 C LK (2.7V /div) IDD (µA) 2000 1500 1000 F ull−S c ale C o de C h an ge 000 H to 3 FF H O utpu t L oad ed w ith 500 2 kΩ an d 200 pF to G N D V O U T (1V /div ) 0 Tim e (1 µ s/d iv ) 1 0 2 3 4 5 VLOGIC (V) Figure 31. Figure 32. FULL SCALE SETTLING TIME HALF SCALE SETTLING TIME CLK (2.7V/div) CLK (2.7V/div) Full−Scale Code Change 3FFH to 000H Output Loaded with 2kΩ and 200pF to GND VOUT (1V/div) Half−Scale Code Change 256 to 768 VOUT (1V/div) Output Loaded with 2 kΩ and 200 pF to GND Time (1 µs/div) Time (1µs/div) Figure 33. HALF SCALE SETTLING TIME Figure 34. POWER ON RESET 0 V POWER-ON RESET to 0V C LK (2.7V /div) H alf−Sca le C ode C ha nge 768 to 256 V O U T (1V/d iv) O u tp ut Lo aded w ith 2 kΩ and 200 pF to GND Time (1 µs/div) Figure 35. 12 Time (20µs/div) Figure 36. DAC6571 www.ti.com SLAS406 – DECEMBER 2003 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, +VDD = +2.7V, unless otherwise noted. EXITING-POWER DOWN (512 Loaded) CODE CHANGE GLITCH H Loa de d w ith 2k and 2 00pF to G N D . CLK (2.7V/div) C ode C hange : VOUT (1V/div) Time (5µs/div) Figure 37. VOUT (20mV/div) 512 to 511 Time (0.5 µs/div) Figure 38. 13 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 THEORY OF OPERATION D/A SECTION The architecture of the DAC6571 consists of a string DAC followed by an output buffer amplifier.Figure 39 shows a generalized block diagram of the DAC architecture. VDD 50 k 50 k 70 k _ Ref+ Resistor String Ref− DAC Register + VOUT GND Figure 39. R-String DAC Architecture The input coding to the DAC6571 is unsigned binary, which gives the ideal output voltage as: V OUT Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 1023. RESISTOR STRING The resistor string section is shown in Figure 40. It is basically a divide-by-2 resistor, followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the ouptupt amplifier by closing one of the switches connecting the string to the amplifier. Because the acrhitecture consists of a string of resistors, it is specified monotonic. To Output Amplifier VDD GND R R R R Figure 40. Typical Resistor String Output Amplifier The output buffer amplifier is a gain-of-2 amplifier, capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical characteristics curves. The slew rate is 1 V/µs with a half-scale settling time of 7 µs with the output unloaded. I2C Interface I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. 14 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 THEORY OF OPERATION (continued) The DAC6571 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-mode. The DAC6571 supports 7-bit addressing; 10-bit addressing and general call address are not supported. F/S-Mode Protocol • • • • The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 41. All I2C-compatible devices should recognize a start condition. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 42). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 43) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 41). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. HS-Mode Protocol • • • When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices. The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. SDA SDA SCL SCL S P Start Condition Stop Condition Figure 41. START and STOP Conditions 15 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 THEORY OF OPERATION (continued) SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 42. Bit Transfer on the I2C Bus Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgement START Condition Figure 43. Acknowledge on the I2C Bus Recognize START or REPEATED START Condition Recognize STOP or REPEATED START Condition Generate ACKNOWLEDGE Signal P SDA MSB Acknowledgement Signal From Slave Sr Address R/W SCL S or Sr START or Repeated START Condition 1 2 7 8 9 ACK 1 2 9 ACK Sr or P Clock Line Held Low While Interrupts are Serviced STOP or Repeated START Condition Figure 44. Bus Protocol 16 3-8 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 THEORY OF OPERATION (continued) DAC6571 I2C Update Sequence The DAC6571 requires a start condition, a valid I2C address, a control-MSB byte, and an LSB byte for a single update. After the receipt of each byte, DAC6571 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the DAC6571. The CTRL/MSB byte sets the operational mode of the DAC6571, and the 4 most significant bits. The DAC6571 then receives the LSB byte containing 6 least significant data bits. DAC6571 performs an update on the falling edge of the acknowledge signal that follows the LSB byte. For the first update, DAC6571 requires a start condition, a valid I2C address, a CTRL/MSB byte, an LSB byte. For all consecutive updates, DAC6571 needs a CTRL/MSB byte, and an LSB byte. Using the I2C high-speed mode (fscl= 3.4 MHz), the clock running at 3.4 MHz, each 10-bit DAC update other than the first update can be done within 18 clock cycles (CTRL/MSB byte, acknowledge signal, LSB byte, acknowledge signal), at 188.88 KSPS. Using the fast mode (fscl= 400 kHz), clock running at 400 kHz, maximum DAC update rate is limited to 22.22 KSPS. Once a stop condition is received, DAC6571 releases the I2C bus and awaits a new start condition. Address Byte MSB 1 LSB 0 0 1 1 0 A0 0 The address byte is the first byte received following the START condition from the master device. The first six bits (MSBs) of the address are factory preset to 100110. The next bit of the address is the device select bit A0. The A0 address input can be connected to VDD or digital GND, or can be actively driven by TTL/CMOS logic levels. The device address is set by the state of this pin during the power-up sequence of the DAC6571. Up to 2 devices (DAC6571) can be connected to the same I2C-Bus without requiring additional glue logic. Broadcast Address Byte MSB 1 LSB 0 0 1 0 0 0 0 Broadcast addressing is also supported by DAC6571. Broadcast addressing can be used for synchronously updating or powering down multiple DAC6571 devices. Using the broadcast address, DAC6571 responds regardless of the state of the address pin A0. Control - Most Significant Byte Most Significant Byte CTRL/MSB[7:0] consists of two zeros, two power-down bits, and four most significant bits of 10-bit unsigned binary D/A conversion data. Least Significant Byte Least Significant Byte LSB[7:0] consists of the 6 least significant bits of the 10-bit unsigned binary D/A conversion data, followed by 2 don't care bits. DAC6571 updates at the falling edge of the acknowledge signal that follows the LSB[0] bit. 17 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 Standard-and Fast-Mode: S SLAVE ADDRESS 0 A Ctrl/MS-Byte A LS-Byte A/A P Data Transferred (n* Words + Acknowledge) Word = 16 Bit ”0” (write) From Master to DAC6571 DAC6571 I2C-SLAVE ADDRESS: From DAC6571 to Master MSB A = A = S = Sr = P = LSB 1 Acknowledge (SDA LOW) Not Acknowledge (SDA HIGH) START Condition Repeated START Condition STOP Condition 0 0 1 1 0 A0 0 Factory Preset A0 = I2C Address Pin High-Speed-Mode (HS-Mode): F/S-Mode S HS-Mode HS-Master Code A Sr Slave Address 0 A Ctrl/MS-Byte HS-Mode Master Code: A/A P HS-Mode Continues Sr Slave Address MSB LSB 0 0 0 1 X X 0 Ctrl/MS-Byte: LS-Byte: MSB 0 A LS-Byte Data Transferred (n* Words + Acknowledge) Word = 16 Bit ”0” (write) 0 F/S-Mode 0 PD1 PD2 D9 D8 D7 LSB MSB D6 D5 LSB D4 D3 D2 D1 D0 X X D9 − D0 = Data Bits Figure 45. Master Transmitter Addressing DAC6571 as a Slave Receiver With a 7-Bit Address 18 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 POWER-ON RESET The DAC6571 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC register is filled with zeros and the output voltage is 0 V. It remains at a zero-code output until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up. POWER-DOWN MODES The DAC6571 contains four separate modes of operation. These modes are programmable via two bits (PD1 and PD0). Table 1 shows how the state of these bits correspond to the mode of operation. Table 1. Modes of Operation for the DAC6571 PD1 PD0 0 0 OPERATING MODE Normal Operation 0 1 1kΩ to AGND, PWD 1 0 100kΩ to AGND, PWD 1 1 High Impedance, PWD When both bits are set to 0, the device works normally with normal power consumption of 150 µA at 5V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while in power-down mode. There are three different options: The output is connected internally to AGND through a 1 kΩ resistor, a 100 kΩ resistor, or it is left open-circuited (high impedance). The output stage is illustrated in Figure 46. Amplifier Resistor String DAC VOUT Powerdown Circuitry Resistor Network Figure 46. Output Stage During Power-Down All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time required to exit power down is typically 2.5 µs for AVDD = 5 V and 5 µs for AVDD = 3V. See the Typical Characteristics for more information. CURRENT CONSUMPTION The DAC6571 typically consumes 150 µA at VDD = 5 V and 120 µA at VDD = 3 V. Additional current consumption can occur due to the digital inputs if VIH << VDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200 nA. DRIVING RESISTIVE AND CAPACITIVE LOADS The DAC6571 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset and gain error margins, the DAC6571 can operate rail-to-rail when driving a capacitive load. When the outputs of the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This may occur within approximately the top 20 mV of the DAC's digital input-to-voltage output transfer characteristic. 19 DAC6571 www.ti.com SLAS406 – DECEMBER 2003 OUTPUT VOLTAGE STABILITY The DAC6571 exhibits excellent temperature stability of 5 ppm/°C typical output voltage drift over the specified temperature range of the device. This enables the output voltage to stay within a ±25 µV window for a ±1°C ambient temperature change. Combined with good dc noise performance and true 10-bit differential linearity, the DAC6571 becomes a perfect choice for closed-loop control applications. APPLICATIONS USING REF02 AS A POWER SUPPLY FOR THE DAC6571 Due to the extremely low supply current required by the DAC6571, a possible configuration is to use a REF02 +5 V precision voltage reference to supply the required voltage to the DAC6571's supply input as well as the reference input, as shown in Figure 47. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V. The REF02 will output a steady supply voltage for the DAC6571. If the REF02 is used, the current it needs to supply to the DAC6571 is 140 µA typical. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total typical current required (with a 5 mW load on a given DAC output) is: 140 µA + (5 mW/5 V) = 1.14 mA. The load regulation of the REF02 is typically (0.005%×VDD)/mA, which results in an error of 0.285 mV for the 1.14 mA current drawn from it. This corresponds to a 0.05 LSB error for a 0 V to 5 V output range. 15 V REF02 5V 1.14 mA I2C Interface A0 SCL DAC6571 VOUT = 0 V to 5 V SDA Figure 47. REF02 as Power Supply to DAC6571 LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The power applied to VDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, VDD should be connected to a +5V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1 µF to 10 µF and 0.1 µF bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the +5V supply, removing the high-frequency noise. 20 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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