TI TP3067A

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
D
Complete PCM Codec and Filtering
Systems Include:
– Transmit High-Pass and Low-Pass
Filtering
– Receive Low-Pass Filter With (sin x)/x
Correction
– Active RC Noise Filters
– µ-Law or A-Law Compatible Coder and
Decoder
– Internal Precision Voltage Reference
– Serial I/O Interface
– Internal Autozero Circuitry
D
D
D
D
D
D
D
D
D
µ-Law – TP3064B and TP13064B
A-Law – TP3067B and TP13067B
± 5-V Operation
Low Operating Power . . . 70 mW Typ
Power-Down Standby Mode . . . 3 mW Typ
Automatic Power Down
TTL- or CMOS-Compatible Digital Interface
Maximizes Line Interface Card Circuit
Density
Improved Versions of National
Semiconductor TP3064, TP3067, TP3064-X,
TP3067-X
description
The TP3064A, TP3067A, TP13064A, and
TP13067A are comprised of a single-chip PCM
codec (pulse-code-modulated encoder and decoder) and PCM line filter. These devices provide
all the functions required to interface a full-duplex
(2-wire) voice telephone circuit with a TDM
(time-division-multiplexed) system. These devices are pin-for-pin compatible with the National
Semiconductor TP3064A and TP3067A, respectively. Primary applications include:
•
•
•
•
•
Line interface for digital transmission and
switching of T1 carrier, PABX, and central
office telephone systems
DW OR N PACKAGE
(TOP VIEW)
VPO+
ANLG GND
VPO –
VPI
VFRO
VCC
FSR
DR
BCLKR/CLKSEL
MCLKR/PDN
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VBB
VFXI+
VFXI –
GSX
ANLG LOOP
TSX
FSX
DX
BCLKX
MCLKX
Subscriber line concentrators
Digital-encryption systems
Digital voice-band data-storage systems
Digital signal processing
These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be
used at the analog termination of a PCM line or trunk. The devices require two transmit and receive master
clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that
are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP3064A, TP3067A, TP13064A, and TP13067A provide the band-pass filtering of the
analog signals prior to encoding and after decoding of voice and call progress tones. The TP3067A and
TP13067A contain patented circuitry to achieve low transmit channel idle noise and are not recommended for
applications in which the composite signals on the transmit side are below – 55 dBm0.
The TP3064A and TP3067A are characterized for operation from 0°C to 70°C. The TP13064A and TP13067A
are characterized for operation from – 40°C to 85°C.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the CMOS gates.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
functional block diagram
R2
17
Analog
Input
VFXI –
VFXI +
18 R1
19
ANLG
LOOP
Autozero
Logic
–
+
RC
Active Filter
R
VPO+
GSX
16
SwitchedCapacitor
Band-Pass Filter
S/H
DAC
–
1
+
R
VPO –
Transmit
Regulator
13
DX
OE
Comparator
–
3
A/D
Control
Logic
Voltage
Reference
+
RC Active
Filter
R3
4
VPI
SwitchedCapacitor
Low-Pass Filter
Receive
Regulator
S/H
DAC
8
DR
CLK
R4
5 VFRO
15
Timing and Control
5V
6
VCC
2
TSX
–5 V
20
VBB
11
2
ANLG GND
POST OFFICE BOX 655303
MCLKX
10
MCLKR/
PDN
• DALLAS, TEXAS 75265
12
9
7
14
BCLKX BCLKR/ FSR FSX
CLKSEL
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
ANLG GND
2
ANLG LOOP
16
Analog loopback control input. Must be set to logic low for normal operation. When pulled to logic high, the transmit
filter input is disconnected from the output of the transmit preamplifier and connected to VPO+ of the receive power
amplifier.
9
The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately,
can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode.
BCLKX is used for both transmit and receive directions (see Table 1).
12
The bit clock that shifts out the PCM data on DX. BCLKX can vary from 64 kHz to 2.048 MHz, but must be synchronous
with MCLKX.
BCLKR/CLKSEL
BCLKX
DR
8
DX
13
Analog ground. All signals are referenced to ANLG GND.
Receive data input. PCM data is shifted into DR following the FSR leading edge.
The 3-state PCM data output that is enabled by FSX.
FSR
7
Receive frame sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see Figures
1 and 2 for timing details).
FSX
14
Transmit frame sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
GSX
17
Analog output of the transmit input amplifier. GSX is used to externally set gain.
MCLKR/PDN
10
Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should
be synchronous for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal
timing. When MCLKR is connected continuously high, the device is powered down.
MCLKX
11
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR
TSX
15
Open-drain output that pulses low during the encoder time slot
VBB
VCC
20
Negative power supply. VBB = – 5 V ± 5%
6
Positive power supply. VCC = 5 V ± 5%
VFRO
5
Analog output of the receive filter
VFXI+
19
Noninverting input of the transmit input amplifier
VFXI –
18
Inverting input of the transmit input amplifier
VPI
4
Inverting input to the receive power amplifier. Also powers down both amplifiers when connected to VBB
VPO+
1
The noninverted output of the receive power amplifier
VPO –
3
The inverted output of the receive power amplifier
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Supply voltage, VBB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 7 V
Voltage range at any analog input or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3 V to VBB – 0.3 V
Voltage range at any digital input or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3 V to GND – 0.3 V
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: TP3064A, TP3067A . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TP13064A, TP13067A . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DW
1025 mW
8.2 mW/°C
656 mW
533 mW
N
1150 mW
9.2 mW/°C
736 mW
598 mW
recommended operating conditions (see Note 2)
MIN
NOM
MAX
UNIT
Supply voltage, VCC
4.75
5
5.25
V
Supply voltage, VBB
– 4.75
–5
– 5.25
V
High-level input voltage, VIH
2.2
Low-level input voltage, VIL
V
0.6
± 2.5
Common-mode input voltage range, VICR‡
Load resistance at GSX, RL
10
Load capacitance at GSX, CL
Operating free-air
free air temperature,
temperature TA
TP13064A, TP13067A
V
kΩ
50
TP3064A, TP3067A
V
0
70
– 40
85
pF
°C
‡ Measure with CMRR > 60 dB.
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current
PARAMETER
ICC
Supply current from VCC
IBB
Supply current from VBB
TEST CONDITIONS
Power down
TP306xA
MIN TYP†
MAX
TP1306xA
MIN TYP†
MAX
0.5
1
0.5
1.2
6
10
6
11
0.5
1
0.5
1.2
6
10
6
11
No load
Active
Power down
No load
Active
UNIT
mA
mA
† All typical values are at VCC = 5 V, VBB = – 5 V, and TA = 25°C.
electrical characteristics at VCC = 5 V ± 5%, VBB = –5 V ± 5%, GND at 0 V, TA = 25°C (unless otherwise
noted)
digital interface
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
DX
VOL
Low level output voltage
Low-level
IIH
IIL
High-level input current
Low-level input current
All digital inputs
IOZ
Output current in high-impedance state
DX
MIN
IH = – 3.2 mA
IL = 3.2 mA
DX
TSX
MAX
2.4
V
0.4
IL = 3.2 mA, Drain open
VI = VIH to VCC
0.4
VI = GND to VIL
VO = GND to VCC
UNIT
V
± 10
µA
± 10
µA
± 10
µA
MAX
UNIT
analog interface with transmit amplifier input
PARAMETER
TEST CONDITIONS
II
ri
Input current
VFXI+ or VFXI–
Input resistance
VFXI+ or VFXI–
ro
Output resistance
VI = – 2.5 V to 2.5 V
VI = – 2.5 V to 2.5 V
Closed loop,
Output dynamic range
GSX
AV
BI
Open-loop voltage amplification
VFXI+ to GSX
Unity-gain bandwidth
GSX
VIO
CMRR
Input offset voltage
VFXI+ or VFXI–
MIN
TYP†
± 200
10
Unit gain
nA
MΩ
1
RL ≥ 10 kΩ
3
Ω
± 2.8
V
5000
1
2
MHz
± 20
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio
† All typical values are at VCC = 5 V, VBB = – 5 V, and TA = 25°C.
mV
60
dB
60
dB
analog interface with receive filter
TYP†
MAX
1
3
Ω
VFRO to GND
500
pF
Output dc offset voltage
VFRO to GND
† All typical values are at VCC = 5 V, VBB = – 5 V, and TA = 25°C.
± 200
mV
PARAMETER
Output resistance
TEST CONDITIONS
VFRO = ± 2.5 V
Load resistance
Load capacitance
MIN
VFRO
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
Ω
600
5
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
analog interface with power amplifiers
PARAMETER
TEST CONDITIONS
II
ri
Input current
VPI = – 1 V to 1 V
Input resistance
VPI = – 1 V to 1 V
ro
Output resistance
VPO+ or VPO–
Inverting unity gain
AV
BI
Voltage amplification
VPO– or VPO+
VPO – = 1.77 Vrms,
Unity-gain bandwidth
VPO–
Open loop
VIO
Input offset voltage
TYP†
MAX
± 100
10
Ω
kHz
± 25
0 kHz to 4 kHz
60
4 kHz to 50 kHz
36
VPO – connected to VPI
RL
Load resistance
Connected from VPO+ to VPO –
CL
Load capacitance
† All typical values are at VCC = 5 V, VBB = – 5 V, and TA = 25°C.
POST OFFICE BOX 655303
mV
dB
Ω
600
100
• DALLAS, TEXAS 75265
nA
–1
400
Supply voltage rejection ratio of VCC or VBB
Supply-voltage
UNIT
MΩ
1
RL = 600 Ω
kSVR
6
MIN
pF
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
operating characteristics, over operating free-air temperature range VCC = 5 V ± 5%,
VBB = –5 V ± 5%, GND at 0 V, VI = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity
gain, noninverting (unless otherwise noted)
timing requirements
PARAMETER
TEST CONDITIONS
MCLX
and
MCLKR
MIN
TYP†
MAX
1.536
1.544
2.048
Depends on the device used and
BCLKX/CLKSEL
UNIT
fclock(M)
Frequency of master clock
fclock(B)
Frequency of bit clock, transmit
BCLKX
tr1
Rise time of master clock
MCLKX
and
MCLKR
Measured from 20% to 80%
50
ns
tf1
Fall time of master clock
MCLKX
and
MCLKR
Measured from 20% to 80%
50
ns
tr2
tf2
Rise time of bit clock, transmit
BCLKX
Measured from 20% to 80%
50
ns
Fall time of bit clock, transmit
BCLKX
Measured from 20% to 80%
50
ns
tw1
tw2
Pulse duration, MCLKX and MCLKR high
tsu1
tw3
tw4
64
Pulse duration, MCLKX and MCLKR low
Setup time, BCLKX high (and FSX in long-frame
sync mode) before MCLKX↓
First bit clock after the leading edge
of FSX
Pulse duration, BCLKX and BCLKR high
VIH = 2.2 V
VIL = 0.6 V
2.048
MHz
160
ns
160
ns
100
ns
160
ns
160
ns
th1
Hold time, frame sync low after bit clock low (long
frame only)
0
ns
th2
Hold time, BCLKX high after frame sync↑ (short
frame only)
0
ns
tsu2
Setup time, frame sync high before bit clock↓ (long
frame only)
80
ns
td1
td2
Pulse duration, BCLKX and BCLKR low
MHz
Load = 150 pF plus 2 LSTTL loads‡
Load = 150 pF plus 2 LSTTL loads‡
Delay time, BCLKX high to data valid
Delay time, BCLKX high to TSX low
td3
Delay time, BCLKX (or 8 clock FSX in long frame
only) low to data output disabled
td4
Delay time, FSX or BCLKX high to data valid (long
frame only)
tsu3
th3
CL = 0 pF to 150 pF
0
140
ns
140
ns
50
165
ns
20
165
ns
Setup time, DR valid before BCLKR↓
50
ns
Hold time, DR valid after BCLKR or BCLKX↓
50
ns
tsu4
Setup time, FSR or FSX high before BCLKR or
BCLKX↓
Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)
50
ns
th4
Hold time, FSX or FSR high after BCLKX or
BCLKR↓
Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)
100
ns
th5
Hold time, frame sync high after bit clock↓
Long-frame sync pulse (from 3- to
8-bit clock periods long)
100
ns
160
ns
tw5
Pulse duration of the frame sync pulse (low level)
64 kbps operating mode
† All typical values are at VCC = 5 V, VBB = – 5 V, and TA = 25°C.
‡ Nominal input value for an LSTTL load is 18 kΩ.
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
filter gains and tracking errors
TEST CONDITIONS‡
PARAMETER
Maximum peak transmit
overload level
MIN
TYP†
TP3064A, TP13064A
3.17 dBm0
2.501
TP3067A, TP13067A
3.14 dBm0
2.492
Transmit filter gain, absolute (at 0 dBm0)
TA = 25°C
f = 16 Hz
– 0.15
V
0.15
dB
– 30
f = 60 Hz
– 26
f = 200 Hz
Absolute transmit gain variation with
temperature and supply voltage
UNIT
– 40
f = 50 Hz
Transmit filter gain, relative to absolute
MAX
– 1.8
– 0.1
f = 300 Hz to 3000 Hz
– 0.15
0.15
f = 3300 Hz
– 0.35
0.05
f = 3400 Hz
– 0.8
0
f = 4000 Hz
– 14
f ≥ 4600 Hz (measure response from 0 Hz to 4000 Hz)
– 32
Relative to absolute transmit gain
– 0.1
dB
0.1
dB
Sinusoidal test method; Reference level = – 10 dBm0
Transmit gain tracking error with level
Receive filter gain, absolute (at 0 dBm0)
Receive filter gain,
gain relative to absolute
3 dBm0 ≥ input level ≥ – 40 dBm0
± 0.2
– 40 dBm0 > input level ≥ – 50 dBm0
± 0.4
– 50 dBm0 > input level ≥ – 55 dBm0
± 0.8
Input is digital code sequence for 0 dBm0 signal,
TA = 25°C
– 0.15
0.15
f = 0 Hz to 3000 Hz,
– 0.15
0.15
f = 3300 Hz
TA = 25°C
– 0.35
0.05
f = 3400 Hz
– 0.8
0
f = 4000 Hz
Absolute receive gain variation with temperature
and supply voltage
TA = full range,
dB
dB
dB
– 14
See Note 4
– 0.1
0.1
dB
3 dBm0 ≥ input level ≥ – 40 dBm0
± 0.2
dB
– 40 dBm0 > input level ≥ – 50 dBm0
± 0.4
– 50 dBm0 > input level ≥ – 55 dBm0
± 0.8
RL = 10 kΩ
± 2.5
V
± 0.25
dB
Sinusoidal test method; reference input PCM code
corresponds to an ideally encoded – 10 dBm0 signal
Receive gain
g
tracking
g error with level
Receive output drive voltage
Transmit and receive gain tracking error with
level (A-law, CCITT C712)
Pseudo-noise-test method; reference input PCM
code corresponds to an ideally encoded – 10 dBm0
signal
3 dBm0 ≥ input level ≥ – 40 dBm0
– 40 dBm0 > input level ≥ – 50 dBm0
± 0.3
– 50 dBm0 > input level ≥ – 55 dBm0
± 0.45
† All typical values are at VCC = 5 V, VBB = – 5 V, and TA = 25°C.
‡ Absolute rms signal levels are defined as follows: VI = 1.2276 V = 0 dBm0 = 4 dBm at f = 1.02 kHz with RL = 600 Ω.
NOTE 4: Full range for the TP3064A and TP3067A is 0°C to 70°C. Full range for the TP13064A and TP13067A is – 40°C to 85°C.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
envelope delay distortion with frequency
TYP†
MAX
UNIT
f = 1600 Hz
290
315
µs
f = 500 Hz to 600 Hz
195
220
f = 600 Hz to 800 Hz
120
145
f = 800 Hz to 1000 Hz
50
75
f = 1000 Hz to 1600 Hz
20
40
f = 1600 Hz to 2600 Hz
55
75
f = 2600 Hz to 2800 Hz
80
105
f = 2800 Hz to 3000 Hz
130
155
180
200
µs
µs
PARAMETER
Transmit delay, absolute (at 0 dBm0)
Transmit filter gain, relative to absolute
Receive delay, absolute (at 0 dBm0)
Receive delay, relative to absolute
TEST CONDITIONS
MIN
f = 1600 Hz
f = 500 Hz to 1000 Hz
– 40
– 25
f = 1000 Hz to 1600 Hz
– 30
– 20
f = 1600 Hz to 2600 Hz
70
90
f = 2600 Hz to 2800 Hz
100
125
f = 2800 Hz to 3000 Hz
† All typical values are at VCC = 5 V, VBB = – 5 V, and TA = 25°C.
140
175
TYP†
MAX
µs
noise
PARAMETER
TEST CONDITIONS
MIN
UNIT
Transmit noise, C-message weighted
TP3064A,
TP13064A
VFXI = 0 V
9
14
dBrnC0
Transmit noise, psophometric weighted
(see Note 5)
TP3067A,
TP13067A
VFXI = 0 V
– 78
– 75
dBm0p
Receive noise, C-message weighted
TP3064A,
TP13064A
PCM code equals alternating positive
and negative zero
2
4
dBrnC0
Receive noise, psophometric weighted
TP3067A,
TP13067A
PCM code equals positive zero
– 86
– 83
dBm0p
– 53
dBm0
Noise, single frequency
VFXI+ = 0 V,
f = 0 kHz to 100 kHz,
Loop-around measurement
† All typical values are at VCC = 5 V, VBB = – 5 V, and TA = 25°C.
NOTE 5: Measured by extrapolation from the distortion test result. This parameter is achieved through use of patented circuitry and is not
recommended for applications in which the composite signals on the transmit side are below – 55 dBm0.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
power supply rejection
PARAMETER
Positive power-supply rejection, transmit
TEST CONDITIONS
MIN
f = 0 Hz to 4 kHz
VCC = 5 V + 100 mVrms,
V
VFXI+ = – 50 dBm0
f = 0 Hz to 4 kHz
VBB = – 5 V + 100 mVrms,
V
VFXI+ = – 50 dBm0
38
µ-law
38
dB
dBC†
40
dB
A-law
35
µ-law
35
dB
dBC†
f = 4 kHz to 50 kHz
Positive power-supply rejection, receive
Negative power-supply rejection, receive
S urious out-of-band
Spurious
out of band signals at the
channel output (VFRO)
f = 0 Hz to 4 kHz
PCM code
d equals
l positive
iti zero,
VCC = 5 V + 100 mVrms
40
dB
A-law
40
µ-law
40
dB
dBC†
f = 4 kHz to 50 kHz
f = 0 Hz to 4 kHz
d equals
l positive
iti zero,
PCM code
VBB = – 5 V + 100 mVrms
UNIT
A-law
f = 4 kHz to 50 kHz
Negative power-supply rejection, transmit
MAX
40
dB
A-law
38
µ-law
38
dB
dBC†
40
dB
f = 4 kHz to 50 kHz
0 dBm0, 300-Hz to 3400-Hz input applied to DR
(measure individual image signals at VFRO)
– 30
f = 4600 Hz to 7600 Hz
– 33
f = 7600 Hz to 100 kHz
– 40
dB
dB
† The unit dBC applies to C-message weighting.
distortion
PARAMETER
TEST CONDITIONS
Signal to distortion ratio,
Signal-to-distortion
ratio transmit or receive half
half-channel
channel‡
MIN
Level = 3 dBm0
33
Level = 0 dBm0 to – 30 dBm0
36
Level = – 40 dBm0
Level = – 55 dBm0
Transmit
29
Receive
30
Transmit
14
Receive
15
Single-frequency distortion products, transmit
Single-frequency distortion products, receive
Loop-around measurement,
VFXI+ = – 4 dBm0 to – 21 dBm0,
Two frequencies in the range of 300 Hz to 3400 Hz
Intermodulation distortion
MAX
UNIT
dBC†
– 46
dB
– 46
dB
– 41
dB
Pseudo noise test method
Signal-to-distortion
g
ratio,, transmit half-channel ((A-Law))
(CCITT G.714)§
Signal-to-distortion
Si
l t di t ti ratio,
ti receive
i h
half-channel
lf h
l (A
(A-law)
l )
(CCITT G
G.714)§
714)§
Level = – 3 dBm0
33
Level = – 6 dBm0 to – 27 dBm0
36
Level = – 34 dBm0
33.5
Level = – 40 dBm0
28.5
Level = – 55 dBm0
13.5
Level = – 3 dBm0
33
Level = – 6 dBm0 to – 27 dBm0
36
Level = – 34 dBm0
34.2
Level = – 40 dBm0
30
dB
dB
Level = – 55 dBm0
15
† The unit dBC applies to C-message weighting.
‡ Sinusoidal test method (see Note 6)
§ Pseudo-noise test method
NOTE 6: The TP13064A and TP3064A are measured using a C-message filter. The TP13067A and TP3067A are measured using a
psophometric weighted filter.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
crosstalk
PARAMETER
TEST CONDITIONS
Crosstalk, transmit to receive
f = 300 Hz to 3000 Hz,
MIN
DR at steady PCM code
Crosstalk, receive to transmit (see Note 7)
VFXI = 0 V,
f = 300 Hz to 3000 Hz
† All typical values are at VCC = 5 V, VBB = – 5 V, and TA = 25°C.
NOTE 7: Receive-to-transmit crosstalk is measured with a – 50 dBm0 activation signal applied to VFXI+.
TYP†
MAX
UNIT
– 90
– 75
dB
– 90
– 72
dB
MIN
MAX
UNIT
power amplifiers
PARAMETER
TEST CONDITIONS
Balanced load,
Maximum 0 dBm0 rms level for better than ± 0.1 dB
linearity over the range if – 10 dBm0 to 3 dBm0
Signal/distortion
RL connected between VPO+ and VPO –
RL = 600 Ω
3.3
RL = 1200 Ω
3.5
RL = 30 kΩ
4
RL = 600 Ω
50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Vrms
dB
11
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
td2
TSX
td3
20%
20%
tr1
tw2
tf1
MCLKX
MCLKR
80%
fclock(M)
80%
80%
20%
20%
tsu1
tw1
80%
BCLKX
80%
20%
80%
1
2
3
4
5
6
7
8
20%
th2
tsu4
th4
FSX
20%
td3
td1
1
DX
2
3
4
5
6
80%
BCLKR
20%
1
2
3
4
5
6
80%
20%
7
7
8
8
80%
20%
20%
th2
tsu4
th4
FSR
80%
20%
tsu3
th3
th3
DR
1
2
3
4
5
Figure 1. Short-Frame Sync Timing
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6
7
8
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
tw1
tr1
fclock(M)
tf1
MCLKX
MCLKR
80%
20%
80%
20%
80%
20%
20%
tf2
tsu1
tw3
tr2
tsu1
tw4
80%
BCLKX
tw2
1
20%
80%
20%
2
80%
20%
80%
20%
3
th1
4
5
6
7
8
9
fclock(B)
th5
tsu2
80%
FSX
20%
td4
td1
td4
td3
DX
1
2
3
4
5
6
7
tw3
80%
80%
20%
20%
20%
td3
tw4
BCLKR
80%
8
20%
80%
20%
20%
th1
tsu2
FSR
th5
80%
20%
80%
tsu3
th3
DR
1
2
3
4
5
th3
6
7
8
Figure 2. Long-Frame Sync Timing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PRINCIPLES OF OPERATION
system reliability and design considerations
TP306xA, TP1306xA system reliability and design considerations are described in the following paragraphs.
latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TP306xA and TP1306xA devices are heavily protected against latch-up, it is still possible to
cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals.
Latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative
supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after power has
been applied but before the ground is connected. This can happen if the device is hot-inserted into a card with
the power applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted
into a system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V – 1N5711 or equivalent) between the
power supply and GND (see Figure 3). If it is possible that a TP306xA- or TP1306xA-equipped card that has
an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground
edge connector traces are longer than the power and signal traces so that the card ground is always the first
to make contact.
device power-up sequence
Latch-up can also occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1. Ensure that no signals are applied to the device before the power-up sequence is complete.
2. Connect GND.
3. Apply VBB (most negative voltage).
4. Apply VCC (most positive voltage).
5. Force a power down condition in the device.
6. Connect clocks.
7. Release the power down condition.
8. Apply FS synchronization pulses.
9. Apply the signal inputs.
When powering down the device, this procedure should be followed in the reverse order.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PRINCIPLES OF OPERATION
VCC
DGND
VBB
Figure 3. Latch-Up Protection Diode Connection
internal sequencing
Power-on reset circuitry initializes the TP3064A, TP3067A, TP13064A, and TP13067A devices when power
is first applied, placing it into the power-down mode. DX and VFRO outputs go into high-impedance states and
all nonessential circuitry is disabled. A low level or clock applied to MCLKR/PDN powers up the device and
activates all circuits. DX, a 3-state PCM data output, remains in the high-impedance state until the arrival of the
second FSX pulse.
synchronous operation
For synchronous operation, a clock is applied to MCLKX. MCLKR/PDN is used as a power-down control. A low
level on MCLKR powers up the device and a high level powers it down. In either case, MCLKX is selected as
the master clock for both receive and transmit direction. BCLKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done via BCLKR/CLKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL.
In the synchronous mode, BCLKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous
with MCLKX.
Table 1. Selection of Master-Clock Frequencies
BCLKR/CLKSEL
MASTER-CLOCK FREQUENCY SELECTED
TP3064A, TP13064A
TP3067A, TP13067A
Clock Input
1.536 MHz or 1.544 MHz
2.048 MHz
Logic Input L
(sync mode only)
2.048 MHz
1.536 MHz or 1.544 MHz
Logic Input H (open)
(sync mode only)
1.536 MHz or 1.544 MHz
2.048 MHz
The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the
enabled DX output on the rising edge of BCLKX. After eight bit-clock periods, the 3-state DX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via DR on the falling edge of BCLKX (or
BCLKR, if running). FSX and FSR must be synchronous with MCLKX and MCLKR.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PRINCIPLES OF OPERATION
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must
be 2.048 MHz for the TP3064A and TP13064A, 1.536 MHz or 1.544 MHz for the TP3067A and TP13067A and
need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This
is easily achieved by applying only static logic levels to MCLKR/PDN. This connects MCLKX to all internal
MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.
Each encoding cycle is started with FSX, and FSX must be synchronous with MCLKX and BCLKX. Each
decoding cycle is started with FSR, and FSR must be synchronous with BCLKR. The logic levels shown in
Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz.
short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing
relationships specified in Figure 1. With FSX high during a falling edge of BCKLX, the next rising edge of BCLKX
enables the 3-state output buffer, DX, which outputs the sign bit. The remaining seven bits are clocked out on
the following seven rising edges, and the next falling edge disables DX. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following
seven falling edges latch in the remaining bits. The short-frame sync pulse can be utilized in either the
synchronous or asynchronous mode.
long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships, as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a shortor long-frame sync pulse is being used. For 64-kHz operation, the frame sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLKX, which ever occurs later, enables the DX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the
remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever
occurs later, disables DX. A rising edge on FSR, the receive frame sync pulse, causes the PCM data at DR to
be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync
pulse may be used in either the synchronous or asynchronous mode.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PRINCIPLES OF OPERATION
transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors. The low noise and wide bandwidth characteristics of these devices provide gains in excess of 20 dB
across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter
followed by an eight-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. As per µ-law (TP3064A and TP13064A) or A-law (TP3067A
and TP13067A) coding conventions, the ADC is a companding type. A precision voltage reference provides an
input overload of nominally 2.5-V peak. The sampling of the filter output is controlled by the FSX frame sync
pulse. Then the successive-approximation encoding cycle begins. The 8-bit code is loaded into a buffer and
shifted out through DX at the next FSX pulse. The total encoding delay is approximately 290 µs. Any offset
voltage due to the filters or comparator is cancelled by sign bit integration (see Table 2).
Table 2. Encoding Format at DX Output
TP3064A, TP13064A
µ-Law
TP3067A, TP13067A
A-Law
(INCLUDES EVEN-BIT INVERSION)
VI = + Full scale
1 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0
VI = 0
1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
VI = – Full scale
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
receive section
The receive section consists of an expanding DAC that drives a fifth-order low-pass filter clocked at 256 kHz.
The decoder is µ-law (TP3064A and TP13064A) or A-law (TP3067A and TP13067A), and the fifth-order
low-pass filter corrects for the (sin x)/x attenuation caused by the 8-kHz sample/hold. The filter is followed by
a second-order RC active post filter with its output at VFRO. The receive section is unity gain, but gain can be
added by using the power amplifiers. At FSR, the data at DR is clocked in on the falling edge of the next eight
BCLKR (BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins and 10-µs later the
decoder DAC output is updated. The decoder delay is about 10 µs (decoder update) plus 110 µs (filter delay)
plus 62.5 µs (1/2 frame), or a total of approximately180 µs.
receive power amplifiers
Two inverting-mode power amplifiers are provided for directly driving a match-line interface transformer. The
gain of the first power amplifier can be adjusted to boost the ± 2.5-V peak output signal from the receive filter
up to the ± 3.3-V peak into an unbalanced 300-Ω load, or ± 4 V into an unbalanced 15-kΩ load. The second power
amplifier is internally connected in the unity-gain inverting mode to give 6 dB of signal gain for balanced loads.
Maximum power transfer to a 600-Ω subscriber line termination is obtained by differentially driving a balanced
transformer with √2:1 turns ratio, as shown in Figure 3. A total peak power of 15.6 dBm can be delivered to the
load plus termination.
POST OFFICE BOX 655303
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17
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
APPLICATION INFORMATION
power supplies
While the pins of the TP1306xA and TP306xA families are well protected against electrical misuse, it is
recommended that the standard CMOS practice be followed ensuring that ground is connected to the device
before any other connections are made. In applications where the printed-circuit board can be plugged into a
hot socket with power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to ANLG GND. This
minimizes the interaction of ground return currents flowing through a common bus impedance. VCC and VBB
supplies should be decoupled by connecting 0.1-µF decoupling capacitors to this common point. These bypass
capacitors must be connected as close as possible to VCC and VBB.
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation rather than via a ground bus. This common ground point should be decoupled to VCC
and VBB with 10-µF capacitors.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
APPLICATION INFORMATION
600 Ω
2
Hybrid
1
1
300 Ω
2
ZBAL
5V
–5 V
300 Ω
R2
0.1 µF
6
VCC
0.1 µF
GND
20
VBB
1
3
VPO+
VFXI +
VPO–
VFXI –
TP3064A
TP3067A
TP13064A
TP13067A
R3
4
VPI
R4
5
FSR
DR
BCLKR
MCLKR/PDN
19
18
R1
GSX
VFRO
7
8
9
10
17
16
15
14
13
12
11
ANLG LOOP
TSX
FSX
DX
BCLKX
MCLKX
NOTES: A. Transmit gain = 20 y log R1 + R2 , (R1 + R2) ≥ 10 kΩ
R2
B. Receive gain = 20 y log
2 × R3 , R4 ≥ 10 kΩ
R4
Figure 4. Typical Synchronous Application
POST OFFICE BOX 655303
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19
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