1 Chip CODEC for Digital Answering phone KS8620 INTRODUCTION 16-DIP-300 The KS8620 consists of on-chip PCM encoders, decoders (PCM CODECs) and PCM line filter. This device provide all the functions required to interface a fullduplex voice telephone circuit, digital answering phone. This device is designed to perform the transmit encoding and receive decoding as well as the transmit and receive 16-SOP-BD300 - SG filtering function in PCM system. Also it is intended to be used at the analog termination of a PCM line / trunk. This device provide the Band pass filtering of the analog signals prior to encoding and after decoding. This combination device performs the encoding and decoding of voice and call progress tones as well as the signaling and supervision information. ORDERING INFORMATION FEATURES Device Package KS8620N 16-DIP-300 KS8620D 16-SOP- BD300 - SG • Complete CODEC and filtering system • Encoding / Decoding : 8 bits µ-law PCM • On-chip auto zero, sample and hold, and precision voltage references • Low power dissipation : 60mW ( operating ) 3mW ( standby ) • + 5V operation • TTL or CMOS compatible • Automatic power down PIN CONFIGURATION V BB 1 16 VFI XI+ GNDA 2 15 VFXI- VF RO 3 14 GSX V CC 4 FS R 5 KS8620 13 TSX 12 FSX DR 6 11 DX BCLK R/CLKSEL 7 10 BCLK X MCLK R/PDN 8 9 MCLK X Operating Temperature 0oC ~ + 70oC 1 Chip CODEC for Digital Answering phone KS8620 BLOCK DIAGRAM R2 14 GSx Auto-zero logic VFxIR1 Analog In 15 - 16 + Switched Capacitor B.P.F RC Active Filter Sample & Hold DAC VFxI+ 11 Dx comparator Voltage Reference A/D Control Logic X’it register DE RC Active Filter 3 Switched Capacitor L.P.F Sample & Hold DAC Power Amplifier 6 DR Receive register CLK 13 /TSx 2 9 8 10 7 5 12 MCLKx MCLKR / PDN BCLKx BCLKR / CLKSEL FSR FSx 1 GNDA 4 VBB Timing and Control Vcc VFRO Fig 1. Block Diagram 1 Chip CODEC for Digital Answering phone KS8620 PIN DESCRIPTION Pin No Symbol Description 1 VBB VBB = -5V + 5% 2 GNDA Analog ground 3 VFRO Analog output of the receiver filter 4 VCC Vcc = +5V + 5% 5 FSR Receive frame sync pulse. 8KHz pulse train. 6 DR PCM data input 7 BCLKR / Logic input which selects either 1.536MHz / 1.544MHz or 2.048MHz for master CLKSEL clock in normal operation and BCLKx is used for both TX and RX directions. Alternately direct clock input available, vary from 64KHz to 2.048MHz. 8 MCLKR / When MCLKR is connected continuously high, the device goes powered down . PDN Normally connected continuously low, MCLKx is selected for all DAC timing. Alternately direct 1.536MHz / 1.544MHz or 2.048MHz clock input is available. 9 MCLKX 1.536MHz / 1.544MHz or 2.048MHz clock input is available 10 BCLKX May be vary from 64KHz 2.048MHz, but BCLKx is externally tied with MCLKx in normal operation. 11 DX PCM data output. 12 FSX TX frame sync pulse. 8KHz pulse train. 13 TSX Changed from high to low during the encoder timeslot. Open drain output. 14 GSX Analog output of the TX input amplifier. Used to set gain through external resistor between pin 14 to pin 15. 15 VFXI- Inverting input stage of the TX analog signal. 16 VFXI+ Non-inverting input stage of the TX analog signal. ABSOLUTE MAXIMUM RATINGS ( Ta = 25 oC) Characteristic Symbol Value Unit Positive Supply Voltage Vcc +7 V Negative Supply Voltage VBB -7 V Voltage at any Analog Input or Output V I (A) Vcc + 0.3 to VBB - 0.3 V Voltage at any Digital Input or Output V I (D) Vcc + 0.3 to GNDA - 0.3 V Operating Temperature Range Ta 0 to 70 oC Storage Temperature Range TSTG -65 to +150 oC Lead Temperature Range ( soldering , 10 sec ) TLEAD 300 oC 1 Chip CODEC for Digital Answering phone KS8620 ELECTRICAL CHARACTERISTICS (Unless otherwise specified : Ta = 0oC to 70oC , Vcc = 5V +5%, VBB = -5V +5%, GNDA = 0V ) Characteristic System Test Conditions Min Typ Max Unit mA Power Dissipation Power down Current Active Current I CC ( down ) No Load 0.5 3.0 I BB ( down ) No Load 0.05 1.0 I CC ( A ) No Load 6.0 10 I BB ( A ) No Load 6.0 10 mA Digital Interface Input Low Voltage V IL Input High Voltage V IH Input Low Current I IL GNDA < VIN < VIL , all digital input -15 15 uA Input High Current I IH VIH < VIN < Vcc -15 15 uA DX , IL = 3.2 mA 0.4 V SIGR , IL = 1.0 mA 0.4 /TSX , IL = 3.2 mA , open drain 0.4 Output Low Voltage Output High Voltage Output Current in High 0.6 2.2 V OL V OH I OH (HZ) DX , IH = -3.2 mA 2.4 SIGR , IH = -1.0 mA 2.4 DX , GNDA < VO < Vcc -15 V V V 15 uA 3 Ω impedance state ( Tri - state ) Analog Interface with Receiver Filter Output Resistance RO pin VFRO Load Resistance RL VFRO = + / - 2.5V Load Capacitance CL Output DC offset voltage V OO(RX) 1 Ω 600 500 pF -200 200 mV 200 nA Analog Interface with Transmit input Amp I LKG -2.5V< V<+2.5V , VFXI+ or VFXI- -200 Input Resistance RI -2.5V< V<+2.5V , VFXI+ or VFXI- 10 Output Resistance RO closed loop , unity gain Load Resistance RL GSx Load Capacitance CL GSx V OD(TX) GSx , RL < 10KΩ +/-2.8 V Voltage Gain GV VFXI+ to GSx 5,000 V/V Unity Gain bandwidth BW 1 Offset Voltage V IO(TX) -20 20 mV Common - mode Voltage V CM(TX) CMRRXA > 60dB -2.5 2.5 V Common mode rejection ratio CMRR DC test 55 dB Power supply rejection ratio PSRR DC test 55 dB Input Leakage Current Output Dynamic Range MΩ 1 3 10 Ω KΩ 50 2 pF MHz 1 Chip CODEC for Digital Answering phone KS8620 TIMING CHARACTERISTICS (Unless otherwise specified : Ta = 0oC to 70oC, Vcc = 5V +5%, VBB = -5V +5%, GNDA = 0V ) Characteristic System Test Conditions Min Typ Frequency of Master Clock fMCK Depends on the device used 1.536 and the BCLKR /CLKSEL pin. 1.544 MCLKx and MCLKR 2.048 Max Unit MHz Rise time of Bit Clock tR(BCK) tPB = 488ns 50 nS Fall Time of Bit Clock tF(BCK) tPB = 488ns 50 nS Hold Time for Bit Clock tH(LFS) Long Frame only 0 nS tH(HFS) Short Frame only 0 nS tSU(FBCL) Long Frame only 80 nS tD(HDV) Load = 150pF + 2 LSTTL loads 0 Delay time to /TSx low tD(/TSXL) Load = 150pF + 2 LSTTL loads Delay time from BCLKx tD(LDD) low to Frame sync Hold Time for Bit Clock High to Frame sync Set-up Time from Frame sync to Bit Clock low Delay time from BCLKx 180 nS 140 nS 50 165 nS 20 165 nS High to data valid low to data output disable Delay Time to valid data tD(VD) from FSx or BCLKx. Set-up Time from DR valid CL = 0 pF to 150 pF Whichever comes later. tSU(DRBL) 50 nS tH(BLDR) 50 nS 50 nS to BCLK x/R low Hold time from BCLK x/R low to DR invalid Set-up time from FS x/R to tSU(FBLS) BCLK x/R low Short Frame sync pulse ( 1 or 2 bit clock periods long ) : note1 Width of master clock High tW(MCKH) MCLKx and MCLKR 160 nS Width of master clock Low tW(MCKL) MCLKx and MCLKR 160 nS Rise Time of Master clock tR(MCK) MCLKx and MCLKR 50 nS Fall Time of Master clock tF(MCK) MCLKx and MCLKR 50 nS Set-up time from BCLKx High tSU(BHMF) 1`st bit clock after the leading ( FSx in Long Frame Sync edge of FSx 50 nS mode ) to MCLKx falling edge Period of Bit Clock tCK 485 488 15,725 nS Width of Bit clock High tW(BCKH) VIH = 2.2V 160 nS Width of Bit clock Low tW(BCKL) VIL = 0.6V 160 nS Hold time from BCLK x/R tH(BLFL) Short Frame sync pulse ( 1 or 2 bit 100 nS to FS x/R low clock periods long ) : note1 1 Chip CODEC for Digital Answering phone KS8620 TRANSMISSION CHARACTERISTICS (Unless otherwise specified : Ta = 0oC to 70oC, Vcc = 5V +5%, VBB = -5V +5%, GNDA = 0V, f = 1.02KHz Vin = 0dBm0, transmit input amplifier connected for unity-gain, non-inverting ) Characteristic System Test Conditions Min Ta=25oC,VCC = 5V, VBB = -5V Typ Max Unit -1.5 1.5 dB f = 0Hz to 3000Hz -0.6 0.5 dB f = 3300Hz -0.55 0.5 f = 3400Hz -1.5 1.5 Amplitude Response Receive Gain, Absolute GV(ARX) Input = Digital code sequence for 0dBm0 signal at 1020Hz Receive Gain, Relative GV(RRX) to Gv(RRX) f = 4000Hz Absolute Receive Gain Variations with temperature Receive Gain ∆ GV(ARX) Ta = 0oC to 70oC + 0.1 dB dB /∆ T ∆ GV(RXL) Sinusoidal test method; reference input PCM code correspond to an Variations with level ideally encoded -10dBm0 signal Receive output drive level Absolute level VO(RX) VAL PCM level = -40dBm0 to +3dBm0 -0.4 0.4 PCM level = -50dBm0 to -40dBm0 -0.8 0.8 RL = 600Ω -2.5 2.5 Norminal 0dBm0 level is same as V 1.2276 Vrms 2.501 VPK 4 dBm ( 600Ω ) Max overload level VOL(MAX) Max overload level ( 3.17dBm0) Transmit gain, absolute GV(ATX) Ta = 25oC,Vcc =5V, VBB = -5V -1.5 1.5 dB f = 16 Hz -35 dB f = 50 Hz -25 f = 60 Hz -21 Input at GSx = 0dBm0 at 1020Hz Transmit gain, relative to GV(ATX) GV(RTX) f = 200 Hz -2 -0.5 f = 300 Hz - 3000Hz -0.5 0.5 f = 3300 Hz -0.55 0.5 f = 3400 Hz -1.5 -1.5 f = 4000 Hz -10 f = 4600 Hz and above, -25 mesaure response from 0 Hz to 4 KHz 1 Chip CODEC for Digital Answering phone KS8620 TRANSMISSION CHARACTERISTICS ( Continued ) Characteristic Absolute trasmit gain variations with temperature Transmit gain System ∆ GV(ATX) Test Conditions Min Max Unit + 0.1 dB -0.4 0.4 dB -0.8 0.8 Ta = 0oC to 70oC Typ /∆ T ∆ GV(TXL) variations with level Sinusoldal test method ; Reference level = -10dBm0 VFXI + = -40dBm0 to +3dB0 VFXI + = -50dBm0 to -40dB0 Envelope Delay Distortion with Frequency Receive Delay, Absolute tD(ARX) f = 1600Hz Receive Delay, Relative to tD(RRX) f = 500Hz - 1000Hz -40 f = 1000Hz - 1600Hz -30 tD (ARX) 200 µs µs f = 1600Hz - 2600Hz 90 f = 2600Hz - 2800Hz 125 f = 2800Hz - 3000Hz 175 Transmit Delay, Absolute tD(ATX) f = 1600Hz 315 µs Transmit Delay, Relative to tD(RTX) f = 500Hz - 600Hz 220 µs f = 600Hz - 800Hz 145 f = 800Hz - 1000Hz 75 f = 1000Hz - 1600Hz 40 f = 1600Hz - 2600Hz 75 f = 2600Hz - 2800Hz 105 f = 2800Hz - 3000Hz 155 tD(ATX) Noise Receive Noise, NRXC C Message Weighted Transmit Noise, C Message Weighted PCM code equals alternating 18 dBrnC0 15 dBrnC0 positive and negative zero, KS8620 NTXC KS8620 1 Chip CODEC for Digital Answering phone KS8620 TRANSMISSION CHARACTERISTICS ( Continued ) Characteristic Noise, Single Frequency System NSF Test Conditions Min f = 0KHz to 100KHz, loop around Typ Max -53 measurement, VFXI+ = 0Vrms Positive Power Supply PSRR(PTX) VFXI+ = 0 Vrms, Unit dBm0 25 dBC 25 dBC f = 0Hz - 4000Hz 25 dBC f = 4KHz - 25KHz 25 dB f = 0Hz - 4000Hz 25 dBC f = 4KHz - 25KHz 25 dB Vcc = 5.0 VDC + 100mVms Rejection, Transmit f = 0KHz - 50KHz Negative Power Supply PSRR(NTX) VFXI+ = 0 Vrms, VBB = -5.0 VDC + 100mVrms Rejection, Transmit f = 0KHz - 50KHz Positive Power Supply PSRR(PRX) PCM code equals positive zero Vcc = 5.0VDC + 100mVrms Rejection, Receive PCM code equals positive zero Negative Power Supply PSRR(NRX) Rejection, Receive Spurious Out-Band Signals SOS VBB = -5.0VDC + 100mVrms Loop around measurement, 0dBm0, 300Hz - 3400Hz input PCM applied at the Channel Output to DR , Measure individual image signals at VFRO 4600Hz -7600Hz -28 7600Hz - 100,000Hz -35 dB Distortion Signal to Total Distortion THDTX Sinusoidal test method ; Transmit or Receive THDRX level = 3.0dBm0 28 = 0dBm0 to 30dBm0 30 = -40dBm0 XMT 25 RCV 25 Half-Channel dBC 1 Chip CODEC for Digital Answering phone KS8620 TRANSMISSION CHARACTERISTICS ( Continued ) Characteristic System Test Conditions Min Typ Single Frequency Disotrtion, THDSF(TX) Max Unit -41 -dB -41 -dB -35 -dB -90 -75 dB -90 -70 dB Transmit Single Frequency Distortion, THDSF(RX) Receive Intermodulation Distortion THDIMD Loop around measurement, VFXI+ = -4dBm0 to -21dBm0, two frequencies in the range 300Hz - 3400Hz Crosstalk Transmit to Receive CT(TX-RX) Crosstalk, 0dBm0 f = 300Hz - 3400Hz DR = Steady PCM code Transmit level Reveive to Transmit CT(RX-TX) Crosstalk, 0dBm0 f = 300Hz - 3400Hz, VFXI = 0V (note1) Receive level Note 1. CT(RX-TX) is measured with a -40dBm0 activating signal applied at VFXI+ ENCODING FORMAT AT D X OUTPUT µ -Law PCM : KS8620 VIN ( at GSX ) = + Full Scale 1 0 0 0 0 0 0 0 VIN ( at GSx ) = 0V 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 VIN ( at GSx ) = - Full Scale 0 0 0 0 0 0 0 0