FUJITSU SEMICONDUCTOR FACT SHEET NP501-00026-0v01-E FRAM MB85R4M2T The MB85R4M2T is an FRAM chip consisting of 262,144 words×16 bits of nonvolatile memory cells fabricated using ferroelectric process and CMOS process technologies. The MB85R4M2T uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM. ■ FEATURES • Bit configuration • LB and UB data byte control • Read/write endurance • Data retention • Operating power supply voltage • Low power operation • Operation ambient temperature range • Package : 262,144 words×16 bits : Available Configuration of 524,288 words × 8 bits : 1013 times / 16 bits : 10 years (+85 °C) : 1.8V to 3.6V : Operating power supply current 20 mA (Max) Standby current 150 μA (Max) Sleep current 20 μA (Max) : -40 °C to +85 °C : 44-pin plastic TSOP (FPT-44P-M34) RoHS compliant ■ ORDERING INFORMATION Product name Package Shipping form MB85R4M2TFN-G-ASE1 44-pin plastic TSOP (FPT-44P-M34) Tray ■ OUTLINE OF PACKAGE Plastic TSOP, 44-pin (FPT-44P-M34) November 2013 1/2 Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB85R4M2T PRELIMINARY ■ PIN ASSIGNMENT (TOP VIEW) A4 A3 A2 A1 A0 /CE I/O0 I/O1 I/O2 I/O3 VDD VSS I/O4 I/O5 I/O6 I/O7 /WE A17 A16 A15 A14 A13 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A5 A6 A7 /OE /UB /LB I/O15 I/O14 I/O13 I/O12 VSS VDD I/O11 I/O10 I/O9 I/O8 /ZZ A8 A9 A10 A11 A12 Pin name A0 to A17 Description Address Input pins I/O0 to I/O15 /CE Data Input / Output pins /WE Write Enable Input pin /OE Output Enable Input pin /ZZ Sleep Mode Input pin /LB, /UB Chip Enable Input pin Lower/Upper byte Control Input pins VDD Supply Voltage pin VSS Ground pin FPT-44P-M34 ■ BLOCK DIAGRAM Address Row Decoder A0 to A17 /ZZ /WE Control circuits /CE FRAM Array 262,144×16 Column Decoder / Sense Amp. / Write Amp. /OE I/O0 to I/O15 /UB /LB NP501-00026-0v01-E November 2013 2/2 Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved