LT3959 Wide Input Voltage Range Boost/SEPIC/Inverting Converter with 6A, 40V Switch DESCRIPTION FEATURES n n n n n n n n n n n Wide VIN Range: 1.6V (2.5V Start-Up) to 40V Positive or Negative Output Voltage Programming with a Single Feedback Pin PGOOD Output Voltage Status Report Internal 6A/40V Power Switch Programmable Soft-Start Programmable Operating Frequency (100kHz to 1MHz) with One External Resistor Synchronizable to an External Clock Low Shutdown Current < 1μA INTVCC Regulator Supplied from VIN or DRIVE Programmable Input Undervoltage Lockout with Hysteresis Thermally Enhanced QFN (5mm × 6mm) Package The LT®3959 is a wide input range, current mode, DC/DC controller which is capable of regulating either positive or negative output voltages from a single feedback pin. It can be configured as a boost, SEPIC or inverting converter. It features an internal low side N-channel MOSFET rated for 6A at 40V and driven from an internal regulated supply provided from VIN or DRIVE. The fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. The operating frequency of LT3959 can be set over a 100kHz to 1MHz range with an external resistor, or can be synchronized to an external clock using the SYNC pin. The LT3959 features soft-start and frequency foldback functions to limit inductor current during start-up and output short-circuit. A window comparator on the FBX pin reports via the PGOOD pin, providing output voltage status indication. APPLICATIONS n n n Automotive Telecom Industrial L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7825665. TYPICAL APPLICATION 2.5V to 24V Input, 12V Output SEPIC Converter Excellent for Automotive 12V Post Regulator Efficiency vs Output Current 100 L1A CIN 22μF 50V ×2 VIN 124k SW L1B EN_UVLO 150k 121k LT3959 COUT 47μF 16V ×2 VOUT 12V 500mA AT VIN = 2.5V 1.5A AT VIN > 8V GND DRIVE 105K 80 75 60 0 FBX SS VC 0.1μF 85 65 SYNC RT 27.4k 300kHz 90 70 PGOOD TIE TO SGND IF NOT USED VIN = 12V 95 EFFICIENCY (%) VIN 2.5V TO 24V 4.7μF 50V SGND GNDK INTVCC 7.5k 22nF 800 600 200 400 OUTPUT CURRENT (mA) 1000 3959 TA01b 15.8K 4.7μF 3959 TA01a 3959f 1 LT3959 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) VC FBX SS RT SYNC PGOOD INTVCC TOP VIEW 36 35 34 33 32 31 30 NC 1 28 DRIVE NC 2 27 VIN SGND 37 NC 3 SGND 4 25 EN/UVLO 24 SGND 23 NC NC 6 SW 38 SW 8 SW 9 21 SW 20 SW NC 10 GND GND GND GND GND 12 13 14 15 16 17 GNDK VIN ............................................................................40V EN/UVLO (Note 2) .....................................................40V DRIVE .......................................................................40V PGOOD ......................................................................40V SW ............................................................................40V INTVCC ........................................................................8V SYNC ..........................................................................8V VC, SS .........................................................................3V RT ............................................................................1.5V GND, GNDK to SGND .............................................±0.3V FBX ................................................................. –3V to 3V Operating Junction Temperature Range (Note 3) LT3959E/LT3959I .............................. –40°C to 125°C Storage Temperature Range .................. –65°C to 125°C UHEMA PACKAGE 36-LEAD (5mm × 6mm) PLASTIC QFN TJMAX =125°C, θJA = 42°C/W, θJC = 3°C/W EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3959EUHE#PBF LT3959EUHE#TRPBF 3959 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C LT3959IUHE#PBF LT3959IUHE#TRPBF 3959 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3959f 2 LT3959 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, EN/UVLO = 12V, INTVCC = 4.75V, unless otherwise noted. PARAMETER CONDITIONS MIN l VIN Operating Voltage VIN Start-Up Voltage RT = 27.4kΩ, FBX = 0 VIN Shutdown IQ EN/UVLO < 0.4V EN/UVLO = 1.15V TYP 1.6 l VIN Operating IQ MAX UNITS 40 V 2.5 2.65 V 0.1 1 6 μA μA 350 450 μA DRIVE Shutdown Quiescent Current EN/UVLO < 0.4V EN/UVLO = 1.15V 0.1 0.1 1 2 μA μA DRIVE Quiescent Current (Not Switching) RT = 27.4kΩ, DRIVE = 6V 2.0 2.5 mA 7.0 8.0 A l SW Pin Current Limit SW Pin On Voltage ISW = 3A SW Pin Leakage Current SW = 40V 6.0 100 mV 5 μA 1.6 –0.80 1.620 –0.785 V V 80 130 10 nA nA Error Amplifier FBX Regulation Voltage (VFBX(REG)) FBX > 0V FBX < 0V FBX Pin Input Current FBX = 1.6V FBX = –0.8V Transconductance gm (ΔIVC/ΔVFBX ) l l 1.580 –0.815 –10 FBX = VFBX(REG) VC Output Impedance 240 μs 5 MΩ FBX Line Regulation [ΔVFBX(REG)/(ΔVIN • VFBX(REG))] 1.6V < VIN < 40V, FBX >0 1.6V < VIN < 40V, FBX <0 0.02 0.02 VC Source Current FBX = 0V, VC = 1.3V –13 μA VC Sink Current FBX = 1.7V, VC = 1.3V FBX = –0.85V, VC = 1.3V 13 10 μA μA 0.05 0.05 %/V %/V Oscillator Switching Frequency RT = 27.4k to SGND, VFBX = 1.6V RT = 86.6k to SGND, V FBX = 1.6V RT = 6.81k to SGND, VFBX = 1.6V RT Voltage FBX = 1.6V, –0.8V l 250 300 100 1000 340 1.13 kHz kHz kHz V SW Minimum Off-Time 150 200 ns SW Minimum On-Time 150 200 ns 3959f 3 LT3959 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, EN/UVLO = 12V, INTVCC = 4.75V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS SYNC Input Low l SYNC Input High l 1.5 SS = 0V, Current Out of Pin l –14 –10.5 –7 μA DRIVE LDO Regulation Voltage DRIVE = 6V, Not Switching l 4.6 4.75 4.9 V VIN LDO Regulation Voltage DRIVE = 0V, Not Switching l 3.6 3.75 3.9 V DRIVE LDO Current Limit INTVCC = 4V 60 mA VIN LDO Current Limit DRIVE = 0V, INTVCC = 3V 60 mA SS Pull-Up Current 0.4 V V Low Dropout Regulators (DRIVE LDO and VIN LDO) DRIVE LDO Load Regulation (ΔVINTVCC/VINTVCC) 0 < IINTVCC < 20mA, DRIVE = 6V –1 –0.6 % VIN LDO Load Regulation (ΔVINTVCC/VINTVCC) DRIVE = 0V, 0 < IINTVCC < 20mA –1 –0.6 % DRIVE LDO Line Regulation [ΔVINTVCC/(VINTVCC • ΔVIN)] 1.6V < VIN < 40V, DRIVE = 6V 0.03 0.07 %/V 0.03 0.07 %/V VIN LDO Line Regulation [ΔVINTVCC/(VINTVCC • ΔVIN)] DRIVE = 0V, 5V < VIN < 40V DRIVE LDO Dropout Voltage (VDRIVE – VINTVCC) DRIVE = 4V, IINTVCC = 20mA l 190 400 mV VIN LDO Dropout Voltage (VIN – VINTVCC) VIN = 3V, DRIVE = 0V, IINTVCC = 20mA l 190 400 mV V INTVCC Undervoltage Lockout Threshold Falling l 1.85 2.0 2.15 INTVCC Undervoltage Lockout Threshold Rising l 2.15 2.3 2.45 INTVCC Current in Shutdown EN/UVLO = 0V 25 V μA Logic l EN/UVLO Threshold Voltage Falling 1.17 EN/UVLO Threshold Voltage Rising Hysteresis 1.22 1.27 20 V mV EN/UVLO Input Low Voltage IVIN < 1μA EN/UVLO Pin Bias Current Low EN/UVLO = 1.15V EN/UVLO Pin Bias Current High EN/UVLO = 1.30V FBX Power Good Threshold Voltage FBX > 0V, PGOOD Falling FBX < 0V, PGOOD Falling VFBX(REG) – 0.08 VFBX(REG) + 0.04 V V FBX Overvoltage Threshold FBX > 0V, PGOOD Rising FBX < 0V, PGOOD Rising VFBX(REG) + 0.12 VFBX(REG) – 0.06 V V PGOOD Output Low (VOL) I PGOOD = 250μA PGOOD Leakage Current PGOOD = 40V 1.8 0.4 V 2.2 2.6 μA 10 100 nA 210 300 mV 1 μA INTVCC Minimum Voltage to Enable PGOOD Function l 2.5 2.7 2.9 V INTVCC Minimum Voltage to Enable SYNC Function l 2.5 2.7 2.9 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: For VIN below 4V, the EN/UVLO pin must not exceed VIN for proper operation. Note 3: The LT3959E is guaranteed to meet performance specifications from the 0°C to 125°C operating junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3959I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 4: The LT3959 is tested in a feedback loop which servos VFBX to the reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V. 3959f 4 LT3959 TYPICAL PERFORMANCE CHARACTERISTICS FBX Positive Regulation Voltage vs Temperature TA = 25°C, unless otherwise noted. FBX Negative Regulation Voltage vs Temperature Quiescent Current vs Temperature –0.78 1.62 2.4 1.61 1.60 1.59 1.58 –50 –25 25 50 75 0 TEMPERATURE (°C) 100 125 –0.79 1.6 IQ (mA) FBX REGULATION VOLTAGE (V) FBX REGULATION VOLTAGE (V) IQ (DRIVE) 2.0 –0.80 0.8 –0.81 –0.82 –50 –25 25 50 75 0 TEMPERATURE (°C) 100 100 NORMALIZED FREQUENCY (%) 60 RT (k) IQ (mA) 125 120 70 IQ (DRIVE) 10 50 40 30 5 20 0 0 800 600 200 400 SWITCHING FREQUENCY (kHz) 1000 80 60 40 20 0 –0.8 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) 3959 G04 275 8.0 7.4 7.5 7.2 7.0 6.8 125 6.4 –50 7.0 6.5 6.0 5.5 –25 0 25 50 75 100 125 TEMPERATURE (°C) 3959 G07 1.6 1.2 SW Current Limit vs Duty Cycle 7.6 6.6 100 0.8 0.4 3959 G06 SW CURRENT LIMIT (A) SW CURRENT LIMIT (A) 300 0 FBX VOLTAGE (V) SW Current Limit vs Temperature 350 325 –0.4 3959 G05 Switching Frequency vs Temperature 25 50 75 0 TEMPERATURE (°C) 100 10 IQ (VIN) SWITCHING FREQUENCY (kHz) 100 90 15 –25 25 50 75 0 TEMPERATURE (°C) Normalized Switching Frequency vs FBX Voltage 80 250 –50 –25 3959 G03 RT vs Switching Frequency 20 0 0.0 –50 125 3959 G02 Dynamic Quiescent Current vs Switching Frequency DRIVE = 6V IQ (VIN) 0.4 3959 G01 25 VIN = 12V DRIVE = 6V 1.2 5.0 0 20 40 60 80 100 DUTY CYCLE (%) 3959 G08 3959 G09 3959f 5 LT3959 TYPICAL PERFORMANCE CHARACTERISTICS EN/UVLO Threshold vs Temperature TA = 25°C, unless otherwise noted. SW Minimum On- and Off-Times vs Temperature 1.27 EN/UVLO Hysteresis Current vs Temperature 200 2.4 190 EN/UVLO RISING 1.23 1.21 EN/UVLO FALLING 1.19 2.2 180 MINIMUM OFF TIME 170 160 150 25 50 75 0 TEMPERATURE (°C) –25 100 130 –50 125 –25 25 50 75 0 TEMPERATURE (°C) 100 3959 G10 INTVCC vs Temperature INTVCC Load Regulation 100 125 INTVCC Line Regulation 5.0 DRIVE = 6V DRIVE LDO DRIVE LDO DRIVE LDO 4.4 4.2 4.0 4.5 INTVCC VOLTAGE (V) INTVCC VOLTAGE (V) INTVCC (V) 25 50 75 0 TEMPERATURE (°C) –25 3959 G12 5 4.6 4 VIN LDO (DRIVE = 0V) 3.5 4.5 4.0 DRIVE = 0V VIN LDO 3.5 VIN LDO 3.8 3.6 –50 3 –25 25 50 75 0 TEMPERATURE (°C) 100 5 0 125 10 15 0 25°C –40°C 100 5 10 15 20 25 3959 G16 25 30 35 40 60 50 50 45 40 30 20 –50 –25 0 25 50 75 45 Internal Switch On-Resistance vs INTVCC 100 125 TEMPERATURE (°C) INTVCC LOAD (mA) 20 3959 G15 ON-RESISTANCE (mΩ) ON-RESISTANCE (mΩ) 125°C 0 15 3959 G14 Internal Switch On-Resistance vs Temperature 300 0 10 VIN (V) VIN = 12V DRIVE = 4V 200 5 INTVCC LOAD (mA) INTVCC Dropout Voltage vs Current, Temperature 400 3.0 25 20 3959 G13 DROPOUT VOLTAGE (mV) 1.6 –50 125 3959 G11 5.0 4.8 2.0 1.8 MINIMUM ON TIME 140 1.17 –50 EN/UVLO (μA) MINIMUM ON/OFF TIME (ns) EN/UVLO VOLTAGE (V) 1.25 40 35 30 2 2.5 3 3.5 4 4.5 5 INTCCC (V) 3959 G17 3959 G18 3959f 6 LT3959 PIN FUNCTIONS DRIVE (Pin 28): DRIVE LDO Supply Pin. This pin can be connected to either VIN or a quasi-regulated voltage supply such as a DC converter output. This pin must be bypassed to GND with a minimum of 1μF capacitor placed close to the pin. Tie this pin to VIN if not used. PGOOD (Pin 35): Output Ready Status Pin. An opencollector pull down on PGOOD asserts when INTVCC is greater than 2.7V and the FBX voltage is within 5% (80mV if VFBX = 1.6V or 40mV if VFBX = –0.8V) of the regulation voltage. EN/UVLO (Pin 25): Shutdown and Undervoltage Detect Pin. An accurate 1.22V (nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. Rising hysteresis is generated by the external resistor divider and an accurate internal 2.2μA pull-down current. An undervoltage condition resets soft-start. Tie to 0.4V, or less, to disable the device and reduce VIN quiescent current below 1μA. RT (Pin 33): Switching Frequency Adjustment Pin. Set the frequency using a resistor to SGND. Do not leave the RT pin open. FBX (Pin 31): Voltage Regulation Feedback Pin for Positive or Negative Outputs. Connect this pin to a resistor divider between the output and SGND. FBX is the input of two error amplifiers—one configured to regulate a positive output; the other, a negative output. Depending upon topology selected, switching causes the output to ramp positive or negative. The appropriate amplifier takes control while the other becomes inactive. Additionally FBX is input for two window comparators that indicate through the PGOOD pin when the output is within 5% of the regulation voltages. FBX also modulates the switching frequency during start-up and fault conditions when FBX is close to SGND. SS (Pin 32): Soft-Start Pin. This pin modulates compensation pin voltage (VC) clamp. The soft-start interval is set with an external capacitor. The pin has a 10μA (typical) pull-up current source to an internal 2.5V rail. The softstart pin is reset to SGND by an EN/UVLO undervoltage condition, an INTVCC undervoltage condition or an internal thermal lockout. GND (Pins 13-17): Source Terminal of Switch and the GND Input to the Switch Current Comparator. GNDK (Pin 12): Kelvin Connection Pin between GND and SGND. Kelvin connect this pin to the SGND plane close to the IC. See the Board Layout section. INTVCC (Pin 36): Regulated Supply for Internal Loads and Gate Driver. Regulated to 4.75V if powered from DRIVE or regulated to 3.75V if powered from VIN. The INTVCC pin must be bypassed to SGND with a minimum of 4.7μF capacitor placed close to the pin. NC (Pins 1-3, 6, 10, 23): No Internal Connection. Leave these pins open or connect them to the adjacent pins. SGND (Exposed Pad Pin 37, Pins 4, 24): Signal Ground. Must be soldered directly to the signal ground plane. Connect to ground terminal of: external resistor dividers for FBX and EN/UVLO; capacitors for INTVCC, SS, and VC; and resistor RT. SW (Exposed Pad Pin 38, Pins 8, 9, 20, 21): Drain of Internal Power N-Channel MOSFET. SYNC (Pin 34): Frequency Synchronization Pin. Used to synchronize the internal oscillator to an outside clock. If this feature is used, an RT resistor should be chosen to program a switching frequency 20% slower than SYNC pulse frequency. Tie the SYNC pin to SGND if this feature is not used. This signal is ignored during FB frequency foldback or when INTVCC is less than 2.7V. VIN (Pin 27): Supply Pin for Internal Leads and the VIN LDO Regulator of INTVCC. Must be locally bypassed to GND with a minimum of 1μF capacitor placed close to this pin. VC (Pin 30): Error Amplifier Compensation Pin. Used to stabilize the voltage loop with an external RC network. Place compensation components between the VC pin and SGND. 3959f 7 LT3959 BLOCK DIAGRAM L1 CDC D1 VOUT t VIN R4 R3 CIN SGND R2 L2 t COUT FBX R1 SGND 25 27 EN/UVLO A10 IS1 2.2μA 2.5V 30 BG UVLO G4 RC 1.72V SGND – + A11 – + A12 –0.86V 1.6V FBX VIN –0.8V 35 A8 VC + A1 – Q2 CURRENT LIMIT CURRENT LIMIT VIN LDO DRIVE LDO INTVCC + 8, 9, 20, 21 R G5 S PWM COMPARATOR SLOPE PGOOD VISENSE RAMP G8 A15 + – + A13 – + A14 G7 –0.76V 1.25V G1 1.25V + + – 32 SS CSS 34 – + A5 + – 45mV RSENSE SYNC GND 13, 14 15, 16 17 RAMP GENERATOR – +A3 FREQ FOLDBACK FREQUENCY FOLDBACK A6 2.7V – 1.52V M1 G2 Q SGND SW DRIVER + A2 – Q4 CVCC 1.2V SR1 – +A7 36 – TSD ~165˚C G6 RPG INTERNAL BIAS OTP CC1 31 INTERNAL BIAS GENERATOR BG_LOW Q3 CC2 FBX 1.22V BANDGAP REFERENCE IS2 10μA VC + – 2.5V IS3 28 DRIVE VIN 100kHz ~ 1MHz OSCILLATOR A4 Q1 FREQ PROG 33 RT SGND 4, 24 12 GNDK 3759 F01 RT Figure 1. LT3959 Block Diagram Working as a SEPIC Converter 3959f 8 LT3959 APPLICATIONS INFORMATION Main Control Loop The LT3959 uses a fixed frequency, current mode control scheme to provide excellent line and load regulation. Operation can be best understood by referring to the Block Diagram in Figure 1. The start of each oscillator cycle sets the SR latch (SR1) and turns on the internal power MOSFET switch M1 through driver G2. The switch current flows through the internal current sensing resistor RSENSE and generates a voltage proportional to the switch current. This current sense voltage VISENSE (amplified by A5) is added to a stabilizing slope compensation ramp and the resulting sum (SLOPE) is fed into the positive terminal of the PWM comparator A7. When SLOPE exceeds the level at the negative input of A7 (VC pin), SR1 is reset, turning off the power switch. The level at the negative input of A7 is set by the error amplifier A1 (or A2) and is an amplified version of the difference between the feedback voltage (FBX pin) and the reference voltage (1.6V or –0.8V, depending on the configuration). In this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. The LT3959 has a switch current limit function. The current sense voltage is input to the current limit comparator A6. If the SENSE voltage is higher than the sense current limit threshold VSENSE(MAX) (45mV, typical), A6 will reset SR1 and turn off M1 immediately. The LT3959 is capable of generating either positive or negative output voltage with a single FBX pin. It can be configured as a boost or SEPIC converter to generate positive output voltage, or as an inverting converter to generate negative output voltage. When configured as a SEPIC converter, as shown in Figure 1, the FBX pin is pulled up to the internal bias voltage of 1.6V by a voltage divider (R1 and R2) connected from VOUT to SGND. Comparator A2 becomes inactive and comparator A1 performs the inverting amplification from FBX to VC. When the LT3959 is in an inverting configuration, the FBX pin is pulled down to –0.8V by a voltage divider connected from VOUT to SGND. Comparator A1 becomes inactive and comparator A2 performs the noninverting amplification from FBX to VC. The LT3959 has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. An overvoltage comparator A11 (with 40mV hysteresis) senses when the FBX pin voltage exceeds the positive regulated voltage (1.6V) by 7.5% and turns off M1. Similarly, an overvoltage comparator A12 (with 20mV hysteresis) senses when the FBX pin voltage exceeds the negative regulated voltage (–0.8V) by 7.5% and turns off M1. Both reset pulses are sent to the main RS latch (SR1) through G6 and G5. The internal power MOSFET switch M1 is actively held off for the duration of an output overvoltage condition. Programming Turn-On and Turn-Off Thresholds with EN/UVLO Pin The EN/UVLO pin controls whether the LT3959 is enabled or is in shutdown state. A micropower 1.22V reference, a comparator A10 and controllable current source IS1 allow the user to accurately program the supply voltage at which the IC turns on and off. The falling value can be accurately set by the resistor dividers R3 and R4. When EN/UVLO is above 0.7V, and below the 1.22V threshold, the small pull-down current source IS1 (typical 2.2μA) is active. The purpose of this current is to allow the user to program the rising hysteresis. The Block Diagram of the comparator and the external resistors is shown in Figure 1. The typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: VVIN(FALLING) = 1.22 • (R3+R4) R4 VVIN(RISING) =2.2μA • R3+ VIN(FALLING) For applications where the EN/UVLO pin is only used as a logic input, the EN/UVLO pin can be connected directly to the input voltage VIN for always-on operation. 3959f 9 LT3959 APPLICATIONS INFORMATION INTVCC Low Dropout Voltage Regulators Operating Frequency and Synchronization The LT3959 features two internal low dropout (LDO) voltage regulators (VIN LDO and DRIVE LDO) powered from different supplies (VIN and DRIVE respectively). Both LDO’s regulate the internal INTVCC supply which powers the gate driver and the internal loads, as shown in Figure 1. Both regulators are designed so that current does not flow from INTVCC to the LDO input under a reverse bias condition. DRIVE LDO regulates the INTVCC to 4.75V, while VIN LDO regulates the INTVCC to 3.75V. VIN LDO is turned off when the INTVCC voltage is greater than 3.75V (typical). Both LDO’s can be turned off if the INTVCC pin is driven by a supply of 4.75V or higher but less than 8V (the INTVCC maximum voltage rating is 8V). A table of the LDO supply and output voltage combination is shown in Table 1. The choice of operating frequency may be determined by on-chip power dissipation, otherwise it is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing gate drive current and internal MOSFET and diode switching losses. However, lower frequency operation requires a physically larger inductor. Switching frequency also has implications for loop compensation. The LT3959 uses a constant-frequency architecture that can be programmed over a 100kHz to 1MHz range with a single external resistor from the RT pin to SGND, as shown in Figure 1. The RT pin must have an external resistor to SGND for proper operation of the LT3959. A table for selecting the value of RT for a given operating frequency is shown in Table 2. Table 1. LDO’s Supply and Output Voltage Combination (Assuming That the LDO Dropout Voltage is 0.15V) SUPPLY VOLTAGES LDO OUTPUT Table 2. Timing Resistor (RT) Value OSCILLATOR FREQUENCY (kHz) RT (kΩ) 86.6 DRIVE INTVCC LDO STATUS (Note 7) 100 VIN 200 41.2 VIN ≤ 3.9V VDRIVE < VIN VIN – 0.15V #1 Is ON 300 27.4 VDRIVE = VIN VIN – 0.15V #1 #2 are ON 400 21.0 VIN < VDRIVE < 4.9V VDRIVE – 0.15V #2 Is ON 500 16.5 4.9V ≤ VDRIVE ≤ 40V 4.75V #2 Is ON 600 13.7 VDRIVE < 3.9V 3.75V #1 Is ON 700 11.5 VDRIVE = 3.9V 3.75V #1 #2 are ON 800 9.76 #2 Is ON 900 8.45 #2 Is ON 1000 6.81 3.9V < VIN ≤ 40V 3.9V < VDRIVE < 4.9V VDRIVE – 0.15V 4.75V 4.9V ≤ VDRIVE ≤ 40V Note 7: #1 is VIN LDO and #2 is DRIVE LDO The DRIVE pin provides flexibility to power the gate driver and the internal loads from a supply that is available only when the switcher is enabled and running. If not used, the DRIVE pin should be tied to VIN. The INTVCC pin must be bypassed to SGND immediately adjacent to the INTVCC pin with a minimum of 4.7μF ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate driver. The switching frequency of the LT3959 can be synchronized to the positive edge of an external clock source. By providing a digital clock signal into the SYNC pin, the LT3959 will operate at the SYNC clock frequency. If this feature is used, an RT resistor should be chosen to program a switching frequency 20% slower than SYNC pulse frequency. The SYNC pulse should have a minimum pulse width of 200ns. Tie the SYNC pin to SGND if this feature is not used. 3959f 10 LT3959 APPLICATIONS INFORMATION Duty Cycle Consideration Switching duty cycle is a key variable defining converter operation. As such, its limits must be considered. Minimum on-time is the smallest time duration that the LT3959 is capable of turning on the internal power MOSFET. This time is generally about 150ns (typical) (see Minimum On-Time in the Electrical Characteristics table). In each switching cycle, the LT3959 keeps the power switch off for at least 150ns (typical) (see Minimum Off-Time in the Electrical Characteristics table). The minimum on-time and minimum off-time and the switching frequency define the minimum and maximum switching duty cycles a converter is able to generate: Minimum duty cycle = minimum on-time • frequency Maximum duty cycle = 1 – (minimum off-time • frequency) Programming the Output Voltage The output voltage (VOUT) is set by a resistor divider, as shown in Figure 1. The positive VOUT and negative VOUT are set by the following equations: ⎛ R2 ⎞ VOUT(POSITIVE) = 1.6V • ⎜1+ ⎟ ⎝ R1 ⎠ ⎛ R2 ⎞ VOUT(NEGATIVE) = –0.8V • ⎜1+ ⎟ ⎝ R1 ⎠ The resistors R1 and R2 are typically chosen so that the error caused by the current flowing into the FBX pin during normal operation is less than 1% (this translates to a maximum value of R1 at about 121k). Soft-Start The LT3959 contains several features to limit peak switch currents and output voltage (VOUT) overshoot during start-up or recovery from a fault condition. The primary purpose of these features is to prevent damage to external components or the load. High peak switch currents during start-up may occur in switching regulators. Since VOUT is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. A large surge current may cause inductor saturation or power switch failure. LT3959 addresses this mechanism with the SS pin. As shown in Figure 1, the SS pin reduces the internal power MOSFET current by pulling down the VC pin through Q2. In this way the SS allows the output capacitor to charge gradually toward its final value while limiting the start-up peak currents. Besides start-up, soft-start can also be triggered by INTVCC undervoltage lockout and/or thermal lockout, which causes the LT3959 to stop switching immediately. The SS pin will be discharged by Q3. When all faults are cleared and the SS pin has been discharged below 0.2V, a 10μA current source IS2 starts charging the SS pin, initiating a soft-start operation. The soft-start interval is set by the soft-start capacitor selection according to the equation: TSS = CSS • 1.25V 10μA FBX Frequency Foldback When VOUT is very low during start-up or a short-circuit fault on the output, the switching regulator must operate at low duty cycles to maintain the power switch current within the current limit range, since the inductor current decay rate is very low during switch off time. The minimum on-time limitation may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switching frequency. So, the switch current will keep increasing through each switch cycle, exceeding the programmed current limit. To prevent the switch peak currents from exceeding the programmed value, the LT3959 contains a frequency foldback function to reduce the switching frequency when the FBX voltage is low (see the Normalized Switching Frequency vs FBX graph in the Typical Performance Characteristics section). 3959f 11 LT3959 APPLICATIONS INFORMATION Some frequency foldback waveforms are shown in the Typical Applications section. The frequency foldback function prevents IL from exceeding the programmed limits because of the minimum on-time. During frequency foldback, external clock synchronization is disabled to allow the frequency reducing operation to function properly. Loop Compensation Loop compensation determines the stability and transient performance. The LT3959 uses current mode control to regulate the output which simplifies loop compensation. The optimum values depend on the converter topology, the component values and the operating conditions (including the input voltage, load current, etc.). To compensate the feedback loop of the LT3959, a series resistor-capacitor network is usually connected from the VC pin to SGND. Figure 1 shows the typical VC compensation network. For most applications, the capacitor should be in the range of 470pF to 22nF, and the resistor should be in the range of 5k to 50k. A small capacitor is often connected in parallel with the RC compensation network to attenuate the VC voltage ripple induced from the output voltage ripple through the internal error amplifier. The parallel capacitor usually ranges in value from 10pF to 100pF. A practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance. Stability should then be checked across all operating conditions, including load current, input voltage and temperature. The Internal Power Switch Current For control and protection, the LT3959 measures the internal power MOSFET current by using a sense resistor (RSENSE) between GND and the MOSFET source. Figure 2 shows a typical wave-form of the internal switch current (ISW). ISW )ISW ISW(PEAK) t DTS TS 3959 F02 Figure 2. The SW Current During a Switching Cycle Due to the current limit (minimum 6A) of the internal power switch, the LT3959 should be used in the applications that the switch peak current ISW(PEAK) during steady state normal operation is lower than 6A by a sufficient margin (10% or higher is recommended). It is recommended to measure the IC temperature in steady state to verify that the junction temperature limit (125°C) is not exceeded. A low switching frequency may be required to ensure TJ(MAX) does not exceed 125°C. If LT3959 die temperature reaches thermal lockout threshold at 165°C (typical), the IC will initiate several protective actions. The power switch will be turned off. A soft-start operation will be triggered. The IC will be enabled again when the junction temperature has dropped by 5°C (nominal). APPLICATION CIRCUITS The LT3959 can be configured as different topologies. The design procedure for component selection differs somewhat between these topologies. The first topology to be analyzed will be the boost converter, followed by SEPIC and inverting converters. 3959f 12 LT3959 APPLICATIONS INFORMATION Boost Converter: Switch Duty Cycle and Frequency The LT3959 can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. Remember that boost converters are not short-circuit protected. Under a shorted output condition, the inductor current is limited only by the input supply capability. For applications requiring a step-up converter that is short-circuit protected, please refer to the Applications Information section covering SEPIC converters. The conversion ratio as a function of duty cycle is: VOUT 1 = VIN 1−D in continuous conduction mode (CCM). For a boost converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (VOUT) and the input voltage (VIN). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT − VIN(MIN) VOUT The alternative to CCM, discontinuous conduction mode (DCM) is not limited by duty cycle to provide high conversion ratios at a given frequency. The price one pays is reduced efficiency and substantially higher switching current. Boost Converter: Maximum Output Current Capability and Inductor Selection For the boost topology, the maximum average inductor current is: IL(MAX) = IO(MAX) • 1 1−DMAX Due to the current limit of its internal power switch, the LT3959 should be used in a boost converter whose maximum output current (IO(MAX)) is less than the maximum output current capability by a sufficient margin (10% or higher is recommended): IO(MAX) < VIN(MIN) • (6A – 0.5 • ΔISW ) VOUT The inductor ripple current ΔISW has a direct effect on the choice of the inductor value and the converter’s maximum output current capability. Choosing smaller values of ΔISW increases output current capability, but requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ΔISW provides fast transient response and allows the use of low inductances, but results in higher input current ripple and greater core losses, and reduces output current capability. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value of the boost converter can be determined using the following equation: L= VIN(MIN) • DMAX ΔISW • fOSC The peak inductor current is the switch current limit (7A typical), and the RMS inductor current is approximately equal to IL(MAX). The user should choose the inductors having sufficient saturation and RMS current ratings. Boost Converter: Output Diode Selection To maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desirable. The peak reverse voltage that the diode must withstand is equal to the regulator output voltage plus any additional ringing across its anode-to-cathode during the on-time. The average forward current in normal operation is equal to the output current. 3959f 13 LT3959 APPLICATIONS INFORMATION It is recommended that the peak repetitive reverse voltage rating VRRM is higher than VOUT by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the diode is: ESRCOUT ≤ PD = IO(MAX) • VD Where VD is diode’s forward voltage drop, and the diode junction temperature is: TJ = TA +PD • R θ J A The RθJA to be used in this equation normally includes the RθJC for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. Boost Converter: Output Capacitor Selection Contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. The effect of these three parameters (ESR, ESL and bulk C) on the output voltage ripple waveform for a typical boost converter is illustrated in Figure 3. tON and the following equations can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: tOFF )VCOUT VOUT (AC) )VESR RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 3959 F03 Figure 3. The Output Ripple Waveform of a Boost Converter The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step ΔVESR and charging/discharging ΔVCOUT. For the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between ΔVESR and ΔVCOUT. This percentage ripple will change, depending on the requirements of the application, 0.01• VOUT ID(PEAK) For the bulk C component, which also contributes 1% to the total ripple: COUT ≥ IO(MAX) 0.01• VOUT • ƒOSC The output capacitor in a boost regulator experiences high RMS ripple currents, as shown in Figure 3. The RMS ripple current rating of the output capacitor can be determined using the following equation: IRMS(COUT) ≥ IO(MAX) • DMAX 1−DMAX Multiple capacitors are often paralleled to meet ESR requirements. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the required RMS current rating. Additional ceramic capacitors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output. Boost Converter: Input Capacitor Selection The input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and the input current waveform is continuous. The input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10μF to 100μF. A low ESR capacitor is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a boost converter is: IRMS(CIN) = 0.3 • ΔIL 3959f 14 LT3959 APPLICATIONS INFORMATION SEPIC CONVERTER APPLICATIONS The LT3959 can be configured as a SEPIC (single-ended primary inductance converter), as shown in Figure 1. This topology allows for the input to be higher, equal, or lower than the desired output voltage. The conversion ratio as a function of duty cycle is: Due to the current limit of it’s internal power switch, the LT3959 should be used in a SEPIC converter whose maximum output current (IO(MAX)) is less than the output current capability by a sufficient margin (10% or higher is recommended): IO(MAX) < (1–DMAX) • (6A – 0.5 • ΔISW) The inductor ripple currents ΔIL1 and ΔIL2 are identical: VOUT + VD D = VIN 1−D ΔIL1 = ΔIL2 = 0.5 • ΔISW SEPIC Converter: Switch Duty Cycle and Frequency The inductor ripple current ΔISW has a direct effect on the choice of the inductor value and the converter’s maximum output current capability. Choosing smaller values of ΔISW requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ΔISW allows the use of low inductances, but results in higher input current ripple and greater core losses and reduces output current capability. For a SEPIC converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (VOUT), the input voltage (VIN) and diode forward voltage (VD). Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value (L1 and L2 are independent) of the SEPIC converter can be determined using the following equation: In continuous conduction mode (CCM). In a SEPIC converter, no DC path exists between the input and output. This is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT + VD VIN(MIN) + VOUT + VD VIN(MIN) • DMAX 0.5 • ΔISW • ƒOSC For most SEPIC applications, the equal inductor values will fall in the range of 1μH to 100μH. SEPIC Converter: The Maximum Output Current Capability and Inductor Selection As shown in Figure 1, the SEPIC converter contains two inductors: L1 and L2. L1 and L2 can be independent, but can also be wound on the same core, since identical voltages are applied to L1 and L2 throughout the switching cycle. For the SEPIC topology, the current through L1 is the converter input current. Based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of L1 and L2 are: IL1(MAX) = IIN(MAX) = IO(MAX) • L1 = L2 = DMAX 1– DMAX By making L1 = L2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2L, due to mutual inductance: VIN(MIN) L= • DMAX ΔISW • ƒOSC This maintains the same ripple current and energy storage in the inductors. The peak inductor currents are: IL1(PEAK) = IL1(MAX) + 0.5 • ΔIL1 IL2(PEAK) = IL2(MAX) + 0.5 • ΔIL2 The maximum RMS inductor currents are approximately equal to the maximum average inductor currents. IL2(MAX) = IO(MAX) 3959f 15 LT3959 APPLICATIONS INFORMATION Based on the preceding equations, the user should choose the inductors having sufficient saturation and RMS current ratings. SEPIC Converter: Output Diode Selection To maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. The average forward current in normal operation is equal to the output current. It is recommended that the peak repetitive reverse voltage rating VRRM is higher than VOUT + VIN(MAX) by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the diode is: PD = IO(MAX) • VD where VD is diode’s forward voltage drop, and the diode junction temperature is: TJ = TA + PD • RθJA The RθJA used in this equation normally includes the RθJC for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IIN, while approximately –IO flows during the on-time. The RMS rating of the coupling capacitor is determined by the following equation: A low ESR and ESL, X5R or X7R ceramic capacitor works well for CDC. INVERTING CONVERTER APPLICATIONS The LT3959 can be configured as a dual-inductor inverting topology, as shown in Figure 4. The VOUT to VIN ratio is: VOUT – VD D =– VIN 1−D In continuous conduction mode (CCM). SEPIC Converter: Selecting the DC Coupling Capacitor The DC voltage rating of the DC coupling capacitor (CDC, as shown in Figure 1) should be larger than the maximum input voltage: VCDC > VIN(MAX) CDC L1 VIN + L2 – + – CIN SW D1 LT3959 SEPIC Converter: Output and Input Capacitor Selection The selections of the output and input capacitors of the SEPIC converter are similar to those of the boost converter. Please refer to the Boost Converter, Output Capacitor Selection and Boost Converter, Input Capacitor Selection sections. VOUT + VD VIN(MIN) IRMS(CDC) > IO(MAX) • GND COUT VOUT + + 3959 F04 Figure 4. A Simplified Inverting Converter Inverting Converter: Switch Duty Cycle and Frequency For an inverting converter operating in CCM, the duty cycle of the main switch can be calculated based on the negative output voltage (VOUT) and the input voltage (VIN). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT – VD VOUT – VD – VIN(MIN) 3959f 16 LT3959 APPLICATIONS INFORMATION Inverting Converter: Output Diode and Input Capacitor Selections The selections of the inductor, output diode and input capacitor of an inverting converter are similar to those of the SEPIC converter. Please refer to the corresponding SEPIC converter sections. Inverting Converter: Output Capacitor Selection The inverting converter requires much smaller output capacitors than those of the boost and SEPIC converters for similar output ripple. This is due to the fact that, in the inverting converter, the inductor L2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. The output ripple voltage is produced by the ripple current of L2 flowing through the ESR and bulk capacitance of the output capacitor: ⎛ ⎞ 1 ΔVOUT(P−P) = ΔIL2 • ⎜ESRCOUT + ⎟ 8 • fOSC • COUT ⎠ ⎝ After specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. The ESR can be minimized by using high quality X5R or X7R dielectric ceramic capacitors. In many applications, ceramic capacitors are sufficient to limit the output voltage ripple. The RMS ripple current rating of the output capacitor needs to be greater than: IRMS(COUT) > 0.3 • ΔIL2 Inverting Converter: Selecting the DC Coupling Capacitor The DC voltage rating of the DC coupling capacitor (CDC, as shown in Figure 4) should be larger than the maximum input voltage minus the output voltage (negative voltage): VCDC > VIN(MAX) – VOUT CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IIN, while approximately –IO flows during the on-time. The RMS rating of the coupling capacitor is determined by the following equation: IRMS(CDC) > IO(MAX) • DMAX 1– DMAX A low ESR and ESL, X5R or X7R ceramic capacitor works well for CDC. Board Layout The high power and high speed operation of the LT3959 demands careful attention to board layout and component placement. Careful attention must be paid to the internal power dissipation of the LT3959 at high input voltages, high switching frequencies, and high internal power switch currents to ensure that a junction temperature of 125°C is not exceeded. This is especially important when operating at high ambient temperatures. Exposed pads on the bottom of the package are SGND and SW terminals of the IC, and must be soldered to a SGND ground plane and a SW plane respectively. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into the copper planes with as much as area as possible. To prevent radiation and high frequency resonance problems, proper layout of the components connected to the IC is essential, especially the power paths with higher di/dt. The following high di/dt loops of different topologies should be kept as tight as possible to reduce inductive ringing: • In boost configuration, the high di/dt loop contains the output capacitor, the internal power MOSFET and the Schottky diode. • In SEPIC configuration, the high di/dt loop contains the internal power MOSFET, output capacitor, Schottky diode and the coupling capacitor. • In inverting configuration, the high di/dt loop contains internal power MOSFET, Schottky diode and the coupling capacitor. 3959f 17 LT3959 APPLICATIONS INFORMATION Check the stress on the internal power MOSFET by measuring the SW-to-GND voltage directly across the IC terminals. Make sure the inductive ringing does not exceed the maximum rating of the internal power MOSFET (40V). the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LT3959 in order to keep the high impedance FBX node short. The small-signal components should be placed away from high frequency switching nodes. For optimum load regulation and true remote sensing, the top of the output voltage sensing resistor divider should connect independently to Figure 5 shows the suggested layout of the 2.5V to 8V input, 12V output boost converter in the Typical Application section. 3959f 18 LT3959 APPLICATIONS INFORMATION R1 CSS VIA TO VOUT RT VIA TO VIN CVCC R2 R5 RC CC 36 35 34 33 32 31 30 1 28 2 27 3 SGND R3 37 4 25 24 6 VIA TO VOUT LT3959 R4 23 38 SW 8 21 9 20 10 12 13 14 15 16 17 L1 COUT COUT D1 CIN GND VOUT VIA TO VOUT VIN 3959 F05 VIAS TO SGND GROUND PLANE VIAS TO SW PLANE Figure 5. Suggested Layout of the 2.5V to 8V Input. 12V Output Boost Converter in the Typical Application Section 3959f 19 LT3959 TYPICAL APPLICATIONS 2.5V to 5V Input, –5V Output Inverting Converter CDC 4.7μF, 25V X7R L1A L1B VIN 2.5V TO 5V CIN 47μF 10V X5R 124k 22k VIN SW PGOOD D2 D1 DRIVE 1μF 16V X5R EN/UVLO 121k LT3959 SYNC SGND GNDK COUT 47μF 10V X5R ×2 GND VOUT –5V 1A 84.5k FBX RT SS 27.4k 300kHz VC INTVCC 9.09k 0.1μF 10nF 15.8k CVCC 4.7μF 10V X5R 3959 TA02 L1A, L1B: COILTRONICS DRQ127-3R3 D1: VISHAY 6CWQ03FN D2: PHILIPS PMEG2005EJ Efficiency vs Output Current 100 VIN = 5V EFFICIENCY (%) 90 80 70 60 50 0 200 400 600 800 1000 OUTPUT CURRENT (mA) 3759 TA02a 3959f 20 LT3959 TYPICAL APPLICATIONS 2.5V to 24V Input, 12V Output SEPIC Converter 4.7μF 50V L1A D1 t t VIN 2.5V TO 24V CIN 22μF 50V ×2 VIN 124k L1B SW GND EN/UVLO 150k COUT1 47μF 16V X5R ×2 VOUT 12V 500mA AT VIN = 2.5V 1.5A AT VIN > 8v 121k LT3959 PGOOD SYNC TIE TO SGND IF NOT USED DRIVE 105k RT FBX SS VC 27.4k 300kHz SGND GNDK INTVCC 7.5k 0.1μF 4.7μF 15.8k 22nF 3959 TA03 L1A, L1B: COILTRONICS DRQ127-150 D1: VISHAY 6CWQ06FN Efficiency vs Output Current 100 VIN = 12V 95 EFFICIENCY (%) 90 85 80 75 70 65 60 200 0 400 600 800 1000 OUTPUT CURRENT (mA) 3759 TA03b Frequency Foldback Waveforms When Output Short-Circuits Load Step Response at VIN = 12V VOUT 10V/DIV VOUT 500mV/DIV (AC) VSW 20V/DIV 0.8A IOUT 500mA/DIV 0.2A 500μs/DIV IL1A+L1B 2.5A/DIV 3959 TA03c 500μs/DIV 3959 TA03d 3959f 21 LT3959 TYPICAL APPLICATIONS 2.5V to 8V Input, 12V LED Driver VIN 2.5V TO 8V L1 8.2μH CIN 22μF 16V X5R R1 124k D1 VIN PGOOD EN/UVLO R2 121k COUT 22μF 16V X5R ×2 SW GND 12V LEDs 500mA LT3959 SYNC DRIVE DZ1 24V SGND GNDK RT VOUT FBX SS RT 27.4k 300kHz CSS 0.1μF R3 7.68k INTVCC VC RC 4.99k CVCC 4.7μF 10V X5R CC 22nF R4 3.48k R5 0.5Ω 3959 TA04 L1: TOKO 962BS-BR2M D1: VISHAY SILICONIX 20BQ030 DZ1: CENTRAL SEMICONDUCTOR CMHZ5252B Efficiency vs VIN 94 EFFICIENCY (%) 92 90 88 86 84 82 2 3 4 5 6 7 8 VIN (V) 3959 TA04b 3959f 22 LT3959 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHE Package Variation: UHE36(28)MA 36(28)-Lead Plastic QFN (5mm × 6mm) (Reference LTC DWG # 05-08-1836 Rev D) 28 27 25 24 23 21 20 0.70 ±0.05 17 30 1.88 ± 0.05 31 5.50 ± 0.05 4.10 ± 0.05 1.50 REF 1.53 ± 0.05 3.00 ± 0.05 32 33 16 3.00 ± 0.05 0.12 ± 0.05 15 14 PACKAGE OUTLINE 13 0.48 ± 0.05 34 12 35 36 1 2 3 4 6 0.50 BSC 8 9 0.25 ±0.05 10 2.00 REF 5.10 ± 0.05 6.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ± 0.10 0.75 ± 0.05 R = 0.10 TYP PIN 1 TOP MARK (NOTE 6) 30 31 32 1.50 REF 33 34 35 28 27 2.00 REF 25 24 1 1.88 ± 0.10 3.00 ± 0.10 0.12 ± 0.10 6.00 ± 0.10 2 3 4 6 23 21 36 PIN 1 NOTCH R = 0.30 OR 0.35 × 45° CHAMFER 1.53 ± 0.10 0.48 ± 0.10 3.00 ± 0.10 20 8 R = 0.125 TYP 9 10 0.40 ± 0.10 0.200 REF 0.00 – 0.05 17 16 15 0.25 ± 0.05 0.50 BSC 14 13 12 (UHE36(28)MA) QFN 0112 REV D BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3959f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LT3959 TYPICAL APPLICATION 2.5V to 8V Input, 12V Output Boost Converter VIN 2.5V TO 8V L1 10μH CIN 22μF 16V X5R R3 124k R5 47k VIN PGOOD EN/UVLO R4 121k D1 COUT 47μF 16V X5R ×2 SW GND LT3959 SYNC DRIVE R2 105k SGND GNDK RT VOUT 12V 500mA, 2.5V ≤ VIN < 5V 1A, 5V ≤ VIN ≤ 8V FBX VC SS RT 27.4k 300kHz CSS 0.22μF R1 15.8k INTVCC RC 3.4k CC 22nF CVCC 4.7μF 10V X5R 3959 TA05 L1: COILTRONICS DR125-100 D1: VISHAY SILICONIX 20BQ030 Efficiency vs Output Current 100 Load Step Response at VIN = 8V VIN = 5V EFFICIENCY (%) 95 VOUT 500mV/DIV (AC) 90 85 0.8A IOUT 500mA/DIV 80 75 0.2A 500μs/DIV 3959 TA05c 70 0 1000 600 800 200 400 OUTPUT CURRENT (mA) 3759 TA05b RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT3957 Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch 3V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operation Frequency, 5mm × 6mm QFN Package LT3958 Boost, Flyback, SEPIC and Inverting Converter with 3.3A, 84V Switch 5V ≤ VIN ≤ 80V, 100kHz to 1MHz Programmable Operation Frequency, 5mm × 6mm QFN Package LT3759 Boost, Flyback, SEPIC and Inverting Controller 1.6V ≤ VIN ≤ 42V, 100kHz to 1MHz Programmable Operation Frequency, MSOP-12E Package LT3758 Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ VIN ≤ 100V, 100kHz to 1MHz Programmable Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages LT3757 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages LT3748 100V Isolated Flyback Controller 5V ≤ VIN ≤ 100V, No Opto Flyback , MSOP-16 with High Voltage Spacing LT3798 Off-Line Isolated No Opto-Coupler Flyback Controller with Active PFC VIN and VOUT Limited Only by External Components 3959f 24 Linear Technology Corporation LT 0712 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2012