LT3580 Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization FEATURES DESCRIPTION n The LT®3580 is a PWM DC/DC converter containing an internal 2A, 42V switch. The LT3580 can be configured as either a boost, SEPIC or inverting converter. Capable of generating 12V at 550mA or –12V at 350mA from a 5V input, the LT3580 is ideal for many local power supply designs. n n n n n n n n n n 2A Internal Power Switch Adjustable Switching Frequency Single Feedback Resistor Sets VOUT Synchronizable to External Clock High Gain SHDN Pin Accepts Slowly Varying Input Signals Wide Input Voltage Range: 2.5V to 32V Low VCESAT Switch: 300mV at 1.5A (Typical) Integrated Soft-Start Function Easily Configurable as a Boost or Inverting Converter User Configurable Undervoltage Lockout (UVLO) Tiny 8-Lead 3mm × 3mm DFN and 8-Lead MSOP Packages APPLICATIONS n n n n n The LT3580 has an adjustable oscillator, set by a resistor from the RT pin to ground. Additionally, the LT3580 can be synchronized to an external clock. The free running or synchronized switching frequency range of the part can be set between 200kHz and 2.5MHz. The LT3580 also features innovative SHDN pin circuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. Additional features such as frequency foldback and soft-start are integrated. The LT3580 is available in tiny 3mm × 3mm 8-lead DFN and 8-lead MSOP packages. VFD Bias Supplies TFT-LCD Bias Supplies GPS Receivers DSL Modems Local Power Supply L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 1.2MHz, 5V to 12V Boost Converter Achieves Over 88% Efficiency Efficiency and Power Loss 95 4.2μH SHDN GND 130k LT3580 RT FB VC SYNC 2.2μF 75k 1000 85 10μF SW SS 10k 0.1μF 1nF 80 800 75 600 70 65 400 POWER LOSS (mW) VIN 1200 90 EFFICIENCY (%) VIN 5V VOUT 12V 550mA 60 200 3580 TA01 55 50 0 0 100 200 300 400 LOAD CURRENT (mA) 500 600 3580 TA01b 3580fg 1 LT3580 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN Voltage ................................................. –0.3V to 32V SW Voltage ................................................ –0.4V to 42V RT Voltage ................................................... –0.3V to 5V SS and FB Voltage .................................... –0.3V to 2.5V VC Voltage ................................................... –0.3V to 2V SHDN Voltage ............................................ –0.3V to 32V SYNC Voltage............................................ –0.3V to 5.5V Operating Junction Temperature Range LT3580E (Notes 2, 5)......................... –40°C to 125°C LT3580I (Notes 2, 5).......................... –40°C to 125°C LT3580H (Notes 2, 5) ........................–40°C to 150°C LT3580MP (Notes 2, 5) ..................... –55°C to 125°C Storage Temperature Range ..................–65°C to 150°C PIN CONFIGURATION TOP VIEW TOP VIEW FB 1 VC 2 VIN 3 9 GND SW 4 8 SYNC 7 SS 6 RT 5 SHDN FB VC VIN SW 1 2 3 4 9 GND 8 7 6 5 SYNC SS RT SHDN MS8E PACKAGE 8-LEAD PLASTIC MSOP DD PACKAGE 8-LEAD (3mm s 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB θJA = 35°C/W TO 40°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3580EDD#PBF LT3580EDD#TRPBF LCXY 8-Lead (3mm × 3mm) Plastic DFN – 40°C to 125°C LT3580IDD#PBF LT3580IDD#TRPBF LCXY 8-Lead (3mm × 3mm) Plastic DFN – 40°C to 125°C LT3580EMS8E#PBF LT3580EMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP – 40°C to 125°C LT3580IMS8E#PBF LT3580IMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP – 40°C to 125°C LT3580HMS8E#PBF LT3580HMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP – 40°C to 150°C LT3580MPMS8E#PBF LT3580MPMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP – 55°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3580fg 2 LT3580 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN unless otherwise noted. (Note 2) PARAMETER Operating Voltage Range Positive Feedback Voltage Negative Feedback Voltage Positive FB Pin Bias Current Negative FB Pin Bias Current CONDITIONS MIN TYP MAX UNITS l 2.5 1.195 0 81 1.215 5 83.3 32 1.230 12 85 V V mV μA l l 81 81 85.5 86 μA μA μmhos l l l VFB = Positive Feedback Voltage, Current Into Pin VFB = Negative Feedback Voltage, Current Out of Pin (LT3580E, LT3580I, LT3580MP) (LT3580H) Error Amplifier Transconductance Error Amplifier Voltage Gain Quiescent Current Quiescent Current in Shutdown Reference Line Regulation Switching Frequency, fOSC Switching Frequency in Foldback Switching Frequency Set Range SYNC High Level for Synchronization SYNC Low Level for Synchronization SYNC Clock Pulse Duty Cycle Recommended Minimum SYNC Ratio fSYNC/fOSC Minimum Off-Time Minimum On-Time Switch Current Limit Switch VCESAT Switch Leakage Current Soft-Start Charging Current SHDN Minimum Input Voltage High SHDN Input Voltage Low SHDN Pin Bias Current VSHDN = 2.5V, Not Switching VSHDN = 0V 2.5V ≤ VIN ≤ 32V RT = 45.3k (LT3580E, LT3580I, LT3580H) RT = 45.3k (LT3580MP) RT = 464k (LT3580E, LT3580I, LT3580H) RT = 464k (LT3580MP) Compared to Normal fOSC SYNCing or Free Running l l l l 1.8 1.8 180 180 l 200 1.3 l 83.3 83.3 230 70 1 0 0.01 2 2 200 200 1/4 35 Minimum Duty Cycle (Note3) (LT3580E, LT3580I, LT3580H) Minimum Duty Cycle (Note3) (LT3580MP) Maximum Duty Cycle (Notes 3, 4) (LT3580E, LT3580I, LT3580MP) Maximum Duty Cycle (Notes 3, 4) (LT3580H) ISW = 1.5A VSW = 5V VSS = 0.5V Active Mode, SHDN Rising (LT3580E, LT3580I) Active Mode, SHDN Rising (LT3580H, LT3580MP) Active Mode, SHDN Falling (LT3580E, LT3580I) Active Mode, SHDN Falling (LT3580H, LT3580MP) Shutdown Mode VSHDN = 3V VSHDN = 1.3V VSHDN = 0V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3580E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3580I is guaranteed over the full –40°C to 125°C operating junction temperature range. The LT3580H is guaranteed over the full –40°C to l l l 2.2 2.15 1.6 l 1.55 l 4 1.27 1.25 1.24 1.22 l l l l 3/4 60 100 2.5 2.2 1.9 1.9 300 0.01 6 1.32 1.32 1.29 1.29 l 9.7 0.4 65 2.8 2.8 2.6 ns ns A A A 2500 l VSYNC = 0V to 2V V/V mA μA %/V MHz MHz kHz kHz Ratio kHz V V % 1.5 1 0.05 2.2 2.25 220 225 40 11.6 0 2.6 1 8 1.38 1.4 1.33 1.35 0.3 60 13.4 0.1 A mV μA μA V V V V V μA μA μA 150°C operating junction temperature range. The LT3580MP is guaranteed over the full –55°C to 125°C operating junction temperature range. Operating lifetime is derated at junction temperatures greater than 125°C. Note 3: Current limit guaranteed by design and/or correlation to static test. Note 4: Current limit measured at equivalent switching frequency of 2.5MHz. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 3580fg 3 LT3580 TYPICAL PERFORMANCE CHARACTERISTICS Switch Current Limit at 1MHz TA = 25°C unless otherwise specified Switch Current Limit at Minimum Duty Cycle Switch Saturation Voltage 400 2.5 350 SATURATION VOLTAGE (mV) 2.0 1.5 1.0 300 SWITCH CURRENT (A) SWITCH CURRENT LIMIT (A) 2.5 250 200 150 2.0 1.5 1.0 100 0.5 0.5 50 0 10 20 30 40 50 60 70 DUTY CYCLE (%) 80 0 90 0 1 0.5 1.5 SWITCH CURRENT (A) 0 2 3580 G01 400 600 800 SS VOLTAGE (mV) 1000 1200 3580 G03 Switching Waveforms for Figure 14 Circuit Positive Feedback Voltage 1.24 3.0 2.5 VOUT 50mV/DIV AC COUPLED 1.23 2.0 FB VOLTAGE (V) SWITCH CURRENT LIMIT (A) 200 3580 G02 Switch Current Limit at Minimum Duty Cycle 1.5 1.0 1.22 VSW 10V/DIV 1.21 1.20 0.5 IL 0.5A/DIV 0 –50 0 50 TEMPERATURE (°C) 100 1.19 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 3580 G04 1.9 1.7 1.5 1.1 –50 RT = 75k 50 0 TEMPERATURE (°C) 100 3580 G07 3580 G06 Internal UVLO 2.40 1 2.38 TA = –35°C 2.36 TA = 100°C 2.34 TA = 25°C VIN VOLTAGE (V) 2.1 NORMALIZED OSCILLATOR FREQUENCY (F/FNOM) RT = 35.7k 2.3 1.3 200ns/DIV Oscillator Frequency During Soft-Start 2.7 2.5 125 3580 G05 Oscillator Frequency FREQUENCY (MHz) 0 2.32 2.30 1/2 2.28 1/3 1/4 2.26 2.24 INVERTING CONFIGURATIONS BOOSTING CONFIGURATIONS 2.22 0 0 0.2 0.4 0.6 0.8 FB VOLTAGE (V) 1.0 1.2 3580 G08 2.20 –50 50 0 TEMPERATURE (°C) 100 3580 G09 3580fg 4 LT3580 TYPICAL PERFORMANCE CHARACTERISTICS SHDN Pin Current TA = 25°C unless otherwise specified SHDN Pin Current 30 300 25 250 Active/Lockout Threshold 1.40 20 15 10 –50°C 5 100°C 0.5 1.36 20°C 200 100°C 150 100 1.34 1.32 SHDN RISING 1.30 1.28 1.26 SHDN FALLING 1.24 50 1.22 20°C 0 0 1.38 SHDN VOLTAGE (V) SHDN PIN CURRENT (μA) SHDN PIN CURRENT (μA) –50°C 1 1.5 SHDN VOLTAGE (V) 2 0 0 5 20 15 25 10 SHDN VOLTAGE (V) 3580 G10 30 3580 G11 1.20 –50 50 0 TEMPERATURE (°C) 100 3580 G12 PIN FUNCTIONS FB (Pin 1): Positive and Negative Feedback Pin. For a boost or inverting converter, tie a resistor from the FB pin to VOUT according to the following equations: RFB = RFB = ( VOUT − 1.215) ; Boost or SEPIC Converter ( 83.3 • 10 −6 VOUT + 5mV 83.3 • 10 −6 ) ; Inverting Converter VC (Pin 2): Error Amplifier Output Pin. Tie external compensation network to this pin. VIN (Pin 3): Input Supply Pin. Must be locally bypassed. SW (Pin 4): Switch Pin. This is the collector of the internal NPN Power switch. Minimize the metal trace area connected to this pin to minimize EMI. RT (Pin 6): Timing Resistor Pin. Adjusts the switching frequency. Place a resistor from this pin to ground to set the frequency to a fixed free running level. Do not float this pin. SS (Pin 7): Soft-Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged by a (nominally) 275k resistor to about 2.2V. SYNC (Pin 8): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less 0.4V. Drive this pin to less than 0.4V to revert to the internal free running clock. See the Applications Information section for more information. GND (Exposed Pad Pin 9): Ground. Exposed pad must be soldered directly to local ground plane. SHDN (Pin 5): Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. Drive below 1.24V (LT3580E, LT3580I) or 1.22V (LT3580H, LT3580MP) to disable the chip. Drive above 1.38V (LT3580E, LT3580I) or 1.40V (LT3580H, LT3580MP) to activate chip and restart the soft-start sequence. Do not float this pin. 3580fg 5 LT3580 BLOCK DIAGRAM RC VIN CSS 7 SHDN 5 1.3V – + CC 2 SS CIN VC DISCHARGE DETECT L1 275k UVLO SR2 SOFTSTART R Q VIN 3 4 ILIMIT COMPARATOR – Q2 A3 1.215V REFERENCE + R S + ∑ A1 – A4 + A2 FREQUENCY FOLDBACK RFB 0.01Ω – RAMP GENERATOR GND FB 14.6k C1 Q1 Q + 1 VOUT SR1 DRIVER S 14.6k D1 SW VC 9 ÷N ADJUSTABLE OSCILLATOR – SYNC BLOCK SYNC 8 6 RT RT 3580 BD OPERATION The LT3580 uses a constant-frequency, current mode control scheme to provide excellent line and load regulation. Refer to the Block Diagram which shows the LT3580 in a boost configuration. At the start of each oscillator cycle, the SR latch (SR1) is set, which turns on the power switch, Q1. The switch current flows through the internal current sense resistor generating a voltage proportional to the switch current. This voltage (amplified by A4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator A3. When this voltage exceeds the level at the negative input of A3, the SR latch is reset, turning off the power switch. The level at the negative input of A3 (VC pin) is set by the error amplifier A1 (or A2) and is simply an amplified version of the difference between the feedback voltage (FB pin) and the reference voltage (1.215V or 5mV depending on the configuration). In this manner, the error amplifier sets the correct peak current level to keep the output in regulation. The LT3580 has a novel FB pin architecture that can be used for either boost or inverting configurations. When configured as a boost converter, the FB pin is pulled up to the internal bias voltage of 1.215V by the RFB resistor connected from VOUT to FB. Comparator A2 becomes inactive and comparator A1 performs the inverting amplification from FB to VC. When the LT3580 is in an inverting configuration, the FB pin is pulled down to 5mV by the RFB resistor connected from VOUT to FB. Comparator A1 becomes inactive and comparator A2 performs the noninverting amplification from FB to VC. 3580fg 6 LT3580 OPERATION SEPIC Topology The LT3580 can be configured as a SEPIC (single-ended primary inductance converter). This topology allows for the input to be higher, equal, or lower then the desired output voltage. Output disconnect is inherently built into the SEPIC topology, meaning no DC path exists between the input and output. This is useful for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. Inverting Topology The LT3580 can also work in a dual inductor inverting topology. The part’s unique feedback pin allows for the inverting topology to be built by simply changing the connection of external components. This solution results in very low output voltage ripple due to inductor L2 in series with the output. Abrupt changes in output capacitor current are eliminated because the output inductor delivers current to the output during both the off-time and the on-time of the LT3580 switch. Start-Up Operation Several functions are provided to enable a very clean start-up for the LT3580. • First, the SHDN pin voltage is monitored by an internal voltage reference to give a precise turn-on voltage level. An external resistor (or resistor divider) can be connected from the input power supply to the SHDN pin to provide a user-programmable undervoltage lockout function. VIN > VOUT OR VIN = VOUT OR VIN < VOUT L1 C2 • VIN SW RT L1 VOUT RT VIN R1 FB SS SW SHDN SHUTDOWN RT RT 3580 F01 Figure 1. SEPIC Topology Allows for the Input to Span the Output Voltage. Coupled or Uncoupled Inductors Can Be Used. Follow Noted Phasing if Coupled VOUT R1 GND VC SYNC CC L2 D1 FB C3 RC CSS • LT3580 + GND C2 • VIN + VC SYNC The LT3580 has a current limit circuit not shown in the Block Diagram. The switch current is consistently monitored and not allowed to exceed the maximum switch current at a given duty cycle (see the Electrical Characteristics table). If the switch current reaches this value, the SR latch (SR1) is reset regardless of the state of the comparator (A1/A2). Also not shown in the Block Diagram is the thermal shutdown circuit. If the temperature of the part exceeds approximately 165°C, the SR2 latch is set regardless of the state of the comparator (A1/A2). A full soft-start cycle will then be initiated. The current limit and thermal shutdown circuits protect the power switch as well as the external components connected to the LT3580. C1 SHDN SHUTDOWN Current Limit and Thermal Shutdown Operation L2 LT3580 C1 • Finally, the frequency foldback circuit reduces the switching frequency when the FB pin is in a nominal range of 350mV to 900mV. This feature reduces the minimum duty cycle that the part can achieve thus allowing better control of the switch current during start-up. When the FB voltage is pulled outside of this range, the switching frequency returns to normal. D1 • + • Second, the soft-start circuitry provides for a gradual ramp-up of the switch current. When the part is brought out of shutdown, the external SS capacitor is first discharged (providing protection against SHDN pin glitches and slow ramping), then an integrated 275k resistor pulls the SS pin up to ~2.2V. By connecting an external capacitor to the SS pin, the voltage ramp rate on the pin can be set. Typical values for the soft-start capacitor range from 100nF to 1μF. SS + C3 RC CSS CC 3580 F02 Figure 2. Dual Inductor Inverting Topology Results in Low Output Ripple. Coupled or Uncoupled Inductors Can Be Used. Follow Noted Phasing if Coupled 3580fg 7 LT3580 APPLICATIONS INFORMATION Setting Output Voltage Inductor Selection The output voltage is set by connecting a resistor (RFB) from VOUT to the FB pin. RFB is determined from the following equation: |V − V | RFB = OUT FB 83.3µA General Guidelines: The high frequency operation of the LT3580 allows for the use of small surface mount inductors. For high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. To improve efficiency, choose inductors with more volume for a given inductance. The inductor should have low DCR (copper wire resistance) to reduce I2R losses, and must be able to handle the peak inductor current without saturating. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology, where each inductor only carries a fraction of the total switch current. Molded chokes or chip inductors usually do not have enough core area to support peak inductor currents in the 2A to 3A range. To minimize radiated noise, use a toroidal or shielded inductor. Note that the inductance of shielded types will drop more as current increases, and will saturate more easily. See Table 1 for a list of inductor manufacturers. Thorough lab evaluation is recommended to verify that the following guidelines properly suit the final application. where VFB is 1.215V (typical) for non-inverting topologies (i.e., boost and SEPIC regulators) and 5mV (typical) for inverting topologies (see the Electrical Characteristics). Power Switch Duty Cycle In order to maintain loop stability and deliver adequate current to the load, the power NPN (Q1 in the Block Diagram) cannot remain “on” for 100% of each clock cycle. The maximum allowable duty cycle is given by: DCMAX = (TP − Min Off Time) • 100% TP where TP is the clock period and Min Off Time (found in the Electrical Characteristics) is typically 60ns. The application should be designed so that the operating duty cycle does not exceed DCMAX. Duty cycle equations for several common topologies are given below, where VD is the diode forward voltage drop and VCESAT is typically 300mV at 1.5A. For the boost topology: V −V +V DC ≅ OUT IN D VOUT + VD − VCESAT For the SEPIC or dual inductor inverting topology (see Figures 1 and 2): VD +| VOUT | DC ≅ VIN + | VOUT | + VD − VCESAT The LT3580 can be used in configurations where the duty cycle is higher than DCMAX, but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. Table 1.Inductor Manufacturers Coilcraft DO3316P, MSS7341 and LPS4018 Series www.coilcraft.com Coiltronics DR, LD and CD Series www.coiltronics.com Murata LQH55D and LQH66S Series www.murata.com Sumida CDRH5D18B/HP, CDR6D23MN, www.sumida.com CDRH6D26/HP, CDRH6D28, CDR7D28MN and CDRH105R Series TDK RLF7030 and VLCF4020 Series www.tdk.com Würth WE-PD and WE-PD2 Series www.we-online.com Minimum Inductance : Although there can be a tradeoff with efficiency, it is often desirable to minimize board space by choosing smaller inductors. When choosing an inductor, there are two conditions that limit the minimum inductance; (1) providing adequate load current, and (2) avoidance of subharmonic oscillation. Choose an inductance that is high enough to meet both of these requirements. Adequate Load Current : Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be 3580fg 8 LT3580 APPLICATIONS INFORMATION provided to a load (IOUT). In order to provide adequate load current, L should be at least: L> DC • VIN ⎛ |V |• I ⎞ 2(f) ⎜ ILIM − OUT OUT ⎟ VIN • η ⎠ ⎝ for boost, topologies, or: L> ⎛ 2(f) ⎜⎜ILIM − ⎝ DC • VIN VOUT • IOUT VIN • η ⎞ − IOUT ⎟⎟ ⎠ for the SEPIC and inverting topologies. where: L = L1||L2 for uncoupled dual inductor topologies DC = switch duty cycle (see previous section) ILIM = switch current limit, typically about 2.4A at 50% duty cycle (see the Typical Performance Characteristics section). η = power conversion efficiency (typically 88% for boost and 75% for dual inductor topologies at high currents). f = switching frequency Negative values of L indicate that the output load current IOUT exceeds the switch current limit capability of the LT3580. for the uncoupled inductor SEPIC and uncoupled inductor inverting topologies. Maximum Inductance: Excessive inductance can reduce current ripple to levels that are difficult for the current comparator (A3 in the Block Diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: LMAX = VIN – VCESAT DC • IMIN−RIPPLE f where LMAX is L1||L2 for uncoupled dual inductor topologies and IMIN-RIPPLE is typically 95mA. Current Rating: Finally, the inductor(s) must have a rating greater than its peak operating current to prevent inductor saturation resulting in efficiency loss. In steady state, the peak input inductor current (continuous conduction mode only) is given by: IL1−PEAK = VOUT •IOUT VIN • η + VIN • DC 2 • L1• f for the boost, uncoupled inductor SEPIC and uncoupled inductor inverting topologies. For uncoupled dual inductor topologies, the peak output inductor current is given by: IL2−PEAK =IOUT + VOUT • (1– DC) 2 • L2 • f Avoiding Subharmonic Oscillations: The LT3580’s internal slope compensation circuit will prevent subharmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least: V • (2 • DC – 1) L > IN (1−DC) • (f) For the coupled inductor topologies: for boost, coupled inductor SEPIC, and coupled inductor inverting topologies, or: Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice, as they have an extremely low ESR and are available in very small packages. X5R or X7R dielectrics are preferred, as L1 L2 > VIN • (2 • DC – 1) (1−DC) • (f) ⎡ ⎤ V • DC V IOUT ⎢1+ OUT ⎥ + IN ⎣ η• VIN ⎦ 2 • L • f Note: Inductor current can be higher during load transients. It can also be higher during start-up if inadequate soft-start capacitance is used. Capacitor Selection 3580fg 9 LT3580 APPLICATIONS INFORMATION these materials retain their capacitance over wider voltage and temperature ranges. A 4.7μF to 20μF output capacitor is sufficient for most applications, but systems with very low output currents may need only a 1μF or 2.2μF output capacitor. Always use a capacitor with a sufficient voltage rating. Many capacitors rated at 2.2μF to 20μF, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. Solid tantalum or OS-CON capacitors can be used, but they will occupy more board area than a ceramic and will have a higher ESR with greater output ripple. Ceramic capacitors also make a good choice for the input decoupling capacitor, which should be placed as closely as possible to the LT3580. A 2.2μF to 4.7μF input capacitor is sufficient for most applications. Table 2 shows a list of several ceramic capacitor manufacturers. Consult the manufacturers for detailed information on their entire selection of ceramic parts. Table 2. Ceramic Capacitor Manufacturers Kemet www.kemet.com Murata www.murata.com Taiyo Yuden www.t-yuden.com Compensation—Adjustment To compensate the feedback loop of the LT3580, a series resistor-capacitor network in parallel with a single capacitor should be connected from the VC pin to GND. For most applications, the series capacitor should be in the range of 470pF to 2.2nF with 1nF being a good starting value. The parallel capacitor should range in value from 10pF to 100pF with 47pF a good starting value. The compensation resistor, RC , is usually in the range of 5k to 50k. A good technique to compensate a new application is to use a 100kΩ potentiometer in place of series resistor RC. With the series capacitor and parallel capacitor at 1nF and 47pF respectively, adjust the potentiometer while observing the transient response and the optimum value for RC can be found. Figures 3a to 3c illustrate this process for the circuit of Figure 14 with a load current stepped between 400mA and 500mA. Figure 3a shows the transient response with RC equal to 1k. The phase margin is poor, as evidenced by the excessive ringing in the output voltage and inductor current. In Figure 3b, the value of RC is increased to 3k, which results in a more damped response. Figure 3c shows the results when RC is increased further to 10k. The transient response is nicely damped and the compensation procedure is complete. VOUT 200mV/DIV AC COUPLED VOUT 200mV/DIV AC COUPLED IL 0.5A/DIV IL 0.5A/DIV RC = 1k 3580 F03a 200μs/DIV RC = 3k Figure 3a. Transient Response Shows Excessive Ringing 200μs/DIV 3580 F03b Figure 3b. Transient Response Is Better VOUT 200mV/DIV AC COUPLED IL 0.5A/DIV RC = 10k 200μs/DIV 3580 F03c Figure 3c. Transient Response Is Well Damped 3580fg 10 LT3580 APPLICATIONS INFORMATION Compensation—Theory Like all other current mode switching regulators, the LT3580 needs to be compensated for stable and efficient operation. Two feedback loops are used in the LT3580— a fast current loop which does not require compensation, and a slower voltage loop which does. Standard bode plot analysis can be used to understand and adjust the voltage feedback loop. As with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. Figure 4 shows the key equivalent elements of a boost converter. Because of the fast current control loop, the power stage of the IC, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier gmp and the current controlled current source (which converts IVIN to ηVIN/VOUT • IVIN). gmp acts as a current source where the peak input current, IVIN, is proportional to the VC voltage. η is the efficiency of the switching regulator, and is typically about 88%. Note that the maximum output currents of gmp and gma are finite. The limits for gmp are in the Electrical Characteristics section (switch current limit), and gma is nominally limited to about ±12μA. – + H • VIN •IVIN VOUT RESR COUT Output Pole: P1= 2 2 • π • RL • COUT Error Amp Pole: P2 = 1 2 • π • ⎡⎣RO + RC ⎤⎦ • CC Error Amp Zero: Z1= 1 2 • π • RC • CC DC Gain: (Breaking Loop at FB Pin) ADC = A OL (0) = ∂VC ∂IVIN ∂VOUT ∂VFB • • • = ∂VFB ∂VC ∂IVIN ∂VOUT ⎛ (gma • R0 ) • gmp • ⎜ η • VVIN ⎝ ESR Zero: Z2 = RHP Zero: Z3 = RL VC CF RC CC RO R1 + gma R2 – RL ⎞ 0.5R2 • ⎟ 2 ⎠ R1+ 0.5R2 1 2 • π • RESR • COUT VIN 2 • RL 2 • π • VOUT 2 • L Phase Lead Zero: Z4 = CPL 1.215V REFERENCE • OUT High Frequency Pole: P3 > VOUT IVIN gmp From Figure 4, the DC gain, poles and zeros can be calculated as follows: Phase Lead Pole: P4 = fS 3 1 2 • π • R1• CPL 1 R2 2 •C 2•π• R2 PL R1+ 2 R1• FB 3580 F04 R2 CC: COMPENSATION CAPACITOR COUT: OUTPUT CAPACITOR CPL: PHASE LEAD CAPACITOR CF: HIGH FREQUENCY FILTER CAPACITOR gma: TRANSCONDUCTANCE AMPLIFIER INSIDE IC gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER RC: COMPENSATION RESISTOR RL: OUTPUT RESISTANCE DEFINED AS VOUT DIVIDED BY ILOAD(MAX) RO: OUTPUT RESISTANCE OF gma R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK RESR: OUTPUT CAPACITOR ESR Figure 4. Boost Converter Equivalent Model Error Amp Filter Pole: P5 = C 1 ,CF < C R •R 10 2 • π • C O • CF RC +RO The current mode zero (Z3) is a right-half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. 3580fg 11 LT3580 APPLICATIONS INFORMATION Using the circuit in Figure 14 as an example, Table 3 shows the parameters used to generate the bode plot shown in Figure 5. Table 3. Bode Plot Parameters PARAMETER VALUE UNITS COMMENT 21.8 Ω Application Specific COUT 10 μF Application Specific RESR 10 mΩ Application Specific RO 305 kΩ Not Adjustable CC 1000 pF Adjustable CF 0 pF Optional/Adjustable CPL 0 pF Optional/Adjustable RC 10 kΩ Adjustable R1 130 kΩ Adjustable R2 14.6 kΩ Not Adjustable VOUT 12 V Application Specific VIN 5 V Application Specific gma 230 μmho Not Adjustable gmp 7 mho Not Adjustable L 4.2 μH Application Specific fS 1.2 MHz Adjustable RL In Figure 5, the phase is –140° when the gain reaches 0dB giving a phase margin of 40°. The crossover frequency is 10kHz, which is more than three times lower than the frequency of the RHP zero to achieve adequate phase margin. 180 0 160 –20 140 –40 –60 PHASE –80 100 –100 80 40o AT 10kHz 60 40 –120 –140 GAIN 20 PHASE (DEG) GAIN (dB) 120 –160 –180 0 Diode Selection Schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the LT3580. The Microsemi UPS120 is a very good choice. Where the input-to-output voltage differential exceeds 20V, use the UPS140 (a 40V diode). These diodes are rated to handle an average forward current of 1A. Oscillator The operating frequency of the LT3580 can be set by the internal free-running oscillator. When the SYNC pin is driven low (< 0.4V), the frequency of operation is set by a resistor from RT to ground. An internally trimmed timing capacitor resides inside the IC. The oscillator frequency is calculated using the following formula: fOSC = 91.9 (R T + 1) where fOSC is in MHz and RT is in kΩ. Conversely, RT (in kΩ) can be calculated from the desired frequency (in MHz) using: RT = 91.9 −1 fOSC Clock Synchronization The operating frequency of the LT3580 can be synchronized to an external clock source. To synchronize to the external source, simply provide a digital clock signal into the SYNC pin. The LT3580 will operate at the SYNC clock frequency. The LT3580 will revert to the internal free-running oscillator clock after SYNC is driven low for a few free-running clock periods. Driving SYNC high for an extended period of time effectively stops the operating clock and prevents latch SR1 from becoming set (see the Block Diagram). As a result, the switching operation of the LT3580 will stop. –200 –20 10 100 1k 10k FREQUENCY (Hz) 100k 1M 3580 F05 Figure 5. Bode Plot for Example Boost Converter The duty cycle of the SYNC signal must be between 35% and 65% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: 3580fg 12 LT3580 APPLICATIONS INFORMATION (2) The SYNC frequency can always be higher than the free-running oscillator frequency, fOSC , but should not be less than 25% below fOSC . Operating Frequency Selection There are several considerations in selecting the operating frequency of the converter. The first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. For example, in products incorporating RF communications, the 455kHz IF frequency is sensitive to any noise, therefore switching above 600kHz is desired. Some communications have sensitivity to 1.1MHz, and in that case, a 1.5MHz switching converter frequency may be employed. The second consideration is the physical size of the converter. As the operating frequency goes up, the inductor and filter capacitors go down in value and size. The tradeoff is efficiency, since the switching losses due to NPN base charge (see Thermal Calculations), Schottky diode charge, and other capacitive loss terms increase proportionally with frequency. Soft-Start The LT3580 contains a soft-start circuit to limit peak switch currents during start-up. High start-up current is inherent in switching regulators in general since the feedback loop is saturated due to VOUT being far from its final value. The regulator tries to charge the output capacitor as quickly as possible, which results in large peak currents. The start-up current can be limited by connecting an external capacitor (typically 100nF to 1μF) to the SS pin. This capacitor is slowly charged to ~2.2V by an internal 275k resistor once the part is activated. SS pin voltages below ~1.1V reduce the internal current limit. Thus, the gradual ramping of the SS voltage also gradually increases the current limit as the capacitor charges. This, in turn, allows the output capacitor to charge gradually toward its final value while limiting the start-up current. In the event of a commanded shutdown or lockout (SHDN pin), internal undervoltage lockout (UVLO) or a thermal lockout, the soft-start capacitor is automatically discharged to ~200mV before charging resumes, thus assuring that the soft-start occurs after every reactivation of the chip. Shutdown The SHDN pin is used to enable or disable the chip. For most applications, SHDN can be driven by a digital logic source. Voltages above 1.38V enable normal active operation. Voltages below 300mV will shutdown the chip, resulting in extremely low quiescent current. While the SHDN voltage transitions through the lockout voltage range (0.3V to 1.24V) the power switch is disabled and the SR2 latch is set (see the Block Diagram). This causes the soft-start capacitor to begin discharging, which continues until the capacitor is discharged and active operation is enabled. Although the power switch is disabled, SHDN voltages in the lockout range do not necessarily reduce quiescent current until the SHDN voltage is near or below the shutdown threshold. Also note that SHDN can be driven above VIN or VOUT as long as the SHDN voltage is limited to less than 32V. ACTIVE (NORMAL OPERATION) 1.38V 1.24V SHDN (V) (1) SYNC may not toggle outside the frequency range of 200kHz to 2.5MHz unless it is stopped low to enable the free-running oscillator. 0.3V 0.0V (HYSTERESIS AND TOLERANCE) LOCKOUT (POWER SWITCH OFF, SS CAPACITOR DISCHARGED) SHUTDOWN (LOW QUIESCENT CURRENT) 3580 F06 Figure 6. Chip States vs SHDN Voltage Configurable Undervoltage Lockout Figure 7 shows how to configure an undervoltage lockout (UVLO) for the LT3580. Typically, UVLO is used in situations where the input supply is current-limited, has a relatively high source resistance, or ramps up/down slowly. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current-limit or latch low under low 3580fg 13 LT3580 APPLICATIONS INFORMATION VIN VIN 1.3V RUVLO1 SHDN – ACTIVE/ LOCKOUT + RUVLO1 = 11.6μA AT 1.3V RUVLO2 (OPTIONAL) GND 3580 F07 Figure 7. Configurable UVLO source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur. The shutdown pin comparator has voltage hysteresis with typical thresholds of 1.32V (rising) and 1.29V (falling). Resistor RUVLO2 is optional. RUVLO2 can be included to reduce the overall UVLO voltage variation caused by variations in SHDN pin current (see the Electrical Characteristics). A good choice for RUVLO2 is ≤10k ±1%. After choosing a value for RUVLO2 , RUVLO1 can be determined from either of the following: VIN+ −1.32V RUVLO1 = ⎛ 1.32V ⎞ ⎜ ⎟ +11.6μA ⎝ RUVLO2 ⎠ or RUVLO1 = − VIN −1.29V ⎛ 1.29V ⎞ ⎜ ⎟ +11.6μA ⎝ RUVLO2 ⎠ where VIN+ and VIN– are the VIN voltages when rising or falling respectively. For example, to disable the LT3580 for VIN voltages below 3.5V using the single resistor configuration, choose: RUVLO1 = 3.5V −1.29V =190.5k ⎛ 1.29V ⎞ ⎜ ⎟ +11.6μA ⎝ ∞ ⎠ To activate the LT3580 for VIN voltage greater than 4.5V using the double resistor configuration, choose RUVLO2 = 10k and: 4.5V −1.32V = 22.1k ⎛ 1.32V ⎞ ⎜ ⎟ +11.6μA ⎝ 10k ⎠ Internal Undervoltage Lockout The LT3580 monitors the VIN supply voltage in case VIN drops below a minimum operating level (typically about 2.3V). When VIN is detected low, the power switch is deactivated, and while sufficient VIN voltage persists, the soft-start capacitor is discharged. After VIN is detected high, the power switch will be reactivated and the soft-start capacitor will begin charging. Thermal Considerations For the LT3580 to deliver its full output power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. This is accomplished by taking advantage of the thermal pad on the underside of the IC. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into a copper plane with as much area as possible. Thermal Lockout If the die temperature reaches approximately 165°C, the part will go into thermal lockout, the power switch will be turned off and the soft-start capacitor will be discharged. The part will be enabled again when the die temperature has dropped by ~5°C (nominal). Thermal Calculations Power dissipation in the LT3580 chip comes from four primary sources: switch I2R loss, NPN base drive (AC), NPN base drive (DC), and additional input current. The following formulas can be used to approximate the power losses. These formulas assume continuous mode operation, 3580fg 14 LT3580 APPLICATIONS INFORMATION so they should not be used for calculating efficiency in discontinuous mode or at light load currents. •I V Average Input Current: IIN = OUT OUT VIN • η Switch I2R Loss: PSW = (DC)(IIN )2 (RSW ) Base Drive Loss (AC): PBAC =13n(IIN )(VOUT )(f) Base Drive Loss (DC): PBDC = (VIN )(IIN )(DC) 50 Input Power Loss: PINP = 7mA(VIN ) where: RSW = switch resistance (typically 200mΩ at 1.5A) DC = duty cycle (see the Power Switch Duty Cycle section for formulas) η = power conversion efficiency (typically 88% at high currents) Example: boost configuration, VIN = 5V, VOUT = 12V, IOUT = 0.5A, f = 1.25MHz, VD = 0.5V: IIN = 1.36A DC = 61.5% PSW = 228mW PBAC = 270mW PBDC = 84mW PINP = 35mW Total LT3580 power dissipation (PTOT) = 617mW Thermal resistance for the LT3580 is influenced by the presence of internal, topside or backside planes. To calculate die temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: TJ = TA + θJA • PTOT where TJ = junction temperature, TA = ambient temperature, θJA = 43°C/W for the 3mm × 3mm DFN package and 35°C/W to 40°C/W for the MSOP Exposed Pad package. PTOT is calculated above. VIN Ramp Rate While initially powering a switching converter application, the VIN ramp rate should be limited. High VIN ramp rates can cause excessive inrush currents in the passive components of the converter. This can lead to current and/or voltage overstress and may damage the passive components or the chip. Ramp rates less than 500mV/μs, depending on component parameters, will generally prevent these issues. Also, be careful to avoid hot-plugging. Hot-plugging occurs when an active voltage supply is “instantly” connected or switched to the input of the converter. Hot-plugging results in very fast input ramp rates and is not recommended. Finally, for more information, refer to Linear application note AN88, which discusses voltage overstress that can occur when an inductive source impedance is hot-plugged to an input pin bypassed by ceramic capacitors. Layout Hints As with all high frequency switchers, when considering layout, care must be taken to achieve optimal electrical, thermal and noise performance. One will not get advertised performance with a careless layout. For maximum efficiency, switch rise and fall times are typically in the 5ns to 10ns range. To prevent noise, both radiated and conducted, the high speed switching current path, shown in Figure 8, must be kept as short as possible. This is implemented in the suggested layout of a boost configuration in Figure 9. Shortening this path will also reduce the parasitic trace inductance. At switch-off, this parasitic inductance produces a flyback spike across the LT3580 switch. When operating at higher currents and output voltages, with poor layout, this spike can generate voltages across the LT3580 that may exceed its absolute maximum rating. A ground plane should also be used under the switcher circuitry to prevent interplane coupling and overall noise. The VC and FB components should be kept as far away as practical from the switch node. The ground for these components should be separated from the switch current path. Failure to do so can result in poor stability or subharmonic oscillation. 3580fg 15 LT3580 APPLICATIONS INFORMATION Board layout also has a significant effect on thermal resistance. The exposed package ground pad is the copper plate that runs under the LT3580 die. This is a good thermal path for heat out of the package. Soldering the pad onto the board reduces die temperature and increases the power capability of the LT3580. Provide as much copper area as possible around this pad. Adding multiple feedthroughs around the pad to the ground plane will also help. Figures 9 and 10 show the recommended component placement for the boost and SEPIC configurations, respectively. Layout Hints for Inverting Topology Figure 11 shows recommended component placement for the dual inductor inverting topology. Input bypass capacitor, C1, should be placed close to the LT3580, as shown. The load should connect directly to the output capacitor, C2, for best load regulation. You can tie the local ground into the system ground plane at the C3 ground terminal. The cut ground copper at D1’s cathode is essential to obtain low noise. This important layout issue arises due to the chopped nature of the currents flowing in Q1 and D1. If they are both tied directly to the ground plane before being combined, switching noise will be introduced into the ground plane. It is almost impossible to get rid of this noise, once present in the ground plane. The solution is to tie D1’s cathode to the ground pin of the LT3580 before the combined currents are dumped in the ground plane as drawn in Figure 2, Figure 12 and Figure 13. This single layout technique can virtually eliminate high frequency “spike” noise, so often present on switching regulator outputs. L1 D1 C1 VOUT SW LT3580 VIN HIGH FREQUENCY SWITCHING PATH C2 LOAD GND 3580 F08 Figure 8. High Speed “Chopped” Switching Path for Boost Topology 3580fg 16 LT3580 APPLICATIONS INFORMATION GND GND 1 2 C1 VIN 6 4 L1 VIN 7 3 2 C1 SYNC 8 9 L1 SHDN 5 SYNC 8 1 9 7 3 6 4 5 SHDN SW SW C2 L2 D1 VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE C2 D1 VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE C3 3580 F09 VOUT 3580 F10 VOUT Figure 9. Suggested Component Placement for Boost Topology (Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed Pad) Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance Figure 10. Suggested Component Placement for Sepic Topology (Both DFN And MSOP Packages. Not to Scale). Pin 9 (Exposed Pad) Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance GND 1 2 C1 VIN 8 9 SYNC 7 3 6 4 5 SHDN L1 SW C2 L2 D1 VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE C3 VOUT 3580 F11 Figure 11. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale). Note Cut in Ground Copper at Diode’s Cathode. Pin 9 (Exposed Pad) Must be Soldered Directly to Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance 3580fg 17 LT3580 APPLICATIONS INFORMATION –(VIN + ⏐VOUT⏐) VCESAT L1 SW C2 L2 SWX VIN –VOUT D1 Q1 + C1 C3 RLOAD + 3580 F12 Figure 12. Switch-On Phase of an Inverting Converter. L1 and L2 Have Positive dI/dt VIN + |VOUT|+ VD L1 SW VD C2 L2 SWX VIN –VOUT D1 Q1 + C1 C3 RLOAD + 3580 F13 Figure 13. Switch-Off Phase of an Inverting Converter. L1 and L2 Currents Have Negative dI/dt L1 4.2μH VIN 5V VIN C2 10μF SW SHDN RT D1 VOUT 12V 550mA GND 130k LT3580 FB VC SYNC C1 2.2μF 75k SS 10k 0.1μF 1nF 3580 F14 C1: 2.2μF, 25V, X5R, 1206 C2: 10μF, 25V, X5R, 1206 D1: MICROSEMI UPS120 L1: SUMIDA CDR6D23MN-4R2 Figure 14. 1.2MHz, 5V to 12V Boost Converter 3580fg 18 LT3580 TYPICAL APPLICATIONS 750kHz, 5V to 40V, 150mA Boost Converter L1 47μH VIN 5V VIN C2 2.2μF SW SHDN RT D1 VOUT 40V 150mA GND 464k LT3580 FB VC SYNC C1 2.2μF SS 121k 10k 0.1μF 47pF 4.7nF 3580 TA02 C1: 2.2μF, 25V, X5R, 1206 C2: 2.2μF, 50V, X5R, 1206 D1: MICROSEMI UPS140 L1: SUMIDA CDRH105R-470 Wide Input Range SEPIC Converter with 5V Output Switches at 2.5MHz C3 1μF L1 4.7μH VIN 2.6V TO 12V OPERATING 12V TO 32V TRANSIENT SHDN RT VOUT 5V, 600mA (VIN = 5V OR HIGHER) 500mA (VIN = 4V) C2 400mA (VIN = 3V) 10μF 300mA (VIN = 2.6V) L2 4.7μH SW VIN D1 GND 46.4k LT3580 FB VC SYNC C1 2.2μF SS 35.7k 10k 0.1μF 22pF 1nF 3580 TA03a C1: 2.2μF, 35V, X5R, 1206 C2: 10μF, 10V, X5R, 1206 C3: 1μF, 50V, X5R, 0805 D1: MICROSEMI UPS140 L1, L2: TDK VLCF4020T-4R7N1R2 Transient Response with 400mA to 500mA Output Load Step VOUT 100mV/DIV AC COUPLED IL1 +IL2 0.5A/DIV VIN = 12V 100μs/DIV 3580 TA03b 3580fg 19 LT3580 TYPICAL APPLICATIONS VFD (Vacuum Flourescent Display) Power Supply Switches at 2MHz to Avoid AM Band Danger High Voltage! Operation by High Voltage Trained Personnel Only D1 R2 10Ω VIN 9V TO 16V C7 1μF L1 10μH D2 D3 R1 10Ω 3.3V C6 1μF SW VIN D4 C4 1μF VOUT1 64V 40mA D5 SHDN C3 1μF LT3580 C1 4.7μF C5 1μF VOUT2 95V 80mA GND RT 383k FB VC C2 4.7μF SYNC SS 45.3k 10k 0.1μF 47pF 2.2nF 3580 TA04 C1, C2: 4.7μF, 25V, X5R, 1206 C3-C7: 1μF, 50V, X5R, 0805 D1-D4: ON SEMICONDUCTOR MBR0540 D5: MICROSEMI UPS140 L1: SUMIDA CDR6D28MNNP-100 R1, R2: 0.5W 3580fg 20 LT3580 TYPICAL APPLICATIONS High Voltage Positive Power Supply Uses Tiny 5.8mm × 5.8mm × 3mm Transformer and Switches at 200kHz Danger High Voltage! Operation by High Voltage Trained Personnel Only VOUT 350V 4.5mA (VIN = 5V) 2.5mA (VIN = 3.3V) T1 1:10.4 VIN 3.3V TO 5V 7, 8 • 1 D1 4.7μH • 5, 6 4 C2 68nF D2 SW VIN SHDN RT FOR ANY VOUT BETWEEN 50V TO 350V, CHOOSE RFB ACCORDING TO GND RFB 4.22M* LT3580 V – 1.215 RFB = OUT 83.3μA FB VC SYNC C1 2.2μF 464k SS 10k 0.47μF 100pF 10nF 3580 TA05a C1: 2.2μF, 25V, X5R, 1206 C2: TDK C3225X7R2J683M D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES D2: ON SEMICONDUCTOR MBR0540 T1: TDK LDT565630T-041 FOR 5V INPUT, KEEP MAXIMUM OUTPUT POWER AT 1.58W FOR 3.3V INPUT, KEEP MAXIMUM OUTPUT POWER AT 0.88W *MAY REQUIRE MULTIPLE SERIES RESISTORS TO COMPLY WITH MAXIMUM VOLTAGE RATINGS Start-Up Waveforms IPRIMARY 1A/DIV VOUT 50V/DIV 5V INPUT NO LOAD 2ms/DIV 3580 TA05b Switching Waveforms VOUT 2V/DIV AC COUPLED IPRIMARY 1A/DIV 5V INPUT 4.5mA LOAD 2μs/DIV 3580 TA05c 3580fg 21 LT3580 TYPICAL APPLICATIONS High Voltage Negative Power Supply Uses Tiny 5.8mm × 5.8mm × 3mm Transformer and Switches at 200kHz Danger High Voltage! Operation by High Voltage Trained Personnel Only T1 1:10.4 VIN 3.3V TO 5V 7, 8 • D1 1 4.7μH • 5, 6 C2 68nF 4 FOR ANY VOUT BETWEEN –50V TO –350V, CHOOSE RFB ACCORDING TO D2 SHDN RT RFB = SW VIN GND RFB 4.22M* LT3580 VOUT –350V 4.5mA (VIN = 5V) 2.5mA (VIN = 3.3V) FB VC SYNC C1 2.2μF 464k SS 10k 0.47μF 100pF 10nF VOUT 83.3μA FOR 5V INPUT, KEEP MAXIMUM OUTPUT POWER AT 1.58W FOR 3.3V INPUT, KEEP MAXIMUM OUTPUT POWER AT 0.88W *MAY REQUIRE MULTIPLE SERIES RESISTORS TO COMPLY WITH MAXIMUM VOLTAGE RATINGS 3580 TA06 C1: 2.2μF, 25V, X5R, 1206 C2: TDK C3225X7R2J683M D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES D2: ON SEMICONDUCTOR MBR0540 T1: TDK LDT565630T-041 3580fg 22 LT3580 TYPICAL APPLICATIONS 5V to 12V Boost Converter Switches at 2.5MHz and Uses a Tiny 4mm × 4mm × 1.7mm Inductor L1 3.3μH VIN 5V D1 VIN SHDN GND 130k LT3580 RT C2 4.7μF SW VOUT 12V 500mA FB VC SYNC C1 4.7μF SS 35.7k 10k 0.1μF 47pF 2.2nF 3580 TA07a C1, C2: 4.7μF, 25V, X5R, 1206 D1: MICROSEMI UPS120 L1: COILCRAFT LPS4018-332ML Efficiency and Power Loss vs Load Current 95 1400 90 1200 1000 80 75 800 70 600 65 400 POWER LOSS (W) EFFICIENCY (%) 85 60 200 55 50 0 100 200 300 400 LOAD CURRENT (mA) 500 0 600 3580 TA07b Transient Response with 400mA to 500mA to 400mA Output Load Step Start-Up Waveforms VOUT 5V/DIV VOUT 0.5V/DIV AC COUPLED IL 1A/DIV IL 0.5A/DIV VSHDN 1V/DIV 100μs/DIV 3580 TA07c 500mA LOAD 2ms/DIV 3580 TA07d 3580fg 23 LT3580 TYPICAL APPLICATIONS –5V Output Inverting Converter Switches at 2.5MHz and Accepts Inputs Between 3.3V to 12V C3 1μF L1 4.7μH VIN 3.3V TO 12V VIN SW SHDN VOUT –5V 800mA (VIN = 12V) C2 620mA (VIN = 5V) 10μF 450mA (VIN = 3.3V) D1 GND 60.4k LT3580 RT L2 4.7μH FB VC SYNC C1 2.2μF 35.7k SS 10k 100pF 0.1μF 2.2nF 3580 TA08a C1: 2.2μF, 25V, X5R, 1206 C2: 10μF, 25V, X5R, 1206 C3: 1μF, 50V, X5R, 0805 D1: CENTRAL SEMI CMMSH1-40 L1, L2: COILCRAFT LSP4018-472ML Efficiency and Power Loss vs Load Current 85 1200 VIN = 5V 80 1000 800 70 65 600 60 400 55 POWER LOSS (W) EFFICIENCY (%) 75 50 200 45 40 0 100 200 300 400 500 LOAD CURRENT (mA) 600 0 700 3580 TA08b 3580fg 24 LT3580 PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698 Rev C) 0.70 p0.05 3.5 p0.05 1.65 p0.05 2.10 p0.05 (2 SIDES) PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 2.38 p0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 p0.10 (4 SIDES) R = 0.125 TYP 5 0.40 p 0.10 8 1.65 p 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD8) DFN 0509 REV C 0.200 REF 0.75 p0.05 4 0.25 p 0.05 1 0.50 BSC 2.38 p0.10 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 3580fg 25 LT3580 PACKAGE DESCRIPTION MS8E Package 8-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1662 Rev F) BOTTOM VIEW OF EXPOSED PAD OPTION 1.88 (.074) 1 0.889 p 0.127 (.035 p .005) 1.88 p 0.102 (.074 p .004) 0.29 REF 1.68 (.066) 0.05 REF 5.23 (.206) MIN DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 1.68 p 0.102 3.20 – 3.45 (.066 p .004) (.126 – .136) 8 0.42 p 0.038 (.0165 p .0015) TYP 3.00 p 0.102 (.118 p .004) (NOTE 3) 0.65 (.0256) BSC 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 p 0.102 (.118 p .004) (NOTE 4) 4.90 p 0.152 (.193 p .006) DETAIL “A” 0o – 6o TYP GAUGE PLANE 1 0.53 p 0.152 (.021 p .006) DETAIL “A” 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.1016 p 0.0508 (.004 p .002) MSOP (MS8E) 0210 REV F 3580fg 26 LT3580 REVISION HISTORY (Revision history begins at Rev F) REV DATE DESCRIPTION PAGE NUMBER F 06/10 Added GND to the Pin Configuration section. 2 Revised Note 2 in the Electrical Characteristics section. 3 Revised Graph G08 in the Typical Performance Characteristics section. Revised the Applications Information section. G 09/10 4 10-11 Revised Table 3 in the Applications Information section. 12 Revised Figure 13 in the Applications Information section. 18 Updated drawing TA01a in the Typical Applications section. 24 Updated Related Parts table. 28 Added H- and MP-Grade information to Absolute Maximum Ratings, Order Information, Electrical Characteristics and Pin Functions sections. Added text at end of General Guidelines and revised equations under Avoiding Subharmonic Oscillations in Applications Information section. 2, 3, 5 8, 9 3580fg Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LT3580 TYPICAL APPLICATION 2MHz Inverting Converter Generates –12V from a 5V to 12V Input VIN 5V TO 12V SHDN RT C2 10μF D1 SW VOUT –12V 500mA (VIN = 12V) 350mA (VIN = 5V) GND 147k LT3580 FB VC SYNC C1 2.2μF SS 45.3k 10k 0.1μF 47pF 1400 VIN = 5V 85 1200 80 1000 75 800 70 600 65 400 60 2.2nF POWER LOSS (mw) VIN 90 L2 22μH EFFICIENCY (%) C3 1μF L1 10μH Efficiency and Power Loss vs Load Current 200 55 3580 TA09a C1: 2.2μF, 25V, X5R, 1206 C2: 10μF, 25V, X5R, 1206 C3: 1μF, 50V, X5R, 0805 D1: CENTRAL SEMI CMMSH1-40 L1: SUMIDA CDRH6D28NP-100NC L2: SUMIDA CDRH3D28NP-220NC 50 0 50 0 100 150 200 250 300 350 400 LOAD CURRENT (mA) 3580 TA09b RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1310 2A (ISW), 40V, 1.2MHz High Efficiency Step-Up DC/DC Converter VIN: 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1μA, ThinSOT™ Package LT1613 550mA (ISW), 1.4MHz High Efficiency Step-Up DC/DC Converter VIN: 0.9V to 10V, VOUT(MAX) = 34V, IQ = 3mA, ISD < 1μA, ThinSOT Package LT1618 1.5A (ISW), 1.25MHz High Efficiency Step-Up DC/DC Converter VIN: 1.6V to 18V, VOUT(MAX) = 35V, IQ = 1.8mA, ISD < 1μA, MS10 Package LT1930/LT1930A 1A (ISW), 1.2MHz/2.2MHz High Efficiency Step-Up DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 4.2mA/5.5mA, ISD < 1μA, ThinSOT Package LT1931/LT1931A 1A (ISW), 1.2MHz/2.2MHz High Efficiency Inverting DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 4.2mA/5.5mA, ISD < 1μA, ThinSOT Package LT1935 2A (ISW), 40V, 1.2MHz High Efficiency Step-Up DC/DC Converter VIN: 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1μA, ThinSOT Package LT1944/LT1944-1 (Dual) Dual Output 350mA (ISW), Constant Off-Time, High Efficiency Step-Up DC/DC Converter VIN: 1.2V to 15V, VOUT(MAX) = 34V, IQ = 20μA, ISD < 1μA, MS10 Package LT1945 (Dual) Dual Output Pos/Neg 350mA (ISW), Constant Off-Time, High Efficiency Step-Up DC/DC Converter VIN: 1.2V to 15V, VOUT(MAX) = ±34V, IQ = 20μA, ISD < 1μA, MS10 Package LT1946/LT1946A 1.5A (ISW), 1.2MHz/2.7MHz High Efficiency Step-Up DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 3.2mA, ISD < 1μA, MS8E Package LT1961 1.5A (ISW), 1.25MHz High Efficiency Step-Up DC/DC Converter VIN: 3V to 25V, VOUT(MAX) = 35V, IQ = 0.9mA, ISD < 6μA, MS8E Package LT3436 3A (ISW), 800kHz, 34V Step-Up DC/DC Converter VIN: 3V to 25V, VOUT(MAX) = 34V, IQ = 0.9mA, ISD < 6μA, TSSOP16E Package LT3467 1.1A (ISW), 1.3MHz High Efficiency Step-Up DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX) = 40V, IQ = 1.2mA, ISD < 1μA, ThinSOT, 2mm × 3mm DFN Packages LT3477 42V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED Driver VIN: 2.5V to 25V, VOUT(MAX) = 40V, Analog/PWM, ISD < 1μA, QFN, TSSOP20E Packages LT3479 3A Full-Featured DC/DC Converter with Soft-Start and Inrush Current Protection VIN: 2.5V to 24V, VOUT(MAX) = 40V, Analog/PWM, ISD < 1μA, DFN, TSSOP Packages 3580fg 28 Linear Technology Corporation LT 0910 REV G • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007