TI TIBPAL20R6

TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
•
•
•
(TOP VIEW)
High-Performance . . . 45 MHz Min
I
I
I
I
I
I
I
I
I
I
I
GND
Reduced ICC of 180 mA Max
Functionally Equivalent, but Faster Than
PAL20L8, PAL20R4, PAL20R6, PAL20R8
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
Preload Capability on Output Registers
Simplifies Testing
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
DEVICE
I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORT
S
PAL20L8
14
2
0
6
PAL20R4
12
0
4 (3-state buffers)
4
PAL20R6
12
0
6 (3-state buffers)
2
PAL20R8
12
0
8 (3-state buffers)
0
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for futher
reduction in board space.
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
TIBPAL20L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
NC
VCC
I
O
•
•
•
TIBPAL20L8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
High-Performance: fmax (w/o feedback)
TIBPAL20R’ -15C Series . . . 45 MHz
TIBPAL20R’ -20M Series . . . 41.6 MHz
I
I
I
NC
I
I
I
4
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I/O
I/O
I/O
NC
I/O
I/O
I/O
I
I
GND
NC
I
I
O
•
NC – No internal connection
Pin assignments in operating mode
Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state.
This feature simplifies testing because the registers can be set to an initial state prior to executing the test
sequence.
The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
Copyright  1989, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
(TOP VIEW)
(TOP VIEW)
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I
I/O
I/O
Q
Q
Q
Q
I/O
I/O
I
OE
I
I
I
NC
I
I
I
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
(TOP VIEW)
(TOP VIEW)
VCC
I
I/O
Q
Q
Q
Q
Q
Q
I/O
I
OE
I
I
I
NC
I
I
I
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
(TOP VIEW)
(TOP VIEW)
VCC
I
Q
Q
Q
Q
Q
Q
Q
Q
I
OE
I
I
I
NC
I
I
I
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
NC
Pin assignments in operating mode
2
POST OFFICE BOX 655303
OE
I
Q
24
23
22
21
20
19
18
17
16
15
14
13
I
I
GND
NC
1
2
3
4
5
6
7
8
9
10
11
12
VCC
I
Q
TIBPAL20R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
NC
TIBPAL20R8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
CLK
I
I
I
I
I
I
I
I
I
I
GND
– No internal connection
• DALLAS, TEXAS 75265
Q
Q
Q
NC
Q
Q
Q
OE
I
I/O
24
23
22
21
20
19
18
17
16
15
14
13
I
I
GND
NC
1
2
3
4
5
6
7
8
9
10
11
12
VCC
I
I/O
TIBPAL20R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
NC
TIBPAL20R6’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
CLK
I
I
I
I
I
I
I
I
I
I
GND
I/O
Q
Q
NC
Q
Q
I/O
OE
I
I/O
1
2
3
4
5
6
7
8
9
10
11
12
I
I
GND
NC
CLK
I
I
I
I
I
I
I
I
I
I
GND
VCC
I
I/O
TIBPAL20R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
NC
TIBPAL20R4’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
Q
Q
Q
NC
Q
Q
Q
TIBPAL20L8-15C, TIBPAL20R4-15C
TIBPAL20L8-20M, TIBPAL20R4-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
functional block diagrams (positive logic)
TIBPAL20L8’
&
40 X 64
20 x
I
14
20
6
20
EN ≥ 1
7
O
7
O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
6
TIBPAL20R4’
OE
CLK
EN 2
C1
&
40 X 64
20 x
I
12
≥1
8
I=0 2
Q
1D
8
Q
8
Q
8
Q
20
4
4
20
EN ≥ 1
7
I/O
7
I/O
7
I/O
7
I/O
4
4
denotes fused inputs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
functional block diagrams (positive logic)
TIBPAL20R6’
OE
CLK
EN 2
C1
&
40 X 64
20 x
I
12
≥1
8
I=0 2
Q
1D
8
Q
8
Q
8
Q
8
Q
8
Q
20
6
2
20
EN ≥ 1
7
I/O
I/O
7
2
6
TIBPAL20R8’
OE
CLK
EN 2
C1
&
40 X 64
20 x
I
12
8
≥1
I=0 2
8
Q
8
Q
8
Q
8
Q
8
Q
8
Q
8
Q
20
8
20
8
denotes fused inputs
4
Q
1D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL20L8-15C
TIBPAL20L8-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
logic diagram (positive logic)
I
1
Increment
0
I
4
8
12
16
20
24
28
32
2
36
39
23
I
First Fuse
Numbers
I
I
I
I
I
I
I
I
I
3
4
5
6
7
8
9
10
0
40
80
120
160
200
240
280
22
320
360
400
440
480
520
560
600
21
640
680
720
760
800
840
880
920
20
960
1000
1040
1080
1120
1160
1200
1240
19
1280
1320
1360
1400
1440
1480
1520
1560
18
1600
1640
1680
1720
1760
1800
1840
1880
17
1920
1960
2000
2040
2080
2120
2160
2200
16
2240
2280
2320
2360
2400
2440
2480
2520
15
14
11
13
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TIBPAL20R4-15C
TIBPAL20R4-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
logic diagram (positive logic)
CLK
1
Increment
0
I
4
8
12
16
20
24
28
32
36
39
2
23
I
First Fuse
Numbers
I
I
I
I
I
I
I
I
I
3
4
5
6
7
8
9
10
0
40
80
120
160
200
240
280
22
320
360
400
440
480
520
560
600
21
640
680
720
760
800
840
880
920
I=0
1D
960
1000
1040
1080
1120
1160
1200
1240
I=0
1D
1280
1320
1360
1400
1440
1480
1520
1560
I=0
1D
1600
1640
1680
1720
1760
1800
1840
1880
I=0
1D
I/O
Q
C1
19
Q
C1
18
Q
C1
17
Q
C1
1920
1960
2000
2040
2080
2120
2160
2200
16
2240
2280
2320
2360
2400
2440
2480
2520
15
11
14
13
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
6
20
I/O
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
I/O
I/O
I
OE
TIBPAL20R6-15C
TIBPAL20R6-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
logic diagram (positive logic)
CLK
1
Increment
0
I
4
8
12
16
20
24
28
32
36
39
2
23
I
First Fuse
Numbers
I
I
I
I
I
I
I
I
I
3
4
5
6
7
8
9
10
0
40
80
120
160
200
240
280
22
320
360
400
440
480
520
560
600
I=0
1D
640
680
720
760
800
840
880
920
I=0
1D
960
1000
1040
1080
1120
1160
1200
1240
I=0
1D
1280
1320
1360
1400
1440
1480
1520
1560
I=0
1D
1600
1640
1680
1720
1760
1800
1840
1880
I=0
1D
1920
1960
2000
2040
2080
2120
2160
2200
I=0
1D
21
I/O
Q
C1
20
Q
C1
19
Q
C1
18
Q
C1
17
Q
C1
16
Q
C1
2240
2280
2320
2360
2400
2440
2480
2520
15
11
14
13
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
I/O
I
OE
7
TIBPAL20R8-15C
TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
logic diagram (positive logic)
CLK
1
Increment
0
I
4
8
12
16
20
24
28
32
36
39
2
23
I
First Fuse
Numbers
I
I
I
I
I
I
I
I
I
3
4
5
6
7
8
9
10
0
40
80
120
160
200
240
280
I=0
1D
320
360
400
440
480
520
560
600
I=0
1D
640
680
720
760
800
840
880
920
I=0
1D
960
1000
1040
1080
1120
1160
1200
1240
I=0
1D
1280
1320
1360
1400
1440
1480
1520
1560
I=0
1D
1600
1640
1680
1720
1760
1800
1840
1880
I=0
1D
1920
1960
2000
2040
2080
2120
2160
2200
I=0
1D
2240
2280
2320
2360
2400
2440
2480
2520
I=0
1D
Q
C1
21
Q
C1
20
Q
C1
19
Q
C1
18
Q
C1
17
Q
C1
16
Q
C1
15
Q
C1
11
14
13
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
8
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
I
OE
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
5.5
V
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
High-level output current
– 3.2
mA
IOL
fclock†
Low-level output current
24
mA
45
MHz
High-level input voltage
2
0.8
Clock frequency
0
tw†
Pulse duration, clock
tsu†
th†
Setup time, input or feedback before clock↑
High
10
Low
12
Hold time, input or feedback after clock↑
0
0
POST OFFICE BOX 655303
ns
15
TA
Operating free-air temperature
† fclock, tw, tsu, and th do not apply for TIBPAL20L8’.
• DALLAS, TEXAS 75265
V
ns
ns
25
75
°C
9
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
VOH
VOL
O, Q outputs
IOZH
VCC = 4.75 V,
VCC = 4.75 V,
II = – 18 mA
IOH = – 3.2 mA
VCC = 4.75 V,
IOL = 24 mA
VCC = 5.25 V,
VO = 2.7 V
VCC = 5.25 V,
VO = 0.4 V
VCC = 5.25 V,
VCC = 5.25 V,
VI = 5.5 V
VI = 2.7 V
IOS§
VCC = 5.25 V,
VCC = 5.25 V,
VI = 0.4 V
VO = 0.5 V
ICC
VCC = 5.25 V,
Outputs open,
VI = 0,
OE at VIH
I/O ports
O, Q outputs
IOZL
I/O ports
II
IIH‡
IIL‡
MIN
TYP†
MAX
UNIT
–0.8
– 1.5
V
2.4
V
0.3
0.5
20
100
– 20
– 250
0.1
– 30
V
µA
µA
mA
25
µA
– 0.25
mA
–70
– 130
mA
120
180
mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
PARAMETER
fmax¶
TO
(OUTPUT)
MIN
TYP†
With feedback
37
40
Without feedback
45
50
TEST CONDITION
UNIT
MHz
tpd
tpd
I, I/O
O, I/O
R1 = 200 Ω,
12
15
ns
CLK↑
Q
R2 = 390 Ω,
8
12
ns
ten
tdis
OE
Q
See Figure 3
10
15
ns
OE↑
Q
8
12
ns
I, I/O
O, I/O
12
18
ns
I, I/O
O, I/O
12
15
ns
ten
tdis
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
¶
1
,
,
f max(with feedback)
1
t su
t
(CLK to Q) f max(without feedback)
t w high
t w low
pd
fmax does not apply for TIBPAL20L8,.
+
10
MAX
+
)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
)
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
5.5
V
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
–2
mA
IOL
fclock†
Low-level output current
12
mA
41.6
MHz
High-level input voltage
2
Clock frequency
0
tw†
Pulse duration, clock
tsu†
th†
Setup time, input or feedback before clock↑
High
12
Low
12
20
Hold time, input or feedback after clock↑
0
TA
Operating free-air temperature
† fclock, tw, tsu, and th do not apply for TIBPAL20L8’.
–55
POST OFFICE BOX 655303
ns
• DALLAS, TEXAS 75265
ns
ns
25
125
°C
11
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V,
II = – 18 mA
IOH = – 2 mA
VOL
IOZH
VCC = 4.5 V,
VCC = 5.5 V,
IOL = 12 mA
VO = 2.7 V
VCC = 5.5 V,
VO = 0.4 V
VCC = 5.5 V,
VI = 5.5 V
O, Q outputs
IOZL‡
I/O ports
II
I/O ports
IIH‡
VCC = 5.5 V,
VI = 2.7 V
IIL‡
IOS§
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 0.5 V
ICC
VCC = 5.5 V,
Outputs open,
VI = 0,
OE = VIH
All others
MIN
2.4
TYP†
MAX
UNIT
–0.8
– 1.5
V
3.2
0.3
V
0.5
V
100
µA
– 20
µA
– 250
1
mA
100
µA
25
– 30
– 0.25
mA
–70
– 250
mA
120
180
mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
PARAMETER
fmax¶
tpd
tpd
ten
tdis
ten
tdis
TO
(OUTPUT)
MIN
TYP†
With feedback
28.5
40
Without feedback
41.6
50
TEST CONDITION
MAX
UNIT
MHz
I, I/O
O, I/O
R1 = 390 Ω,
12
20
ns
CLK↑
Q
R2 = 750 Ω,
8
15
ns
OE
Q
See Figure 3
10
20
ns
OE↑
Q
8
20
ns
I, I/O
O, I/O
12
25
ns
I, I/O
O, I/O
12
20
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. Set VO at 0.5 V to
avoid test equipment ground degradation.
¶
1
,
,
f max(with feedback)
1
t su
t
(CLK to Q) f max(without feedback)
t w high
t w low
pd
fmax does not apply for TIBPAL20L8,.
+
12
+
)
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)
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With VCC at 5 volts and Pin 1 at VIL, raise Pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 13 to VIL. Preload can be verified by observing the
voltage level at the output pin.
VIHH
Pin 13
VIL
td
tsu
tw
td
VIH
Pin 1
VIL
VIH
Registered I/O
Input
VOH
Output
VIL
VOL
Figure 1. Preload Waveforms
NOTES: 2. Pin numbers shown are for JT, NT, and W packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 v
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TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
VCC
5V
4V
tpd†
(600 ns TYP, 1000 ns MAX)
VOH
Active Low
Registered Output
1.5 V
VOL
tsu‡
VIH
CLK
1.5 V
1.5 V
VIL
tw
† This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡ This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
14
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TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT  PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
PARAMETER MEASUREMENT INFORMATION
5V
S1
R1
From Output
Under Test
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
3-STATE OUTPUTS
1.5 V
1.5 V
tw
th
(3.5 V) [3 V]
Data
Input
1.5 V
(3.5 V) [3 V]
(0.3 V) [0]
In-Phase
Output
VOH
1.5 V
VOL
tpd
tpd
1.5 V
VOH
1.5 V
VOL
(3.5 V) [3 V]
1.5 V
Waveform 1
S1 Closed
(see Note B)
tdis
1.5 V
≈ 3.3 V
VOL +0.5 V
VOL
tdis
ten
Waveform 2
S1 Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
(0.3 V) [0]
ten
tpd
1.5 V
1.5 V
(0.3 V) [0]
Output
Control
(low-level
enabling)
1.5 V
tpd
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
(3.5 V) [3 V]
Low-Level
Pulse
1.5 V
(0.3 V) [0]
Input
1.5 V
(0.3 V) [0]
(0.3 V) [0]
tsu
Out-of-Phase
Output
(see Note D)
(3.5 V) [3 V]
High-Level
Pulse
(3.5 V) [3 V]
Timing
Input
VOH
1.5 V
VOH –0.5 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ). PRR ≤ 1 MHz,
tr = tf ≤ 2 ns, duty cycle = 50%. For M suffix, use the voltage levels indicated in brackets [ ]. PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty cycle
= 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 3. Load Circuit and Voltage Waveforms
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D0892
1992 Texas Instruments Incorporated
SRPS021
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