TI TIBPAL20R6-5CFN

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
•
•
•
•
TIBPAL20L8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
I
I
I
I
I
I
I
I
I
I
I
GND
Functionally Equivalent, but Faster Than,
Existing 24-Pin PLDs
DEVICE
I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORT
S
PAL20L8
14
2
0
6
PAL20R4
12
0
4 (3-state buffers)
4
PAL20R6
12
0
6 (3-state buffers)
2
PAL20R8
12
0
8 (3-state buffers)
0
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
(TOP VIEW)
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
Security Fuse Prevents Duplication
24
2
TIBPAL20L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
Preload Capability on Output Registers
Simplifies Testing
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
1
I
I
I
NC
VCC
I
O
•
High-Performance Operation:
fmax (no feedback)
TIBPAL20R’ -5C Series . . . 125 MHz Min
TIBPAL20R’ -7M Series . . . 100 MHz Min
fmax (internal feedback)
TIBPAL20R’ -5C Series . . . 125 MHz Min
TIBPAL20R’ -7M Series . . . 100 MHz Min
fmax (external feedback)
TIBPAL20R’ -5C Series . . . 117 MHz Min
TIBPAL20R’ -7M Series . . . 74 MHz Min
Propagation Delay
TIBPAL20L8-5C Series . . . 5 ns Max
TIBPAL20L8-7M Series . . . 7 ns Max
TIBPAL20R’ -5C Series
(CLK-to-Q) . . . 4 ns Max
TIBPAL20R’ -7M Series
(CLK-to-Q) . . . 6.5 ns Max
I
I
I
NC
I
I
I
4
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I/O
I/O
I/O
NC
I/O
I/O
I/O
I
I
GND
NC
I
I
O
•
NC – No internal connection
Pin assignments in operating mode
description
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board.
The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
Copyright  1992, Texas Instruments Incorporated
This document contains information on products in more than one
phase of development. The status of each device is indicated on the
page(s) specifying its electrical characteristics.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
(TOP VIEW)
(TOP VIEW)
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I
I/O
I/O
Q
Q
Q
Q
I/O
I/O
I
OE
I
I
I
NC
I
I
I
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
(TOP VIEW)
(TOP VIEW)
VCC
I
I/O
Q
Q
Q
Q
Q
Q
I/O
I
OE
I
I
I
NC
I
I
I
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
(TOP VIEW)
(TOP VIEW)
VCC
I
Q
Q
Q
Q
Q
Q
Q
Q
I
OE
I
I
I
NC
I
I
I
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
NC
Pin assignments in operating mode
2
POST OFFICE BOX 655303
OE
I
Q
24
23
22
21
20
19
18
17
16
15
14
13
I
I
GND
NC
1
2
3
4
5
6
7
8
9
10
11
12
VCC
I
Q
TIBPAL20R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
NC
TIBPAL20R8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
CLK
I
I
I
I
I
I
I
I
I
I
GND
– No internal connection
• DALLAS, TEXAS 75265
Q
Q
Q
NC
Q
Q
Q
OE
I
I/O
24
23
22
21
20
19
18
17
16
15
14
13
I
I
GND
NC
1
2
3
4
5
6
7
8
9
10
11
12
VCC
I
I/O
TIBPAL20R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
NC
TIBPAL20R6’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
CLK
I
I
I
I
I
I
I
I
I
I
GND
I/O
Q
Q
NC
Q
Q
I/O
OE
I
I/O
1
2
3
4
5
6
7
8
9
10
11
12
I
I
GND
NC
CLK
I
I
I
I
I
I
I
I
I
I
GND
VCC
I
I/O
TIBPAL20R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
NC
TIBPAL20R4’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
Q
Q
Q
NC
Q
Q
Q
TIBPAL20L8-5C, TIBPAL20R4-5C
TIBPAL20L8-7M, TIBPAL20R4-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
functional block diagrams (positive logic)
TIBPAL20L8’
&
40 X 64
20 x
I
14
20
6
20
EN ≥ 1
7
O
7
O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
6
TIBPAL20R4’
OE
CLK
EN 2
C1
&
40 X 64
20 x
I
12
≥1
8
I=0 2
Q
1D
8
Q
8
Q
8
Q
20
4
4
20
EN ≥ 1
7
I/O
7
I/O
7
I/O
7
I/O
4
4
denotes fused inputs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
functional block diagrams (positive logic)
TIBPAL20R6’
OE
CLK
EN 2
C1
&
40 X 64
20 x
I
12
≥1
8
I=0 2
Q
1D
8
Q
8
Q
8
Q
8
Q
8
Q
20
6
2
20
EN ≥ 1
7
I/O
I/O
7
2
6
TIBPAL20R8’
OE
CLK
EN 2
C1
&
40 X 64
20 x
I
12
8
≥1
I=0 2
8
Q
8
Q
8
Q
8
Q
8
Q
8
Q
8
Q
20
8
20
8
denotes fused inputs
4
Q
1D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL20L8-5C
TIBPAL20L8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
I
1
Increment
0
I
4
8
12
16
20
24
28
32
2
36
39
23
I
First Fuse
Numbers
I
I
I
I
I
I
I
I
I
3
4
5
6
7
8
9
10
0
40
80
120
160
200
240
280
22
320
360
400
440
480
520
560
600
21
640
680
720
760
800
840
880
920
20
960
1000
1040
1080
1120
1160
1200
1240
19
1280
1320
1360
1400
1440
1480
1520
1560
18
1600
1640
1680
1720
1760
1800
1840
1880
17
1920
1960
2000
2040
2080
2120
2160
2200
16
2240
2280
2320
2360
2400
2440
2480
2520
15
14
11
13
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TIBPAL20R4-5C
TIBPAL20R4-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
CLK
1
Increment
0
I
4
8
12
16
20
24
28
32
36
39
2
23
I
First Fuse
Numbers
I
I
I
I
I
I
I
I
I
3
4
5
6
7
8
9
10
0
40
80
120
160
200
240
280
22
320
360
400
440
480
520
560
600
21
640
680
720
760
800
840
880
920
I=0
1D
960
1000
1040
1080
1120
1160
1200
1240
I=0
1D
1280
1320
1360
1400
1440
1480
1520
1560
I=0
1D
1600
1640
1680
1720
1760
1800
1840
1880
I=0
1D
I/O
Q
C1
19
Q
C1
18
Q
C1
17
Q
C1
1920
1960
2000
2040
2080
2120
2160
2200
16
2240
2280
2320
2360
2400
2440
2480
2520
15
11
14
13
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
6
20
I/O
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
I/O
I/O
I
OE
TIBPAL20R6-5C
TIBPAL20R6-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
CLK
1
Increment
0
I
4
8
12
16
20
24
28
32
36
39
2
23
I
First Fuse
Numbers
I
I
I
I
I
I
I
I
I
3
4
5
6
7
8
9
10
0
40
80
120
160
200
240
280
22
320
360
400
440
480
520
560
600
I=0
1D
640
680
720
760
800
840
880
920
I=0
1D
960
1000
1040
1080
1120
1160
1200
1240
I=0
1D
1280
1320
1360
1400
1440
1480
1520
1560
I=0
1D
1600
1640
1680
1720
1760
1800
1840
1880
I=0
1D
1920
1960
2000
2040
2080
2120
2160
2200
I=0
1D
21
I/O
Q
C1
20
Q
C1
19
Q
C1
18
Q
C1
17
Q
C1
16
Q
C1
2240
2280
2320
2360
2400
2440
2480
2520
15
11
14
13
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
I/O
I
OE
7
TIBPAL20R8-5C
TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
CLK
1
Increment
0
I
4
8
12
16
20
24
28
32
36
39
2
23
I
First Fuse
Numbers
I
I
I
I
I
I
I
I
I
3
4
5
6
7
8
9
10
0
40
80
120
160
200
240
280
I=0
1D
320
360
400
440
480
520
560
600
I=0
1D
640
680
720
760
800
840
880
920
I=0
1D
960
1000
1040
1080
1120
1160
1200
1240
I=0
1D
1280
1320
1360
1400
1440
1480
1520
1560
I=0
1D
1600
1640
1680
1720
1760
1800
1840
1880
I=0
1D
1920
1960
2000
2040
2080
2120
2160
2200
I=0
1D
2240
2280
2320
2360
2400
2440
2480
2520
I=0
1D
Q
C1
21
Q
C1
20
Q
C1
19
Q
C1
18
Q
C1
17
Q
C1
16
Q
C1
15
Q
C1
11
14
13
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
8
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
I
OE
TIBPAL20L8-5C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage (see Note 2)
IOL
TA
Low-level output current
High-level input voltage (see Note 2)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
5.5
V
2
0.8
High-level output current
Operating free-air temperature
0
25
V
– 3.2
mA
24
mA
75
°C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
II = – 18 mA
IOH = – 3.2 mA
VOL
IOZH‡
IOZL‡
VCC = 4.75 V,
VCC = 5.25 V,
IOL = 24 mA
VO = 2.7 V
VCC = 5.25 V,
VCC = 5.25 V,
VO = 0.4 V
VI = 5.5 V
VCC = 5.25 V,
VCC = 5.25 V,
VI = 2.7 V
VI = 0.4 V
IOS§
ICC
VCC = 5.25 V,
VCC = 5.25 V,
VO = 0.5 V
VI = 0,
Ci
f = 1 MHz,
Co
f = 1 MHz,
VI = 2 V
VO = 2 V
II
IIH‡
IIL‡
MIN
TYP†
MAX
UNIT
– 0.8
– 1.5
V
2.4
2.7
0.3
– 30
–70
Outputs open
V
0.5
V
100
µA
–100
µA
100
µA
25
µA
–250
µA
–130
mA
210
mA
8.5
pF
10
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
I, I/O
O, I/O
with up to 4 outputs
switching
I, I/O
O, I/O
with more than 4
outputs switching
tpd
ten
tdis
I, I/O
O, I/O
I, I/O
O, I/O
TEST
CONDITIONS
R1 = 200 Ω,
R2 = 200 Ω,
See Figure 8
TIBPAL20L8-5CFN
TIBPAL20L8-5CJT
TIBPAL20L8-5CNT
MIN
MAX
MIN
MAX
1.5
5
1.5
5
1.5
5
1.5
5.5
2
7
2
7
ns
2
7
2
7
ns
UNIT
ns
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TIBPAL20R4-5C, TIBPAL20R6-5C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
5.5
V
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage (see Note 2)
IOL
fclock
Low-level output current
tw
Pulse duration, clock
tsu
th
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
0
TA
Operating free-air temperature
0
High-level input voltage (see Note 2)
2
0.8
High-level output current
– 3.2
Clock frequency
0
High
4
Low
4
V
mA
24
mA
125
MHz
ns
4.5
ns
ns
25
75
°C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL20R4-5C, TIBPAL20R6-5C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
II = – 18 mA
IOH = – 3.2 mA
VOL
IOZH‡
IOZL‡
VCC = 4.75 V,
VCC = 5.25 V,
IOL = 24 mA
VO = 2.7 V
VCC = 5.25 V,
VCC = 5.25 V,
VO = 0.4 V
VI = 5.5 V
VCC = 5.25 V,
VCC = 5.25 V,
VI = 2.7 V
VI = 0.4 V
VCC = 5.25 V,
VCC = 5.25 V,
VO = 0.5 V
VI = 0,
II
IIH‡
IIL‡
IOS§
ICC
I
Ci
f = 1 MHz,
I/O
Q
TYP†
MAX
UNIT
– 0.8
– 1.5
V
2.4
2.7
0.3
– 30
–70
Outputs open
f = 1 MHz,
V
0.5
V
100
µA
–100
µA
100
µA
25
µA
– 250
µA
–130
mA
210
mA
8.5
VI = 2 V
CLK/OE
Co
MIN
pF
7.5
10
VO = 2 V
pF
7
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
TIBPAL20R4-5CFN
TIBPAL20R6-5CFN
MIN
fmax¶
TYP†
MAX
125
125
with internal feedback (counter configuration)
125
125
with external feedback
117
TYP†
Q
1.5
CLK↑
Internal feedback
R1 = 200 Ω,
MAX
MHz
4
tpd
ten
I, I/O
I/O
R2 = 200 Ω,
1.5
5
OE↓
Q
See Figure 8
1.5
6
tdis
ten
OE↑
Q
1
I, I/O
I/O
I, I/O
I/O
1.5
4.5
ns
3.5
ns
1.5
5
ns
1.5
6
ns
6.5
1
7
ns
2
7
2
7
ns
2
7
2
7
ns
3.5
Skew between registered outputs
UNIT
111
CLK↑
tf
tsk (o) #
MIN
without feedback
tpd
tpd
tdis
tr
TIBPAL20R4-5CJT
TIBPAL20R4-5CNT
TIBPAL20R6-5CJT
TIBPAL20R6-5CNT
1.5
1.5
ns
1.5
1.5
ns
0.5
0.5
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
¶ See ’fmax Specification’ near the end of this data sheet.
# tsk (o) is the skew time between registered outputs.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
5.5
V
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage (see Note 2)
IOL
fclock
Low-level output current
tw
Pulse duration, clock
tsu
th
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
0
TA
Operating free-air temperature
0
High-level input voltage (see Note 2)
2
0.8
High-level output current
– 3.2
Clock frequency
0
High
4
Low
4
V
mA
24
mA
125
MHz
ns
4.5
ns
ns
25
75
°C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
12
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• DALLAS, TEXAS 75265
TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
electrical characteristics over recommended operating free-air temperature range
TIBPAL20R8-5CJT
TIBPAL20R8-5CNT
TIBPAL20R8-5CFN
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
– 0.8
– 1.5
MIN
MAX
– 0.8
– 1.5
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
II = – 18 mA
IOH = –3.2 mA
VOL
IOZH
VCC = 4.75 V,
VCC = 5.25 V,
IOL = 24 mA
VO = 2.7 V
IOZL
II
VCC = 5.25 V,
VCC = 5.25 V,
VO = 0.4 V
VI = 5.5 V
IIH
IIL
VCC = 5.25 V,
VCC = 5.25 V,
VI = 2.7 V
VI = 0.4 V
IOS‡
ICC
VCC = 5.25 V,
VCC = 5.25 V,
VO = 0.5 V
VI = 0, Outputs open
8.5
6.5
f = 1 MHz,
VI = 2 V
7.5
5.5
f = 1 MHz,
VO = 2 V
10
8
2.4
2.7
–70
CLK/OE
Co
V
2.7
0.5
0.3
V
0.5
V
100
100
µA
–100
–100
µA
100
100
µA
25
25
µA
– 250
– 30
–130
– 30
–70
210
I
Ci
2.4
0.3
UNIT
TYP†
– 250
µA
–130
mA
210
mA
pF
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
TIBPAL20R8-5CFN
MIN
fmax§
TYP†
MAX
TIBPAL20R8-5CJT
TIBPAL20R8-5CNT
MIN
without feedback
125
125
with internal feedback (counter configuration)
125
125
with external feedback
117
111
CLK↑
Q
with up to 4 outputs
switching
CLK↑
Q
with more than 4
outputs switching
tpd
R1 = 200 Ω,
R2 = 200 Ω,
See Figure 8
TYP†
UNIT
MAX
MHz
1.5
4
1.5
4
1.5
4
1.5
4.5
ns
tpd¶
ten
CLK↑
Internal feedback
3.5
ns
OE↓
Q
1.5
6
1.5
6
ns
tdis
OE↑
Q
1
6.5
1
7
ns
3.5
tr
tf
tsk (o)#
Skew between outputs
1.5
1.5
ns
1.5
1.5
ns
0.5
0.5
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
§ See ’fmax Specification’ near the end of this data sheet.
¶ This parameter is calculated from the measured fmax with internal feedback in a counter configuration (see Figure 4 for illustration).
# tsk (o) is the skew time between registered outputs.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
5.5
V
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage (see Note 2)
0.8
V
High-level output current
–2
mA
IOL
fclock†
Low-level output current
12
mA
100
MHz
High-level input voltage (see Note 2)
2
Clock frequency
0
tw†
Pulse duration, clock
tsu†
th†
Setup time, input or feedback before clock↑
High
5
Low
5
ns
7
Hold time, input or feedback after clock↑
ns
0
TA
Operating free-air temperature
† fclock, tw, tsu, and th do not apply to TIBPAL16L8’
–55
ns
25
125
°C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
14
POST OFFICE BOX 655303
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TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK
VOH
VOL
0, Q outputs
IOZH
I/O ports
0, Q outputs
IOZL
I/O ports
II
I/O ports
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = – 18 mA
IOH = – 2 mA
VCC = 4.5 V,
IOL = 12 mA
VCC = 5.5 V,
VO = 2.7 V
VCC = 5.5 V,
VO = 0.4 V
VCC = 5.5 V,
VI = 5.5 V
VCC = 5.5 V,
VI = 2.7 V
IIL
IOS‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 0.5 V
ICC
VCC = 5.5 V,
VI = GND,
IIH
All others
I
Ci
CLK/OE
f = 1 MHz,
MIN
2.4
TYP†
MAX
UNIT
– 0.8
– 1.5
V
2.7
0.25
V
0.5
20
100
– 20
– 250
– 30
–70
Outputs open
µA
1
mA
µA
– 250
µA
– 130
mA
220
mA
8.5
VI = 2 V
µA
100
25
OE = VIH,
V
pF
7.5
Co
f = 1 MHz,
VO = 2 V
10
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
fmax§
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITION
MIN
without feedback
100
with internal feedback
(counter configuration)
100
MAX
UNIT
MHz
R1 = 390 Ω,
74
tpd
tpd
I, I/O
O, I/O
R2 = 750 Ω,
1
7
ns
CLK
Q
See Figure 8
1
7
ns
ten
tdis
OE↓
Q
1
8
ns
OE↑
Q
1
10
ns
ten
tdis
I, I/O
O, I/O
1
9
ns
I, I/O
O, I/O
1
10
ns
with external feedback
§ See ’fmax Specification’ near the end of this data sheet. fmax does not apply for TIBPAL20L8′. fmax with external feedback is not production tested
and is calculated from the equation found in the fmax specifications section.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
asynchronous preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With VCC at 5 volts and Pin 1 at VIL, raise Pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Lower Pin 13 to 5 V.
Remove output voltage, then lower Pin 13 to VIL. Preload can be verified by observing the
voltage level at the output pin.
VIHH
Pin 13
5V
VIL
td
tsu + th
td
VOH
VIH
Registered Output
Input
Output
VIL
Figure 1. Asynchronous Preload Waveforms
NOTE 3: td = tsu = th = 100 ns to 1000 ns, VIHH = 10.25 V to 10.75 V
16
POST OFFICE BOX 655303
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VOL
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
power-up reset, see Figure 2
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
VCC
5V
4V
tpd†
(600 ns typ, 1000 ns MAX)
VOH
Active Low
Registered Output
1.5 V
VOL
tsu‡
VIH
Clock
1.5 V
1.5 V
VIL
tw
† This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡ This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
POST OFFICE BOX 655303
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17
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
fmax SPECIFICATIONS
fmax without feedback, see Figure 3
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (tsu + th).
However, the minimum fmax is determined by the minimum clock period (tw high + tw low).
1
1
Thus, f max without feedback
or (t
t ).
(t whigh
t wlow)
su
h
+
)
)
CLK
Logic
Array
C1
1D
tsu + th
or
tw high + tw low
Figure 3. fmax Without Feedback
fmax with internal feedback, see Figure 4
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
1
Thus, f max with internal feedback
(t su
t
CLK to FB) .
pd
+
)
* *
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
Logic
Array
C1
1D
tsu
tpd CLK - to - FB
Figure 4. fmax With Internal Feedback
18
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TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
fmax SPECIFICATIONS
fmax with external feedback, see Figure 5
This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals
(tsu + tpd CLK-to-Q).
1
Thus, f max with external feedback
(t su
t
CLK to Q).
pd
+
)
* *
CLK
Logic
Array
Next Device
C1
1D
tsu
tpd CLK - to - Q
tsu
Figure 5. fmax With External Feedback
POST OFFICE BOX 655303
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19
TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
THERMAL INFORMATION
thermal management of the TIBPAL20R8-5C
Thermal management of the TIBPAL20R8-5CNT and TIBPAL20R8-5CFN is necessary when operating at
certain conditions of frequency, output loading, and outputs switching simultaneously. The device and system
application will determine the appropriate level of management.
Determining the level of thermal management is based on factors such as power dissipation (PD), ambient
temperature (TA), and transverse airflow (FPM). Figures 6 (a) and 6 (b) show the relationship between ambient
temperature and transverse airflow at given power dissipation levels. The required transverse airflow can be
determined at a particular ambient temperature and device power dissipation level in order to ensure the device
specifications.
Figure 7 illustrates how power dissipation varies as a function of frequency and the number of outputs switching
simultaneously. It should be noted that all outputs are fully loaded (CL = 50 pF). Since the condition of eight fully
loaded outputs represents the worst-case condition, each application must be evaluated accordingly.
MINIMUM TRANSVERSE AIR FLOW
vs
AMBIENT TEMPERATURE
MINIMUM TRANSVERSE AIR FLOW
vs
AMBIENT TEMPERATURE
1000
Minimum Transverse Air Flow – ft/min
Minimum Transverse Air Flow – ft/min
1000
800
PD = 1.6 W
PD = 1.4 W
PD = 1.2 W
PD = 1 W
PD = 0.8 W
PD = 0.6 W
600
400
200
800
PD = 1.6 W
PD = 1.4 W
PD = 1.2 W
PD = 1 W
PD = 0.8 W
PD = 0.6 W
600
400
200
0
0
0
10
20
30
40
50
60
70
0
80
TA – Ambient Temperature – °C
20
30
40
50
60
TA – Ambient Temperature – °C
(b) TIBPAL20R8-5CFN
(a) TIBPAL20-5CNT
Figure 6
20
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
70
80
TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
THERMAL INFORMATION
POWER DISSIPATION
vs
FREQUENCY
P – Power Dissipation – mW
D
1800
VCC = 5 V
TA = 25 °C
CL = 50 pF
1600
8 Outputs Switching
7 Outputs Switching
6 Outputs Switching
5 Outputs Switching
4 Outputs Switching
3 Outputs Switching
2 Outputs Switching
1 Output Switching
1400
1200
1000
800
600
1
2
4
10
20
40
100
200
f – Frequency – MHz
Figure 7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
PARAMETER MEASUREMENT INFORMATION
5V
S1
R1
From Output
Under Test
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3V
3V
1.5 V
Timing
Input
0
th
tsu
3V
1.5 V
1.5 V
Data
Input
1.5 V
High-Level
Pulse
0
tw
Low-Level
Pulse
3V
1.5 V
0
(see Note B)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
3V
1.5 V
1.5 V
0
Input
tpd
tpd
80 %
In-Phase
Output
1.5 V
20 %
tr
tpd
Out-of-Phase
Output
(see Note D)
20 %
1.5 V
VOH
1.5 V
VOL
tf
tpd
VOH
1.5 V
80 %
tf
tr
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
0
(see Note B)
Output
Control
(low-level
enabling)
1.5 V
1.5 V
0
(see Note B)
ten
tdis
≈ 2.7 V
1.5 V
Waveform 1
S1 Closed
(see Note C)
VOL + 0.5 V
VOL
tdis
ten
Waveform 2
S1 Open
(see Note C)
VOH
1.5 V
VOH – 0.5 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. All input pulses have the following characteristics: For C suffix, PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%; For M suffix,
PRR ≤ 10 MHz, tr = tf ≤ 2 ns, duty cycle = 50%
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 8. Load Circuit and Voltage Waveforms
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
metastable characteristics of TIBPAL20R4-5C, TIBPAL20R6-5C, and TIBPAL20R8-5C
At some point a system designer is faced with the problem of synchronizing two digital signals operating at two
different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock
through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time
specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop
can influence overall system reliability.
Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said
to be in the metastable state if the output hangs up in the region between VIL and VIH. This metastable condition
lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum
propagation delay time (CLK to Q max).
From a system engineering standpoint, a designer cannot use the specified data sheet maximum for
propagation delay time when using the flip-flop as a data synchronizer – how long to wait after the specified data
sheet maximum must be known before using the data in order to guarantee reliable system operation.
The circuit shown in Figure 9 can be used to evaluate MTBF (Mean Time Between Failure) and ∆t for a selected
flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in opposite states.
When the Q output of the DUT is higher than 2 V or lower than 0.8 V, the comparators are at the same logic level.
The outputs of the two comparators are sampled a selected time (∆t) after SCLK. The exclusive OR gate detects
the occurrence of a failure and increments the failure counter.
DUT
Noise
Generator
Data in
VIH
Comparator
1D
MTBF
Counter
1D
1D
C1
+
C1
VIL
Comparator
SCLK
C1
1D
C1
SCLK + ∆ t
Figure 9. Metastable Evaluation Test Circuit
In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied
so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 10.
Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state.
Data
SCLK
SCLK + ∆ t
MTBF
+
∆t
∆t
Time (sec)
# Failures
trec = ∆ t – CLK to Q (max)
Figure 10. Timing Diagram
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
By using the described test circuit, MTBF can be determined for several different values of ∆t (see Figure 9).
Plotting this information on semilog scale demonstrates the metastable characteristics of the selected flip-flop.
Figure 11 shows the results for the TIBPAL20’-5C operating at 1 MHz.
10 9
10 yr
10 8
1 yr
MTBF (s)
10 7
10 6
1 mo
1 wk
10 5
1 day
10 4
1 hr
10 3
10 2
1 min
10 1
10 s
0
10
fclk = 1 MHz
fdata = 500 kHz
20
30
40
∆ t (ns)
50
60
70
Figure 11. Metastable Characteristics
From the data taken in the above experiment, an equation can be derived for the metastable characteristics at
other clock frequencies.
The metastable equation: 1
f
x f
x C1 e ( C2 x Dt)
data
SCLK
MTBF
*
+
The constants C1 and C2 describe the metastable characteristics of the device. From the experimental data,
these constants can be solved for: C1 = 4.37 X 10–3 and C2 = 2.01
Therefore
1
MTBF
+
f
SCLK
x f
data
x 4.37 x 10
*3
*
e ( 2.01 x
Dt)
definition of variables
DUT (Device Under Test): The DUT is a 5-ns registered PLD programmed with the equation Q : = D.
MTBF (Mean Time Between Failures): The average time (s) between metastable occurrences that cause a
violation of the device specifications.
fSCLK (system clock frequency): Actual clock frequency for the DUT.
fdata (data frequency): Actual data frequency for a specified input to the DUT.
C1: Calculated constant that defines the magnitude of the curve.
C2: Calculated constant that defines the slope of the curve.
trec (metastability recovery time): Minimum time required to guarantee recovery from metastability, at a given
MTBF failure rate. trec = ∆t – tpd (CLK to Q, max)
∆t: The time difference (ns) from when the synchronizing flip-flop is clocked to when its output is sampled.
The test described above has shown the metastable characteristics of the TIBPAL20R4/R6/R8-5C series. For
additional information on metastable characteristics of Texas Instruments logic circuits, please refer to TI
Applications publication SDAA004, ”Metastable Characteristics, Design Considerations for ALS, AS, and LS
Circuits.’’
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
I OH – High-Level Output Current – mA
15
VCC = 5 V
TA = 25 ° C
10
5
0
–5
–10
–15
VCC = 5 V
TA = 25 ° C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–20
0.4 0.6
–0.8 –0.6 –0.4 –0.2
0
0.2
VOL – Low-Level Output Voltage – V
–100
0
0.8
0.5
1
1.5
2
2.5
VOH – High-Level Output Voltage – V
Figure 12
3
Figure 13
SUPPLY CURRENT
vs
FREE - AIR TEMPERATURE
220
200
I CC – Supply Current – mA
I OL – Low-Level Output Current – mA
20
180
VCC = 5.5 V
VCC = 5.25 V
160
140
VCC = 4.5 V
VCC = 4.75 V
VCC = 5 V
120
100
–75
–50
75
100
–25
0
25
50
TA – Free - Air Temperature – ° C
125
Figure 14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
FREQUENCY
8 - BIT COUNTER MODE
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
6
1100
TA = 25 ° C
CL = 50 pF
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
5
TA = 80 ° C
1000
Propagation Delay Time – ns
P – Power Dissipation – mW
D
VCC = 5 V
TA = 25 ° C
900
TA = 0 ° C
TA = 0 ° C
TA = 80 ° C
800
4
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
3
tPLH (CLK to Q)
2
tPHL (CLK to Q)
1
700
2
1
4
10
20
40
100
0
4.5
200
5.25
4.75
5
VCC – Supply Voltage – V
f – Frequency – MHz
Figure 15
Figure 16
PROPAGATION DELAY TIME
vs
FREE - AIR TEMPERATURE
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
16
6
VCC = 5 V
CL = 50 pF
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
4
3
2
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPLH (CLK to Q)
VCC = 5 V
TA = 25 ° C
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
14
Propagation Delay Time – ns
Propagation Delay Time – ns
5
tPHL (CLK to Q)
12
tPHL (I, I/O to O, I/O)
10
8
tPHL (CLK to Q)
6
4
tPLH (I, I/O to O, I/O)
1
2
0
–75
tPLH (CLK to Q)
0
–50
–25
0
25
50
75 100
TA – Free - Air Temperature – ° C
125
0
Figure 17
26
5.5
100
500
200
300
400
CL – Load Capacitance – pF
Figure 18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
600
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X  PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TYPICAL CHARACTERISTICS
t sk(o)
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
0.8
6
VCC = 5 V
TA = 25 ° C
R1 = 200 Ω
R2 = 200 Ω
CL = 50 pF
8-Bit Counter
0.7
0.6
VCC = 5 V
TA = 25 ° C
CL = 50 pF
R1 = 200 Ω
R2 = 200 Ω
5
Propagation Delay Time – ns
– Skew Between Outputs Switching – ns
SKEW BETWEEN OUTPUTS
vs
NUMBER OF OUTPUTS SWITCHING
0.5
0.4
Outputs Switching in the Opposite Direction
0.3
0.2
4
3
2
= tPHL (I, I/O to O, I/O)
= tPLH (I, I/O to O, I/O)
= tPHL (CLK to Q)
= tPLH (CLK to Q)
1
0.1
Outputs Switching in the Same Direction
0
0
2
3
4
5
6
7
Number of Outputs Switching
8
1
Figure 19
2
6
3
4
5
Number of Outputs Switching
7
8
Figure 20
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27
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D0892
1992 Texas Instruments Incorporated
SRPS010F
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jul-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-87671193A
ACTIVE
LCCC
FK
28
1
TBD
Call TI
Level-NC-NC-NC
5962-8767119KA
ACTIVE
CFP
W
24
1
TBD
Call TI
Level-NC-NC-NC
5962-8767119LA
ACTIVE
CDIP
JT
24
1
TBD
Call TI
Level-NC-NC-NC
TIBPAL20L8-5CFN
ACTIVE
PLCC
FN
28
37
TBD
Call TI
Level-1-220-UNLIM
TIBPAL20L8-5CNT
ACTIVE
PDIP
NT
24
15
TBD
Call TI
Level-NC-NC-NC
TIBPAL20R4-5CFN
OBSOLETE
PLCC
FN
28
TBD
Call TI
Call TI
TIBPAL20R4-5CNT
OBSOLETE
PDIP
NT
24
TBD
Call TI
Call TI
TIBPAL20R6-5CFN
ACTIVE
PLCC
FN
28
37
TBD
Call TI
Level-1-220-UNLIM
15
TIBPAL20R6-5CNT
ACTIVE
PDIP
NT
24
TBD
Call TI
Level-NC-NC-NC
TIBPAL20R8-5CFN
OBSOLETE
PLCC
FN
28
TBD
Call TI
Call TI
TIBPAL20R8-5CNT
OBSOLETE
PDIP
NT
24
TBD
Call TI
Call TI
TIBPAL20R8-7MFKB
ACTIVE
LCCC
FK
28
1
TBD
Call TI
Level-NC-NC-NC
TIBPAL20R8-7MJTB
ACTIVE
CDIP
JT
24
1
TBD
Call TI
Level-NC-NC-NC
TIBPAL20R8-7MWB
ACTIVE
CFP
W
24
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
13
24
B
1
24
28
A MAX
1.280
(32,51)
1.460
(37,08)
A MIN
1.240
(31,50)
1.440
(36,58)
B MAX
0.300
(7,62)
0.291
(7,39)
B MIN
0.245
(6,22)
0.285
(7,24)
DIM
12
0.070 (1,78)
0.030 (0,76)
0.100 (2,54) MAX
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.090 (2,29)
0.045 (1,14)
0.045 (1,14)
0.026 (0,66)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
1
0.360 (9,14)
0.240 (6,10)
24
0.019 (0,48)
0.015 (0,38)
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5 / B 03/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
PINS **
A
24
28
A MAX
1.260
(32,04)
1.425
(36,20)
A MIN
1.230
(31,24)
1.385
(35,18)
B MAX
0.310
(7,87)
0.315
(8,00)
B MIN
0.290
(7,37)
0.295
(7,49)
DIM
24
13
0.280 (7,11)
0.250 (6,35)
1
12
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040050 / B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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