USB3317 Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface 26MHz Reference Clock PRODUCT FEATURES Data Brief USB-IF “Hi-Speed” compliant to the Universal Serial Bus Specification Rev 2.0 Interface compliant with the ULPI Specification revision 1.1 as a Single Data Rate (SDR) PHY 1.8V to 3.3V IO Voltage (+/- 10%) SMSC flexPWRTM Technology — Low current design ideal for battery powered applications — “Sleep” mode tri-states all ULPI pins and places the part in a low current state Supports FS pre-amble for FS hubs with a LS device attached (UTMI+ Level 3) Supports HS SOF and LS keep-alive pulse Includes full support for the optional On-The-Go (OTG) protocol detailed in the On-The-Go Supplement Revision 1.0a specification Supports the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) Allows host to turn VBUS off to conserve battery power in OTG applications Support OTG monitoring of VBUS levels with internal comparators “Wrapper-less” design for optimal timing performance and design ease — Low Latency Hi-Speed Receiver (43 Hi-Speed clocks Max) allows use of legacy UTMI Links with a ULPI bridge Internal 5V cable short-circuit protection of ID, DP and DM lines to VBUS or ground 26MHz Reference Clock operation — 0 to 3.6V input drive tolerant — Able to accept “noisy” clock sources Carkit UART mode for non-USB serial data transfers Industrial Operating Temperature -40°C to +85°C Packaging Options — 24 pin QFN lead-free RoHS compliant package (4 x 4 x 0.90 mm height) — 25 ball VFBGA lead-free RoHS compliant package also available; (3 x 3 x 0.88mm height) Applications The USB3317 is targeted for any application where a HiSpeed USB connection is desired and when board space, power, and interface pins must be minimized. The USB3317 is well suited for: Cell Phones PDAs MP3 Players GPS Personal Navigation Scanners External Hard Drives Digital Still and Video Cameras Portable Media Players Entertainment Devices Printers Set Top Boxes Video Record/Playback Systems IP and Video Phones Gaming Consoles POS Terminals Internal low jitter PLL for 480MHz Hi-Speed USB operation Internal detection of the value of resistance to ground on the ID pin Integrated battery to 3.3V LDO regulator — 2.2uF bypass capacitor — 100mV dropout voltage Integrated ESD protection circuits — Up to +-15kV without any external devices SMSC USB3317 PRODUCT PREVIEW Revision 1.3 (11-02-07) Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock Order Number(s): USB3317-CP-TR FOR 24 PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (TAPE AND REEL) USB3317-GJ-TR FOR 25 PIN, VFBGA LEAD-FREE ROHS COMPLIANT PACKAGE (TAPE AND REEL) REEL SIZE IS 4000 PIECES. 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. 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Revision 1.3 (11-02-07) 2 PRODUCT PREVIEW SMSC USB3317 Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock General Description The USB3317 is a highly integrated Hi-Speed USB 2.0 Transceiver (PHY) that supports systems architectures based on a 26MHz reference clock. It is designed to be used in both commercial and industrial temperature applications. The USB3317 meets all of the electrical requirements to be used as a Hi-Speed USB Host, Device, or an On-the-Go (OTG) device. In addition to the supporting USB signaling the USB3317 also provides USB UART mode USB3317 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB PHY to the Link. The industry standard ULPI interface uses a method of in-band signaling and status byte transfers between the Link and PHY, to facilitate a USB session. By using in-band signaling and status byte transfers the ULPI interface requires only 12 pins. The USB3317 uses SMSC’s “wrapper-less” technology to implement the ULPI interface. This “wrapperless” technology allows the PHY to achieve a low latency transmit and receive time. SMSC’s low latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused. REFCLK VBUS ID DP DM ESD Protection CPEN Low Jitter Integrated PLL OTG Hi-Speed USB Transceiver ULPI Registers and State Machine Carkit BIAS Integrated Power Management RBIAS RESETB VBAT VDD33 VDD18 VDDIO ULPI Interface STP NXT DIR CLKOUT DATA[7:0] Figure 1 USB3317 Block Diagram The USB3317 is designed to run with a 26MHz reference clock. By using a reference clock from the Link the USB3317 is able to remove the cost of a crystal reference from the design. The USB3317 includes a integrated 3.3V LDO regulator to generate its own supply from power applied at the VBAT pin. The voltage on the VBAT pin can range from 3.1 to 5.5V. The regulator dropout voltage is less than 100mV which allows the PHY to continue USB signaling when the voltage on VBAT drops to 3.1V. The USB transceiver will continue to operate at lower voltages, although some parameters may be outside the limits of the USB specifications. If the user would like to provide a 3.3V supply to the USB3317, the VBAT and VDD3.3 pins should be connected together. The USB3317 also includes integrated pull-up resistors that can be used for detecting the attachment of a USB Charger. By sensing the attachment to a USB Charger, a product using the USB3317 can charge its battery at more than the 500mA allowed when charging from a USB Host. SMSC USB3317 3 PRODUCT PREVIEW Revision 1.3 (11-02-07) Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock USB3317 Pin Locations and Descriptions Package Diagram with Pin Locations RBIAS REFCLK RESETB VDD1.8 STP DIR 24 23 22 21 20 19 The pinout below is viewed from the top of the package. ID 1 18 NXT VBUS 2 17 VDDIO VBAT 3 16 DATA0 VDD3.3 4 15 DATA1 DM 5 14 DATA2 DP 6 13 DATA3 11 12 DATA4 CLKOUT 9 DATA6 10 8 DATA7 DATA5 7 CPEN 24Pin QFN 4x4mm Figure 2 USB3317 QFN Pinout - Top View Revision 1.3 (11-02-07) 4 PRODUCT PREVIEW SMSC USB3317 Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock 1 2 3 4 5 A B C D E TOP VIEW Figure 3 USB3317 VFBGA Pinout - Top View Pin Definitions The following table details the pin definitions for the figure above. Table 1 USB3317 Pin Description PIN BALL 1 B1 NAME DIRECTION/ TYPE ACTIVE LEVEL Input, Analog N/A ID pin of the USB cable. For non-OTG applications this pin can be floated. For an A-Device ID is grounded. For a BDevice ID is floated. I/O, Analog N/A VBUS pin of the USB cable. This pin is used for the Vbus comparator inputs and for Vbus pulsing during session request protocol. Power N/A Regulator input. The regulator supply can be from 5.5V to 3.1V. Power N/A 3.3V Regulator Output. A 2.2uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB3317. ID 2 C1 VBUS 3 C2 VBAT DESCRIPTION 4 D2 VDD3.3 5 D1 I/O, Analog N/A D- pin of the USB cable. DM 6 E1 I/O, Analog N/A D+ pin of the USB cable. DP SMSC USB3317 5 PRODUCT PREVIEW Revision 1.3 (11-02-07) Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock Table 1 USB3317 Pin Description (continued) Output, CMOS High External 5 volt supply enable. This pin is used to enable the external Vbus power supply. The CPEN pin is low on POR. This pad uses VDD3.3 logic level. ULPI bi-directional data bus. DATA[7] is the MSB. 7 E2 CPEN 8 E3 I/O, CMOS N/A DATA[7] 9 D3 I/O, CMOS N/A DATA[6] 10 E4 I/O, CMOS N/A DATA[5 11 D4 I/O, CMOS N/A DATA[4] Output, CMOS N/A ULPI bi-directional data bus. ULPI bi-directional data bus. ULPI bi-directional data bus. 60MHz reference clock output. All ULPI signals are driven synchronous to the rising edge of this clock. 12 E5 CLKOUT 13 D5 I/O, CMOS N/A DATA[3] 14 C4 I/O, CMOS N/A DATA[2] 15 C5 I/O, CMOS N/A DATA[1] 16 B4 I/O, CMOS N/A DATA[0] ULPI bi-directional data bus. DATA[0] is the LSB. Power N/A 1.8V to 3.3V ULPI interface supply voltage. This voltage sets the value of VOH for the ULPI interface. Output, CMOS High The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. Output, CMOS N/A Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. Input, CMOS High The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. Power N/A External 1.8V Supply input pin. This pad needs to be bypassed with a 0.1uF capacitor to ground, placed as close as possible to the USB3317. 17 B5 18 A5 19 A4 20 A3 21 B3 Revision 1.3 (11-02-07) ULPI bi-directional data bus. ULPI bi-directional data bus. ULPI bi-directional data bus. VDDIO NXT DIR STP VDD1.8 6 PRODUCT PREVIEW SMSC USB3317 Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock Table 1 USB3317 Pin Description (continued) 22 B2 RESETB 23 A2 REFCLK 24 A1 FLAG C3 SMSC USB3317 RBIAS Input, CMOS, N/A When low, the part is suspended with all of the I/O tri-stated. When high the USB3317 will operate as a normal ULPI device. Input, CMOS N/A 26MHz Reference Clock input. Analog, CMOS N/A Rbias pin. This pin requires an 8.06kΩ (±1%) resistor to ground, placed as close as possible to the USB3317. Ground N/A Ground. QFN only: The flag should be connected to the ground plane with a via array under the exposed flag. This is the main ground for the IC. GND 7 PRODUCT PREVIEW Revision 1.3 (11-02-07) Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock Reference Clock RESETB 8.06KΩ DIR STP 20 VDD1.8 21 RESETB REFCLK 13 NXT VDDIO DATA0 DATA1 Note: VDDIO can be connected to the 1.8V supply for 1.8V IO DATA2 DATA3 CLKOUT 12 6 11 ULPI Interface 19 15 14 DATA4 5 Volt Supply 16 5 CPEN CVBUS 4 7 2.2u F DP 24Pin QFN 4 x 4 mm 3 10 DM 17 DATA5 VDD3.3 USB Connector 2 9 VBAT 18 DATA6 VBUS 1 8 0.1u F ID 22 VDDIO 1.8-3.3V IO Supply 23 RBIAS 24 0.1u F 4.7uF 3.1-5.5V Battery / Supply 12 (msb) DATA7 4.7uF 1.8V Supply 0.1u F Application Diagrams Host/OTG Only CVBUS Min Host 120uF Max Device 1uF 10uF OTG Device 1uF 6.5uF QFN Ground Flag REFCLK and CLKOUT should be isolated with a ground line on both sides. Figure 4 USB3317 QFN Application Diagram Revision 1.3 (11-02-07) 8 PRODUCT PREVIEW SMSC USB3317 Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock ULPI Interface 12 0.1uF 4.7uF 1.8V Supply VDD1.8 B3 A3 A4 A5 0.1uF VBAT 4.7uF 3.1-5.5V Battery / Supply C2 E5 B4 C5 8.06KΩ RBIAS ID VBUS USB Connector DM DP 2.2uF VDD3.3 CVBUS 5 Volt Supply Host/OTG Only B4 A1 3x3mm VFBGA 25 Ball Array 0.5mm Pitch C4 D5 D4 E4 B1 D3 C1 E3 D1 E2 E1 B2 D2 C3 VDDIO 0.1uF 1.8-3.3V IO Supply A2 STP DIR NXT CLKOUT DATA0 DATA1 Note: VDDIO can be connected to the 1.8V supply for 1.8V IO DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 (msb) CPEN RESETB from Link REFCLK CPEN REFCLK and CLKOUT should be isolated with a ground line on both sides. CVBUS Min Host 120uF Max Device 1uF 10uF OTG Device 1uF 6.5uF Figure 5 USB3317 VFBGA Application Diagram SMSC USB3317 9 PRODUCT PREVIEW Revision 1.3 (11-02-07) Figure 6 24-pin QFN, 4x4mm Body, 0.5mm Pitch SMSC USB3317 PRODUCT PREVIEW 10 Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock Revision 1.3 (11-02-07) Package Outlines PRODUCT PREVIEW 11 Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock Revision 1.3 (11-02-07) SMSC USB3317 Figure 7 25-pin VFBGA, 3x3mm Body, 0.5mm Pitch