Ordering number : ENA0788A LC72131K LC72131KMA CMOS IC PLL Frequency Synthesizer Overview The LC72131K and LC72131KMA are PLL frequency synthesizers for use in tuners in radio/cassette players. They allow high-performance AM/FM tuners to be implemented easily. Features • High speed programmable dividers • FMIN: 10 to 160MHz …………………….. pulse swallower (built-in divide-by-two prescaler) • AMIN: 2 to 40MHz ………………………. pulse swallower 0.5 to 10MHz …………………….. direct division • IF counter • IFIN: 0.4 to 12MHz ………………………. AM/FM IF counter • Reference frequencies • Twelve selectable frequencies (4.5 or 7.2MHz crystal) • 100, 50, 25, 15, 12.5, 6.25, 3.125, 10, 9, 5, 3, 1kHz • Phase comparator • Dead zone control • Unlock detection circuit • Deadlock clear circuit • Built-in MOS transistor for forming an active low-pass filter • I/O ports • Dedicated output ports: 4 • Input or output ports: 2 • Support clock time base output • Serial data I/O • Support CCB format communication with the system controller. Continued on next page. • CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format. • CCB is a registered trademark of Semiconductor Components Industries, LLC. Semiconductor Components Industries, LLC, 2013 June, 2013 O3112HK 20120919-S00009/51407HKIM 20070328-S00008,S00009 No.A0788-1/22 LC72131K, LC72131KMA Continued from preceding page. • Operating ranges • Supply voltage ........................4.5 to 5.5V • Packages • DIP22S(300mil) / MFP20J(300mil) • Operating temperature ............ -40 to +85°C Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Symbol Pins Conditions Ratings Unit Supply voltage VDD max VDD -0.3 to +7.0 Maximum input voltage VIN1 max CE, CL, DI, AIN -0.3 to +7.0 V VIN2 max XIN, FMIN, AMIN, IFIN -0.3 to VDD+0.3 V VIN3 max IO1, IO2 -0.3 to +15 V VO1 max DO -0.3 to +7.0 V VO2 max XOUT, PD -0.3 to VDD+0.3 V -0.3 to +15 V Maximum output voltage Maximum output current Allowable power dissipation V VO3 max BO1 to BO4, IO1, IO2, AOUT IO1 max BO1 0 to 3.0 IO2 max DO, AOUT 0 to 6.0 mA IO3 max BO2 to BO4, IO1, IO2 0 to 10 mA Pd max mA Ta≤85°C [LC72131K] 350 mW Ta≤85°C [LC72131KMA] 180 mW Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C Note 1: Power pins VDD and VSS: Insert a capacitor with a capacitance of 2,000pF or higher between these pins when using the IC. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. No.A0788-2/22 LC72131K, LC72131KMA Allowable Operating Ranges at Ta = -40°C to +85°C, VSS = 0V Parameter Symbol Pins Conditions Ratings min typ max unit Supply voltage VDD VDD 4.5 5.5 Input high-level voltage VIH1 CE, CL, DI 0.7VDD 6.5 V VIH2 IO1, IO2 0.7VDD 13 V V Input low-level voltage VIL CE, CL, DI, IO1, IO2 0 0.3VDD V Output voltage VO1 DO 0 6.5 V VO2 BO1 to BO4, IO1, IO2, AOUT 0 13 V fIN1 XIN VIN1 1.0 8.0 MHz fIN2 FMIN VIN2 10 160 MHz fIN3 AMIN VIN3 2.0 40 MHz fIN4 AMIN VIN4 0.5 10 MHz fIN5 IFIN VIN5 0.4 12 MHz Supported crystals X'tal XIN, XOUT Note 1 4.0 8.0 Input amplitude VIN1 XIN fIN1 400 1500 mVrms VIN2-1 FMIN f=10 to 130MHz 40 1500 mVrms VIN2-2 FMIN f=130 to 160MHz 70 1500 mVrms VIN3 AMIN fIN3 40 1500 mVrms VIN4 AMIN fIN4 40 1500 mVrms VIN5 IFIN fIN5 (IFS=1) 40 1500 mVrms VIN6 IFIN fIN5 (IFS=0) 70 1500 mVrms Data setup time tSU DI, CL Note 2 0.75 μs Data hold time tHD DI, CL Note 2 0.75 μs Clock low-level time tCL CL Note 2 0.75 μs Clock high-level time tCH CL Note 2 0.75 μs CE wait time tEL CE, CL Note 2 0.75 μs CE setup time tES CE, CL Note 2 0.75 μs CE hold time tEH CE, CL Note 2 0.75 Data latch change time tLC Data output time tDC DO, CL Differs depending tDH DO, CE on the value of the Input frequency High-level clock pulse width tφH CL [Figure 1][Figure 2] 160 ns Low-level clock pulse width Note 2 pull-up resistor. MHz μs 0.75 μs 0.35 μs Note 2 Note 1: Recommended crystal oscillator CI values: CI≤120Ω (For a 4.5MHz crystal) CI≤70Ω (For a 7.2MHz crystal) The characteristics of the oscillation circuit depends on the printed circuit board, circuit constants, and other factors. Therefore we recommend consulting with the anufacturer of the crystal for evaluation and reliability. Note 2: Refer to "Serial Data Timing". No.A0788-3/22 LC72131K, LC72131KMA Electrical Characteristics in the Allowable Operating Ranges Parameter Built-in feedback resistance Symbol Pins Conditions Ratings min typ max unit Rf1 XIN 1.0 MΩ Rf2 FMIN 500 kΩ Rf3 AMIN 500 kΩ Rf4 IFIN 250 kΩ Rpd1 FMIN 200 kΩ Rpd2 AMIN 200 kΩ Hysteresis VHYS CE, CL, DI, IO1, IO2 Output high-level voltage VOH PD IO=1mA Output low-level voltage VOL1 PD IO=1mA 1.0 V VOL2 BO1 V Built-in pull-down resistor VOL3 VOL4 VOL5 Input high-level current Input low-level current DO BO2 to BO4, IO1, IO2 0.1VDD V VDD-0.1 V IO=0.5mA 0.5 IO=1mA 1.0 V IO=1mA 0.2 V IO=5mA 1.0 V IO=1mA 0.2 V IO=5mA 1.0 V IO=8mA 1.6 V AOUT IO=1mA AIN=1.3V 0.5 V 5.0 μA IIH1 CE, CL, DI VI=6.5V IIH2 IO1, IO2 VI=13V 5.0 μA IIH3 XIN VI=VDD 2.0 11 μA IIH4 FMIN, AMIN VI=VDD 4.0 22 μA IIH5 IFIN VI=VDD 8.0 44 μA IIH6 AIN VI=6.5V 200 nA IIL1 CE, CL, DI VI=0V 5.0 μA IIL2 IO1, IO2 VI=0V 5.0 μA IIL3 XIN VI=0V 2.0 11 μA IIL4 FMIN, AMIN VI=0V 4.0 22 μA IIL5 IFIN VI=0V 8.0 44 μA IIL6 AIN VI=0V 200 nA Output off leakage current IOFF1 BO1 to BO4, AOUT, IO1, IO2 VO=13V 5.0 μA IOFF2 DO VO=6.5V 5.0 μA High-level three-state off leakage IOFFH PD VO=VDD 0.01 200 nA IOFFL PD VO=0V 0.01 200 nA current Low-level three-state off leakage current Input capacitance CIN FMIN Current drain IDD1 VDD 6 fIN2=130MHz IDD2 VDD pF X'tal=7.2MHz 5 10 mA VIN2=40mVrms PLL block stopped (PLL INHIBIT) X'tal oscillator 0.5 mA operating (X'tal=7.2MHz) IDD3 VDD PLL block stopped X'tal oscillator 10 μA operating No.A0788-4/22 LC72131K, LC72131KMA ≈ Serial Data Timing VIH tCL VIH VIL CL VIH VIL tHD tEL ≈ ≈ ≈ ≈ ≈ ≈ VIH tSU VIH VIL DI VIL VIL DO Internal data latch VIH VIL ≈ ≈ ≈ ≈ ≈ ≈ ≈ tCH ≈ ≈ CE tES tDC tDC tEH tDH tLC Old New ≈ When stopped with CL low VIH VIH VIL VIH VIH VIH DI VIL tSU tHD DO Internal data latch VIH VIL ≈ ≈ ≈ ≈ ≈ ≈ ≈ CL VIL ≈ tCL tEL VIL tES tEH ≈ ≈ ≈ ≈ ≈ ≈ tCH ≈ CE tDC tDH tLC Old New When stopped with CL high Package Dimensions Package Dimensions unit : mm (typ) 3059A [LC72131K] unit : mm (typ) 3445 [LC72131KMA] 12.7 21.0 20 22 7.8 1 2 1.27 0.4 0.15 (0.8) 1.78 0.48 SANYO : DIP22S(300mil) 0.05 1.8 (3.25) (0.635) 0.51min 3.3 3.9 max 0.5 11 0.95 0.25 1 5.4 6.4 7.62 12 SANYO : MFP20J(300mil) No.A0788-5/22 LC72131K, LC72131KMA XOUT VSS AOUT AIN PD VDD FMIN AMIN NC IO2 IFIN Pin Assignments 22 21 20 19 18 17 16 15 14 13 12 2 3 4 5 6 7 8 9 10 NC CE DI CL DO BO1 BO2 BO3 BO4 11 IO1 1 XIN LC72131K XOUT VSS AOUT AIN PD VDD FMIN AMIN IO2 IFIN Top view 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 XIN CE DI CL DO BO1 BO2 BO3 BO4 IO1 LC72131KMA Top view Block Diagram REFERENCE DIVIDER XIN PHASE DETECTOR CHARGE PUMP PD XOUT FMIN 1/2 SWALLOW COUNTER 1/16,1/17 4bits UNLOCK DETECTOR AIN AOUT 12bits PROGRAMMABLE DIVIDER AMIN CE DI CL CCB I/F DATA SHIFT REGISTER LATCH UNIVERSAL COUNTER IFIN DO VDD VSS POWER ON RESET BO1 BO2 BO3 BO4 IO1 IO2 No.A0788-6/22 LC72131K, LC72131KMA Pin Functions Symbol Pin No. LC72131K LC72131KMA XIN 1 1 XOUT 22 20 FMIN 16 14 Type X'tal OSC Functions Circuit configuration Crystal resonator connection (4.5MHz/7.2MHz) Local FMIN is selected when the serial data input DVS bit is set to 1. oscillator The input frequency range is from 10 to 160MHz. signal input The input signal passes through the internal divide-by-two prescaler and is input to the swallow counter. The divisor can be in the range 272 to 65535. However, since the signal has passed through the divide-by-two prescaler, the actual divisor is twice the set value. AMIN 15 13 Local AMIN is selected when the serial data input DVS bit is set to 0. oscillator When the serial data input SNS bit is set to 1: signal input • The input frequency range is 2 to 40MHz. • The signal is directly input to the swallow counter. • The divisor can be in the range 272 to 65535, and the divisor used will be the value set. When the serial data input SNS bit is set to 0: • The input frequency range is 0.5 to 10MHz. • The signal is directly input to a 12-bit programmable divider. • The divisor can be in the range 4 to 4095, and the divisor used will be the value set. CE 3 2 Chip enable Set this pin high when inputting (DI) or outputting (DO) serial S data. DI 4 3 Input data Inputs serial data transferred from the controller to the S LC72131K/KMA. CL 5 4 Clock DO 6 5 Output data S Used as the synchronization clock when inputting (DI) or outputting (DO) serial data. Outputs serial data transferred from the LC72131K/KMA to the controller. The content of the output data is determined by the serial data DOC0 to DOC2. VDD 17 15 Power supply The LC72131K/KMA power supply pin (VDD=4.5 to 5.5V) The power on reset circuit operates when power is first applied. VSS 21 19 Ground The LC72131K/KMA ground BO1 7 6 Output port Dedicated output pins BO2 8 7 The output states are determined by BO1 to BO4 bits in BO3 9 8 the serial data. BO4 10 9 - Data: 0=open, 1=low A time base signal (8Hz) can be output from the BO1 pin. (When the serial data TBC bit is set to 1.) Care is required when using the BO1 pin, since it has a higher on impedance that the other output ports (pins BO2 to BO4). IO1 11 10 IO2 13 12 I/O port I/O dual-use pins The direction (input or output) is determined by bits IOC1 and IOC2 in the serial data. Data: 0=input port, 1=output port When specified for use as input ports: S The state of the input pin is transmitted to the controller over the DO pin. Input state: low=0 data value high=1 data value When specified for use as output ports: The output states are determined by the IO1 and IO2 bits in the serial data. Data: 0=open, 1=low These pins function as input pins following a power on reset. Continued on next page. No.A0788-7/22 LC72131K, LC72131KMA Continued from preceding page. Pin No. Symbol PD LC72131K LC72131KMA 18 16 Type Functions Charge pump Circuit configuration PLL charge pump output output When the frequency generated by dividing the local oscillator frequency by N is higher than the reference frequency, a high level is output from the PD pin. Similarly, when that frequency is lower, a low level is output. The PD pin goes to the high impedance state when the frequencies match. AIN 19 17 LPF amplifier The n-channel MOS transistor used for the PLL active AOUT 20 18 transistors low-pass filter. IFIN 12 11 IF counter Accepts an input in the frequency range 0.4 to 12MHz. The input signal is directly transmitted to the IF counter. The result is output starting the MSB of the IF counter using the DO pin. Four measurement periods are supported: 4, 8, 32, and 64ms. DI Control Data (Serial Data Input) Structure [1] IN1 mode address DI 0 0 0 1 0 1 0 0 R3 R2 (2) R-CTR R1 R0 XS (3) IF-CTR CTE DVS SNS P15 P14 P13 P12 P11 P10 P9 P7 BO4 P8 P6 0 (1) P-CTR P5 0 BO3 P4 1 BO2 P3 P2 P1 P0 First Data IN1 [2] IN2 mode address 1 0 0 1 0 TEST2 TEST1 IFS (11) IFS (12) TEST DLC (10) PD-C TEST0 TBC GT1 (9) TIME (3) IF-CTR GT0 DZ1 UL1 DZ0 (8) DZ-C (7) UNLOCK UL0 DOC2 DOC1 (6) DO-C DOC0 DNC (13) Don’t care (5) O-PORT BO1 IO2 IO1 IOC2 IOC1 First Data IN2 (4) IO-C DI No.A0788-8/22 LC72131K, LC72131KMA Control Data Functions No. (1) Control block/data Functions Related data Programmable Data that sets the divisor of the programmable divider. divider data A binary value in which P15 is the MSB. The LSB changes depending on P0 to P15 DVS and SNS. (*: don’t care) DVS SNS LSB Divisor setting (N) Actual divisor 1 0 0 * 1 0 P0 P0 P4 272 to 65535 272 to 65535 4 to 4095 Twice the value of the setting The value of the setting The value of the setting Note: P0 to P3 are ignored when P4 is the LSB. DVS, SNS Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches the input frequency range. (*: don’t care) DVS SNS Input pin 1 0 0 * 1 0 FMIN AMIN AMIN Input frequency range 10 to 160MHz 2 to 40MHz 0.5 to 10MHz Note: See the “Programmable Divider Structure” item for more information. (2) Reference divider data R0 to R3 Reference frequency (fref) selection data. R3 R2 R1 R0 Reference frequency 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 100kHz 50 25 25 12.5 6.25 3.125 3.125 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 10 9 5 1 1 1 1 1 0 0 0 1 3 15 1 1 1 0 1 1 1 1 * PLL INHIBIT + X'tal OSC STOP * PLL INHIBIT Note *: PLL INHIBIT The programmable divider block and the IF counter block are stopped, the FMIN, AMIN, and IFIN pins are set to the pull-down state (ground), and the charge pump goes to the high impedance state. XS Crystal resonator selection XS=0: 4.5MHz XS=1: 7.2MHz The 7.2MHz frequency is selected after the power-on reset. (3) IF counter control IF counter measurement start data data CTE=1: Counter start CTE GT0, GT1 IFS =0: Counter reset Determines the IF counter measurement period. GT1 GT0 0 0 1 1 0 1 0 1 Measurement time (ms) 4 8 32 64 Wait time (ms) 3 to 4 3 to 4 7 to 8 7 to 8 Note: See the “IF Counter Structure” item for more information. Continued on next page. No.A0788-9/22 LC72131K, LC72131KMA Continued from preceding page. No. Control block/data (4) I/O port specification data Functions Related data Specifies the I/O direction for the bidirectional pins IO1 and IO2. Data: 0=input mode, 1=output mode IOC1, IOC2 (5) Output port data BO1 to BO4 (6) Data that determines the output from the BO1 to BO4, IO1 and IO2 output ports IOC2 IO1, IO2 The data=0 (open) state is selected after the power-on reset. DO pin control data Data that determines the DO pin output DOC0 DOC1 DOC2 IOC1 Data: 0=open, 1=low UL0, UL1 DOC2 DOC1 DOC0 Do pin state CTE 0 0 0 0 0 0 1 1 0 1 0 1 Open Low when the unlock state is detected end-UC *1 Open IOC1 1 1 1 1 0 0 1 1 0 1 0 1 Open The IO1 pin state *2 The IO2 pin state *2 IOC2 Open The open state is selected after the power-on reset. ≈ Note: 1. end-UC: Check for IF counter measurement completion ≈ DO pin (1) Count start (2) Count end (3)CE: High (1) When end-UC is set and the IF counter is started (i.e., when CTE is changed from zero to one), the DO pin automatically goes to the open state. (2) When the IF counter measurement completes, the DO pin goes low to indicate the measurement completion state. (3) Depending on serial data I/O (CE: high) the DO pin goes to the open state. Note: 2. Goes to the open state if the I/O pin is specified to be an output port. Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE high) will be open, regardless of the state of the DO control data (DOC0 to DOC2). Also, the DO pin during a data output period (an OUT mode period with CE high) will output the contents of the internal DO serial data in synchronization with the CL pin signal, regardless of the state of the DO control data (DOC0 to DOC2). (7) Unlock detection Selects the phase error (φE) detection width for checking PLL lock. DOC0 data A phase error in excess of the specified detection width is seen as an unlocked state. DOC1 UL0, UL1 UL1 UL0 0 0 1 1 0 1 0 1 φE detection width stopped 0 ±0.55μs ±1.11 DOC2 Detector output Open φE is output directry φE is extended by 1 to 2ms ↑ Note: In the unlocked state the DO pin goes low and the UL bit in the serial data becomes zero. Continued on next page. No.A0788-10/22 LC72131K, LC72131KMA Continued from preceding page. No. Control block/data (8) Functions Phase comparator Related data • Controls the phase comparator dead zone. control data DZ0, DZ1 DZ1 DZ0 Dead zone mode 0 0 1 1 0 1 0 1 DZA DZB DZC DZD Dead zone width: DZA<DZB<DZC<DZD (9) (10) Clock time base Setting TBC to one causes an 8Hz, 40% duty clock time base signal to be output from the BO1 TBC pin. (BO1 data is invalid in this mode.) Charge pump control Forcibly controls the charge pump output. data DLC DLC Charge pump output 0 1 Normal operation Forced low BO1 Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO oscillator stopping, deadlock can be cleared by forcing the charge pump output to low and (11) setting Vtune to VCC. (This is the deadlock clearing circuit.) This data must be set 1 in normal mode. IF counter control data IFS Though if this value is set to zero, the system enters input sensitivity degradation mode, IFS and the sensitivity is reduced to 10 to 30mVrms. * See the “IF Counter Operation” item for details. (12) LSI test data LSI test data TEST0 to 2 TEST0 TEST1 These values must all be set to 0. TEST2 These test data are set to 0 automatically after the power-on reset. (13) DNC Don’t care. This data must be set to 0. DO Control Data (Serial Data Output) Structure [3] OUT Mode 0 1 0 1 0 1 0 0 C16 DI C17 address C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C11 C12 C13 C14 C15 C18 C19 I1 C10 (3) IF-CTR (2) UNLOCK (1) IN-PORT I2 DO UL Fist Data OUT : Must be 0. No.A0788-11/22 LC72131K, LC72131KMA Control Data Functions No. Control block/data (1) Functions Latched from the pin states of the IO1 and IO2 I/O ports. IOC1 I2, I1 These values follow the pin states regardless of the input or output setting. High: 1 I1 ← IO1 pin state IOC2 PLL unlock data Latched from the state of the unlock detection circuit. I2 ← IO2 pin state (2) Related data I/O port data Low: 0 UL0 UL ← 0: Unlocked UL UL1 UL ← 1: Locked or detection stopped mode (3) IF counter binary Latched from the value of the IF counter (20-bit binary counter). CTE counter C19 ← MSB of the binary counter GT0 C19 to C0 C0 ← LSB of the binary counter GT1 Serial Data I/O Methods The LC72131K/KMA inputs and outputs data using Our CCB (computer control bus) audio LSI serial bus format. This LSI adopts an 8-bit address format CCB. I/O mode Address B0 B1 B2 B3 A0 A1 A2 Function A3 • Control data input mode (serial data input) [1] IN1 (82) 0 0 0 1 0 1 0 0 • 24 data bits are input. • See the “DI Control Data (serial data input) Structure” item for details on the meaning of the input data. • Control data input mode (serial data input) [2] IN2 (92) 1 0 0 1 0 1 0 0 • 24 data bits are input. • See the “DI Control Data (serial data input) Structure” item for details on the meaning of the input data. • Data output mode (serial data output) [3] OUT (A2) 0 1 0 1 0 1 0 0 • The number of bits output is equal to the number of clock cycles. • See the “DO Control Data (serial data output) Structure” item for details on the meaning of the output data. ≈ I/O mode determined ≈ CE (1) CL DI B0 B1 B2 B3 A0 A1 A2 A3 First Data IN1/2 (1) First Data OUT DO (2) (1) CL: Normal high (2) CL: Normal low First Data OUT ≈ ≈ ≈ ≈ ≈ ≈ ≈ (2) No.A0788-12/22 LC72131K, LC72131KMA 1. Serial Data Input (IN1/IN2) tSU, tHD, tES, tEH≥0.75μs tLC<0.75μs (1) CL: Normal high tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data (2) CL: Normal low tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data 2. Serial Data Output (OUT) tSU, tHD, tEL, tES, tEH≥0.75μs tDC, tDH<0.35μs (1) CL: Normal high tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC DO tDC I2 I1 tDH UL C3 C2 C1 C0 (2) CL: Normal low tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC DO tDC I2 I1 tDH UL C3 C2 C1 C0 Note: Since the DO pin is an N-channel open-drain pin, the time for the data to change (tDC and tDH) will differ depending on the value of the pull-up resistor and printed circuit board capacitance. No.A0788-13/22 LC72131K, LC72131KMA Programmable Divider Structure 4bits 1/2 FMIN 12bits (A) Swallow Counter Programmable Divider (C) (B) AMIN fvco/N φE PD fref DVS fvco=fref×N SNS DVS SNS Input pin Set divisor Actual divisor: N Input frequency range (A) 1 * FMIN 272 to 65535 Twice the set value 10 to 160MHz (B) 1 1 AMIN 272 to 65535 The set value 2 to 40MHz (C) 0 0 AMIN 4 to 4095 The set value 0.5 to 10MHz *: Don't care Programmable Divider Calculation Examples (1) FM, 50kHz steps (DVS=1, SNS=*: FMIN selected) FM RF=90.0MHz (IF=+10.7MHz) FM VCO=100.7MHz PLL fref=25kHz (R0 to R1=1, R2 to R3=0) 100.7MHz (FMVCO)÷25kHz (fref) ÷2 (FMIN: divide-by-two prescaler) =2014→07DE (HEX) 0 0 R3 1 0 R2 0 1 R1 0 1 R0 1 XS * CTE 0 DVS P13 0 SNS 0 P15 0 P14 0 P14 1 P12 1 P11 1 0 P10 1 P9 P5 1 P8 0 P7 1 7 P6 1 P4 P1 1 P3 1 D P2 0 P0 E 0 1 0 1 (2) SW 5kHz steps (DVS=0, SNS=1: AMIN high-speed side selected) SW RF=21.75MHz (IF=+450kHz) SW VCO=22.20MHz PLL fref=5kHz (R0=R2=0, R1=R3=1) 22.2MHz (SW VCO) ÷5kHz (fref) =4440→1158 (HEX) 0 0 0 0 0 P15 SNS DVS R3 0 0 0 0 1 R3 1 R2 0 R2 0 R1 1 R1 0 R0 0 R0 DVS 0 XS SNS 1 CTE P15 * P14 P13 * P13 P12 * P12 P11 * P11 0 P10 1 P10 P9 0 P9 P8 0 P8 P7 P5 0 P7 P4 1 P6 P3 0 P6 P2 1 P5 0 P4 1 P3 1 P2 0 1 P1 0 1 P0 0 P1 5 P0 8 (3) MW 10kHz steps (DVS=0, SNS=0: AMIN low-speed side selected) MW RF=1000kHz (IF=+450kHz) MW VCO=1450kHz PLL fref=10kHz (R0 to R2=0, R3=1) 1450kHz (MW VCO) ÷10kHz (fref)=145→091 (HEX) 0 XS 9 CTE 1 No.A0788-14/22 LC72131K, LC72131KMA IF Counter Structure The LC72131K/KMA IF counter is a 20-bit binary counter. The result, i.e., the counter’s msb, can be read serially from the DO pin. IF counter (20bits binary counter) (Fc) L S B 0 to 3 IFIN (GT) 4/8/32/64ms M S B 4 to 7 8 to 11 12 to 15 16 to 19 DO pin (C) CTE GT1 GT0 C=Fc×GT Measurement time GT1 GT0 Measurement time (GT) (ms) Wait time (twu) (ms) 0 0 4 3 to 4 0 1 8 3 to 4 1 0 32 7 to 8 1 1 64 7 to 8 The IF frequency (Fc) is measured by determining how many pulses were input to an IF counter in a specified measurement period, GT. Fc= C (C=Fc×GT) GT C: Count value (number of pulses) IF Counter Frequency Calculation Examples (1) When the measurement period (GT) is 32ms, the count (C) is 53980 hexadecimal (342400 decimal): IF frequency (Fc) =342400÷32ms=10.7MHz 0 0 0 0 C0 0 C1 C6 0 C2 0 C3 1 C4 1 0 C5 0 C7 0 C8 1 8 C9 1 C10 C14 1 C11 0 C12 0 9 C13 1 C15 C18 0 C16 1 3 C17 0 C19 UL I1 I2 5 (2) When the measurement period (GT) is 8ms, the count (C) is E10 hexadecimal (3600 decimal): IF frequency (Fc) =3600÷8ms=450kHz 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 0 C16 1 C17 E C18 0 C19 UL I1 I2 0 No.A0788-15/22 LC72131K, LC72131KMA IF Counter Operation CE CTE data=1 Measurement time GT Frequncy Measurement time Wait time IFIN Count start Count end (end-UC) Before starting the IF count, the IF counter must be reset in advance by setting CTE in the serial data to 0. The IF count is started by changing the CTE bit in the serial data from 0 to 1. The serial data is latched by the LC72131K/KMA when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the period between the point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF counter at the end of the measurement period must be read out during the period that CTE is 1. This is because the IF counter is reset when CTE is set to 0. Note: When operating the IF counter, the control microprocessor must first check the state of the IF-IC SD (station detect) signal and only after determining that the SD signal is present turn on IF buffer output and execute an IF count operation. Autosearch techniques that use only the IF counter are not recommended, since it is possible for IF buffer leakage output to cause incorrect stops at points where there is no station. IFIN minimum input sensitivity standard IFS f [MHz] 0.4≤f<0.5 0.5≤f<8 8≤f≤12 1: Normal mode 40mVrms (0.1 to 3mVrms) 40mVrms 40mVrms (1 to 10mVrms) 0: Degradation mode 70mVrms (10 to 15mVrms) 70mVrms 70mVrms (30 to 40mVrms) Note: Values in parentheses are actual performance values presented as reference data. Unlock Detection Timing Unlock Detection Determination Timing Unlocked state detection is performed in the reference frequency (fref) period (interval). Therefore, in principle, unlock determination requires a time longer than the period of the reference frequency. However, immediately after changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the reference frequency. CE DATA LATCH Old data New data VCO/N Ncounter Old divisor N New divisor N’ fref φERROR (unlock) The divisor N is not updated during the first period. Note: After changing the divisor, φERROR is output after two fref periods. Figure 1 Unlocked State Detection Timing For example, if fref is 1kHz, i.e., the period is 1ms, after changing the divisor N, the system must wait at least 2ms before checking for the unlocked state. No.A0788-16/22 LC72131K, LC72131KMA ÷R VCO ÷N fref VCO/N UNLOCK detection circuit UNLOCK Phase comparator φERROR L.P.F Preset DATA LATCH Figure 2 Circuit Structure Data input Data output (1) Data output (2) CE N Old data New data VCO frequency φERROR Unlock (UL) serial data output Unlock detection pin output Locked Unlocked Locked Figure 3 Unlocked State Data Output Using Serial Data Output In the LC72131K/KMA, once an unlocked state occurs, the unlocked state serial data (UL) will not be reset until a data input (or output) operation is performed. At the data output (1) point in Figure 3, although the VCO frequency has stabilized (locked), since no data output has been performed since the divisor N was changed the unlocked state data remains in the unlocked state. As a result, even though the frequency has stabilized (locked), the system remains (from the standpoint of the data) in the unlocked state. Therefore, the unlocked state data acquired at data output (1), which occurs immediately after the divisor N was changed, should be treated as a dummy data output and ignored. The second data output (data output (2)) and following outputs are valid data. <Locked State Determination Flowchart Example> Divisor N modification (data input) Wait for at least two reference frequency periods. Dummy data output Valid data can be output at intervals of one reference frequency period or longer. Valid data output locked * YES NO *: Locking state determination is more reliable if it is based on reading valid output data several times No.A0788-17/22 LC72131K, LC72131KMA Directly Outputting Unlocked State Data from the DO Pin (Set by the DO pin control data) Since the unlocked state (high=locked, low=unlocked) is output directly from the DO pin, the dummy data processing described in section 3 above is not required. After changing the divisor N, the locking state can be checked after waiting at least two reference frequency periods. Clock Time Base Usage Notes The pull-up resistor used on the clock time base output pin (BO1) should be at least 100kΩ. This is to prevent degrading the VCO C/N characteristics when a loop filter is formed using the built-in low-pass filter transistor. Since the clock time base output pin and the low-pass filter have a common ground internal to the IC, it is necessary to minimize the time base output pin current fluctuations and to suppress their influence on the low-pass filter. Also, to prevent chattering we recommend using a Schmitt input at the controller (microprocessor) that receives this signal. VDD LC72131K/KMA Rt≥100kΩ BO1 Microprocessor S Time base output Schmitt input PD VCC AOUT VCO Vt AIN Loop filter Other Items [1] Notes on the Phase Comparator Dead Zone DZ1 DZ0 Dead zone mode Charge pump Dead zone 0 0 DZA ON/ON - -0s 0 1 DZB ON/ON -0s 1 0 DZC OFF/OFF +0s 1 1 DZD OFF/OFF ++0s Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the ON/ON state, the loop can easily become unstable. This point requires special care when designing application circuits. The following problems may occur in the ON/ON state. (1) Side band generation due to reference frequency leakage (2) Side band generation due to both the correction pulse envelope and low frequency leakage Schemes in which a dead zone is present (OFF/OFF) have good loop stability, but have the problem that acquiring a high C/N ratio can be difficult. On the other hand, although it is easy to acquire a high C/N ratio with schemes in which there is no dead zone, it is difficult to achieve high loop stability. Therefore, it can be effective to select DZA or DZB, which have no dead zone, in applications which require an FM S/N ratio in excess of 90 to 100dB, or in which an increased AM stereo pilot margin is desired. On the other hand, we recommend selecting DZC or DZD, which provide a dead zone, for applications which do not require such a high FM signal-to-noise ratio and in which either AM stereo is not used or an adequate AM stereo pilot margin can be achieved. No.A0788-18/22 LC72131K, LC72131KMA Dead Zone The phase comparator compares fp to a reference frequency (fr) as shown in Figure 1. Although the characteristics of this circuit (see Figure 2) are such that the output voltage is proportional to the phase difference ø (line A), a region (the dead zone) in which it is not possible to compare small phase differences occurs in actual ICs due to internal circuit delays and other factors (line B). A dead zone as small as possible is desirable for products that must provide a high S/N ratio. However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularlypriced products. This is because it is possible for RF signals to leak from the mixer to the VCO and modulate the VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is narrow, the circuit outputs correction pulses and this output can further modulate the VCO and generate beat frequencies with the RF signal. V RF (A) MIX Reference Divider Programmable Divider fr Signal leak Phase fp (B) LPF VCO φ(ns) Detector Dead Zone Figure 2 Figure 1 [2] Notes on the FMIN, AMIN, and IFIN Pins Coupling capacitors must be placed as close as possible to their respective pin. A capacitance of about 100pF is desirable. In particular, if a capacitance of 1000pF or over is used for the IF pin, the time to reach the bias level will increase and incorrect counting may occur due to the relationship with the wait time. [3] Notes on IF Counting→SD must be used in conjunction with the IF counting time When using IF counting, always implement IF counting by having the microprocessor determine the presence of the IF-IC SD (station detect) signal and turn on the IF counter buffer only if the SD signal is present. Schemes in which auto-searches are performed with only IF counting are not recommended, since they can cause false detection where there is no signal due to overflow from the IF counter buffer. [4] DO Pin Usage Techniques In addition to data output mode times, the DO pin can also be used to check for IF counter count completion and for unlock detection output. Also, an input pin state can be output unchanged through the DO pin and input to the controller. Pin States After the Power ON Reset [LC72131K] XIN XOUT NC VSS CE AOUT DI AIN CL PD Open DO Open BO1 FMIN Open BO2 AMIN Open BO3 NC Open BO4 IO2 Input port IO1 IFIN LC72131K VDD Input port No.A0788-19/22 LC72131K, LC72131KMA Pin States After the Power ON Reset [LC72131KMA] XIN XOUT CE VSS DI AOUT CL AIN PD Open DO Open BO1 Open BO2 FMIN Open BO3 AMIN Open BO4 IO2 Input port IO1 IFIN LC72131KMA VDD Input port Application System Example [LC72131K] μ-COM 22 XOUT NC 2 21 VSS CE CE 3 S 20 AOUT DI DI 4 S 19 AIN CL CL 5 S 18 PD DO DO 6 LC72131K Unlock tune end-UC IFcount ST-indic XIN 1 BO1 7 AMVCO 16 FMIN 15 AMIN BO3 9 14 NC S 13 IO2 IO1 11 S FMVCO 17 VDD BO2 8 BO4 10 VCC 12 IFIN tune AM/FM-IF TUNER-System IF-Request FM/AM MONO/ST ST-Indicate No.A0788-20/22 LC72131K, LC72131KMA Application System Example [LC72131KMA] XIN 1 μ-COM CE CE 2 S 19 VSS DI DI 3 S 18 AOUT CL CL 4 S 17 AIN DO DO 5 LC72131KMA Unlock tune end-UC IFcount ST-indic 20 XOUT BO1 6 15 VDD AMVCO 14 FMIN BO3 8 13 AMIN S IO1 10 12 IO2 S FMVCO 16 PD BO2 7 BO4 9 VCC 11 IFIN tune AM/FM-IF TUNER-System IF-Request FM/AM MONO/ST ST-Indicate No.A0788-21/22 LC72131K, LC72131KMA ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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