TI SN74AUP1G02DCKR

SN74AUP1G02
LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE
www.ti.com
SCES568D – JUNE 2004 – REVISED MAY 2007
FEATURES
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Low Static-Power Consumption
(ICC = 0.9 µA Max)
Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typ)
Low Noise – Overshoot and Undershoot
<10% of VCC
Ioff Supports Partial-Power-Down Mode
Operation
Input Hysteresis Allows Slow Input Transition
and Better Switching-Noise Immunity at the
Input (Vhys = 250 mV Typ at 3.3 V)
Wide Operating VCC Range of 0.8 V to 3.6 V
A
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 4.5 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
ESD Protection Exceeds ±5000 V With
Human-Body Model
•
•
•
•
•
VCC
A
VCC
A
B
B
GND
B
Y
GND
GND
VCC
Y
Y
DRY PACKAGE
(TOP VIEW)
A
B
GNDP
1
3
V
W CC
I5E NC
V
RE
2
6
4
YZP PACKAGE
(BOTTOM VIEW)
GND
Y
3 4
B
2
A
1 5
Y
VCC
YFP PACKAGE
(BOTTOM VIEW)
GND 3 4 YW
E
5 I DNU
B 2V
E
6
1
VCC
AR
P
See mechanical drawings for dimensions.
NC - No internal connection
DNU - Do not use
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see Figure 1 and Figure 2).
This single 2-input positive-NOR gate performs the Boolean function Y = A + B or Y = A • B in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
SN74AUP1G02
LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE
www.ti.com
SCES568D – JUNE 2004 – REVISED MAY 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Static-Power Consumption
Dynamic-Power Consumption
(µA)
(pF)
Switching Characteristics
at 25 MHz†
3.5
100%
80%
80%
3.3-V
Logic†
60%
60%
3
Voltage − V
100%
3.3-V
Logic†
LVC
2.5
40%
40%
0.5
20%
20%
0
−0.5
AUP
0%
†
Input
2
Output
1.5
1
0
5
10
AUP
0%
†
15
20 25 30
Time − ns
35
40
45
AUP1G08 data at CL = 15 pF
Single, dual, and triple gates
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
ORDERING INFORMATION
PACKAGE (1) (2)
TA
(2)
(3)
Reel of 3000
SN74AUP1G02YFPR
PREVIEW
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUP1G02YZPR
PREVIEW
Reel of 5000
SN74AUP1G02DRYR
PREVIEW
SOT (SOT-23) – DBV
Reel of 3000
SN74AUP1G02DBVR
H02_
SOT (SC-70) – DCK
Reel of 3000
SN74AUP1G02DCKR
HB_
SOT (SOT-553) – DRL
Reel of 4000
SN74AUP1G02DRLR
HB_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
A
B
OUTPUT
Y
L
L
H
L
H
L
H
L
L
H
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
2
TOP-SIDE MARKING (3)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP (Pb-free)
–40°C to 85°C SON – DRY
(1)
ORDERABLE PART NUMBER
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SN74AUP1G02
LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE
www.ti.com
SCES568D – JUNE 2004 – REVISED MAY 2007
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
–0.5
4.6
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Output voltage range in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
θJA
Package thermal impedance (3)
DBV package
206
DCK package
252
DRL package
142
DRY package
234
YFP/YZP package
Tstg
(1)
(2)
(3)
Storage temperature range
V
°C/W
132
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74AUP1G02
LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE
www.ti.com
SCES568D – JUNE 2004 – REVISED MAY 2007
Recommended Operating Conditions (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
MIN
MAX
0.8
3.6
Low-level input voltage
VI
Input voltage
VO
Output voltage
0.65 × VCC
High-level output current
2
0
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
Low-level output current
0.9
0
3.6
0
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
V
VCC
V
VCC = 0.8 V
–20
µA
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65 V
–1.9
VCC = 2.3 V
–3.1
mA
–4
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
∆t/∆v
V
0.7
VCC = 3 V
IOL
V
1.6
VCC = 3 V to 3.6 V
IOH
V
VCC
VCC = 0.8 V
VIL
UNIT
µA
mA
4
VCC = 0.8 V to 3.6 V
–40
200
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74AUP1G02
LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE
www.ti.com
SCES568D – JUNE 2004 – REVISED MAY 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
0.8 V to 3.6 V
IOH = –1.1 mA
TA = –40°C to 85°C
MAX
MIN
VCC – 0.1
1.1 V
0.75 ×
VCC
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.11
1.03
IOH = –1.9 mA
1.65 V
1.32
1.3
2.05
1.97
1.9
1.85
2.72
2.67
2.3 V
IOH = –2.7 mA
3V
IOH = –4 mA
2.6
IOL = 20 µA
0.8 V to 3.6 V
IOL = 1.1 mA
MAX
UNIT
V
2.55
0.1
0.1
1.1 V
0.3 × VCC
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.31
0.37
IOL = 1.9 mA
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
0.44
0.45
0 V to 3.6 V
0.1
0.5
µA
IOL = 2.3 mA
2.3 V
IOL = 3.1 mA
IOL = 2.7 mA
3V
IOL = 4 mA
II
TYP
VCC – 0.1
IOH = –3.1 mA
A or B
inputs
MIN
IOH = –20 µA
IOH = –2.3 mA
VOL
TA = 25°C
VCC
VI = GND to 3.6 V
V
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
0.6
µA
∆Ioff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
µA
ICC
VI = GND or (VCC to 3.6 V),
IO = 0
0.8 V to 3.6 V
0.5
0.9
µA
∆ICC
VI = VCC – 0.6 V (1),
IO = 0
3.3 V
40
50
µA
Ci
VI = VCC or GND
Co
VO = GND
(1)
0V
1.5
3.6 V
1.5
0V
pF
3
pF
One input at VCC – 0.6 V, other inputs at VCC or GND
Switching Characteristics
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
0.8 V
tpd
A or B
Y
TYP
TA = –40°C to 85°C
MAX
MIN
MAX
19.3
1.2 V ± 0.1 V
2.6
7.3
13
2.1
16.3
1.5 V ± 0.1 V
1.4
5.2
8.9
0.9
10.8
1.8 V ± 0.15 V
1
4.2
6.8
0.5
8.7
2.5 V ± 0.2 V
1
3
4.6
0.5
5.9
3.3 V ± 0.3 V
1
2.4
3.7
0.5
4.6
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UNIT
ns
5
SN74AUP1G02
LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE
www.ti.com
SCES568D – JUNE 2004 – REVISED MAY 2007
Switching Characteristics
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
VCC
MIN
0.8 V
tpd
A or B
Y
TA = –40°C to 85°C
TYP MAX
MIN
MAX
UNIT
22.3
1.2 V ± 0.1 V
1.5
8.5
14.9
1
17.9
1.5 V ± 0.1 V
1
6.2
10.2
0.5
11.8
1.8 V ± 0.15 V
1
5
7.9
0.5
9.5
2.5 V ± 0.2 V
1
3.6
5.4
0.5
6.5
3.3 V ± 0.3 V
1
2.9
4.4
0.5
5
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
VCC
MIN
TYP
1.2 V ± 0.1 V
3.6
0.8 V
tpd
A or B
Y
TA = –40°C to 85°C
MAX
MIN
MAX
9.9
16.5
3.1
20.6
UNIT
25
1.5 V ± 0.1 V
2.3
7.2
11.3
1.8
13.7
1.8 V ± 0.15 V
1.6
5.8
8.9
1.1
11.1
2.5 V ± 0.2 V
1
4.3
6.1
0.5
7.7
3.3 V ± 0.3 V
1
3.4
5
0.5
6.2
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
VCC
MIN
0.8 V
tpd
A or B
Y
TYP
TA = –40°C to 85°C
MAX
MIN
MAX
UNIT
34.6
1.2 V ± 0.1 V
4.9
13.1
21.1
4.4
26.2
1.5 V ± 0.1 V
3.4
9.5
14.4
2.9
17.4
1.8 V ± 0.15 V
2.5
7.7
11.2
2
14
2.5 V ± 0.2 V
1.8
5.7
7.8
1.3
9.8
3.3 V ± 0.3 V
1.5
4.7
6.4
1
7.8
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
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VCC
TYP
0.8 V
4.1
1.2 V ± 0.1 V
4.1
1.5 V ± 0.1 V
4.1
1.8 V ± 0.15 V
4.1
2.5 V ± 0.2 V
4.2
3.3 V ± 0.3 V
4.3
UNIT
pF
SN74AUP1G02
LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE
www.ti.com
SCES568D – JUNE 2004 – REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Duration)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
VCC/2
0V
tPLH
tsu
VOH
VM
Output
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
E.
th
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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SN74AUP1G02
LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE
www.ti.com
SCES568D – JUNE 2004 – REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × VCC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
VOL + V∆
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL
tPHZ
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUP1G02DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DBVRE4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DCKRE4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DCKTE4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DRLR
ACTIVE
SOT
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G02DRLRG4
ACTIVE
SOT
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
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to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74AUP1G02DBVR
SOT-23
3000
180.0
DBV
5
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.2
3.23
3.17
1.37
4.0
8.0
Q3
SN74AUP1G02DBVT
SOT-23
DBV
5
250
180.0
9.2
3.23
3.17
1.37
4.0
8.0
Q3
SN74AUP1G02DCKR
SC70
DCK
5
3000
180.0
9.2
2.24
2.34
1.22
4.0
8.0
Q3
SN74AUP1G02DCKT
SC70
DCK
5
250
180.0
9.2
2.24
2.34
1.22
4.0
8.0
Q3
SN74AUP1G02DRLR
SOT
DRL
5
4000
180.0
9.2
1.78
1.78
0.69
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1G02DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74AUP1G02DBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
SN74AUP1G02DCKR
SC70
DCK
5
3000
202.0
201.0
28.0
SN74AUP1G02DCKT
SC70
DCK
5
250
202.0
201.0
28.0
SN74AUP1G02DRLR
SOT
DRL
5
4000
202.0
201.0
28.0
Pack Materials-Page 2
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