SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES503D – NOVEMBER 2003 – REVISED JUNE 2005 • • FEATURES • • • • • • • • Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Low Static-Power Consumption (ICC = 0.9 µA Max) Low Dynamic-Power Consumption (Cpd = 4.3 pF Typ at 3.3 V) Low Input Capacitance (Ci = 1.5 pF Typ) Low Noise – Overshoot and Undershoot <10% of VCC Ioff Supports Partial-Power-Down Mode Operation Includes Schmitt-Trigger Inputs Wide Operating VCC Range of 0.8 V to 3.6 V DBV PACKAGE (TOP VIEW) In1 1 6 Optimized for 3.3-V Operation 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation tpd = 5.3 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) ESD Protection Exceeds ±5000 V With Human-Body Model • • • • • DCK PACKAGE (TOP VIEW) In1 In2 GND 2 5 VCC In0 3 4 Y 1 6 GND 2 5 In0 3 4 YEA, YEP, YZA, OR YZP PACKAGE (BOTTOM VIEW) DRL PACKAGE (TOP VIEW) In2 VCC In1 1 6 In2 GND 2 5 VCC In0 3 4 Y In0 3 4 Y GND 2 5 VCC In1 1 6 In2 Y See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity, which produces very low undershoot and overshoot characteristics. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP Tape and reel SN74AUP1G57YEPR NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Tape and reel SN74AUP1G57YZPR SOT (SOT-23) – DBV Tape and reel SN74AUP1G57DBVR HA7_ SOT (SC-70) – DCK Tape and reel SN74AUP1G57DCKR HH_ SOT (SOT-553) – DRL Reel of 4000 SN74AUP1G57DRLR HH_ _ _ _HH_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES503D – NOVEMBER 2003 – REVISED JUNE 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The SN74AUP1G57 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All inputs can be connected to VCC or GND. The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition and better switching noise immunity at the input. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS In0 OUTPUT Y L L H L H L L H L H L H H L H L L L H L H L H H L H H H H H In2 In1 L L LOGIC DIAGRAM (POSITIVE LOGIC) In0 3 4 In1 In2 2 1 6 Y SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES503D – NOVEMBER 2003 – REVISED JUNE 2005 FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-input AND 1 2-input AND with both inputs inverted 4 2-input NAND with inverted input 2, 3 2-input OR with inverted input 2, 3 2-input NOR 4 2-input NOR with both inputs inverted 1 2-input XNOR 5 LOGIC CONFIGURATIONS VCC VCC A Y B A A Y B A Y B 1 6 2 5 3 4 A B A Y Y B Figure 1. 2-Input AND Gate 1 6 2 5 3 4 B Y Figure 2. 2-Input NAND Gate With Inverted A Input VCC VCC A A Y B A B Y Y B A 1 6 2 5 3 4 B A Y A B Y Figure 3. 2-Input NAND Gate With Inverted B Input 1 6 2 5 3 4 B Y Figure 4. 2-Input NOR Gate VCC A Y B A 1 6 2 5 3 4 B Y Figure 5. 2-Input XNOR Gate 3 SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES503D – NOVEMBER 2003 – REVISED JUNE 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 4.6 V –0.5 4.6 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Output voltage range in the high or low state (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA Continuous current through VCC or GND ±50 mA θJA Package thermal impedance (3) Tstg (1) (2) (3) DBV package 165 DCK package 259 DRL package 142 YEP/YZP package 123 Storage temperature range –65 V °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) MIN MAX 0.8 3.6 V Input voltage 0 3.6 V Output voltage 0 VCC V VCC = 0.8 V –20 µA VCC = 1.1 V –1.1 VCC = 1.4 V –1.7 VCC = 1.65 –1.9 VCC = 2.3 V –3.1 VCC Supply voltage VI VO IOH High-level output current VCC = 3 V IOL Low-level output current Input transition rise or fall rate TA Operating free-air temperature (1) 4 mA –4 VCC = 0.8 V 20 VCC = 1.1 V 1.1 VCC = 1.4 V 1.7 VCC = 1.65 V 1.9 VCC = 2.3 V 3.1 VCC = 3 V ∆t/∆v UNIT µA mA 4 VCC = 0.8 V to 3.6 V –40 200 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES503D – NOVEMBER 2003 – REVISED JUNE 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VT+ Positive-going input threshold voltage VTNegative-going input threshold voltage ∆VT Hysteresis (VT+ – VT–) TA = –40°C to 85°C MAX MIN MAX 0.6 0.3 0.6 0.3 1.1 V 0.53 0.9 0.53 0.9 1.4 V 0.74 1.11 0.74 1.11 1.65 V 0.91 1.29 0.91 1.29 2.3 V 1.37 1.77 1.37 1.77 3V 1.88 2.29 1.88 2.29 0.8 V 0.1 0.6 0.1 0.6 1.1 V 0.26 0.65 0.26 0.65 1.4 V 0.39 0.75 0.39 0.75 1.65 V 0.47 0.84 0.47 0.84 2.3 V 0.69 1.04 0.69 1.04 1.24 3V 0.88 1.24 0.88 0.8 V 0.07 0.5 0.07 0.5 1.1 V 0.08 0.46 0.08 0.46 1.4 V 0.18 0.56 0.18 0.56 1.65 V 0.27 0.66 0.27 0.66 2.3 V 0.53 0.92 0.53 0.92 0.79 1.31 0.79 1.31 IOH = –20 µA 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1 IOH = –1.1 mA 1.1 V 0.75 × VCC 0.7 × VCC IOH = –1.7 mA 1.4 V 1.11 1.03 IOH = –1.9 mA 1.65 V 1.32 1.3 2.05 1.97 1.9 1.85 2.72 2.67 IOH = –2.3 mA 2.3 V IOH = –3.1 mA IOH = –2.7 mA 3V IOH = –4 mA VOL TYP 0.8 V 3V VOH TA = 25°C MIN IOL = 20 µA 0.8 V to 3.6 V IOL = 1.1 mA 2.6 1.1 V 0.3 × VCC 0.3 × VCC IOL = 1.7 mA 1.4 V 0.31 0.37 IOL = 1.9 mA 1.65 V 0.31 0.35 0.31 0.33 0.44 0.45 0.31 0.33 2.3 V IOL = 2.7 mA 3V IOL = 4 mA V V 2.55 0.1 IOL = 3.1 mA V V 0.1 IOL = 2.3 mA UNIT 0.44 0.45 0 V to 3.6 V 0.1 V 0.5 µA Ioff VI or VO = 0 V to 3.6 V 0V 0.2 0.6 µA ∆Ioff VI or VO = 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 µA ICC VI = GND or (VCC to 3.6 V), IO = 0 0.8 V to 3.6 V 0.5 0.9 µA ∆ICC VI = VCC – 0.6 V (1), IO = 0 3.3 V 40 50 µA II All inputs VI = GND to 3.6 V Ci VI = VCC or GND Co VO = GND (1) 0V 1.5 3.6 V 1.5 0V 3 pF pF One input at VCC – 0.6 V, other inputs at VCC or GND 5 SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES503D – NOVEMBER 2003 – REVISED JUNE 2005 Switching Characteristics over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 6 and Figure 7) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25°C VCC MIN 0.8 V tpd In0, In1, or In2 Y TA = –40°C to 85°C TYP MAX MIN MAX UNIT 28.6 1.2 V ± 0.1 V 2.6 9.5 13.6 2.1 17.1 1.5 V ± 0.1 V 1.9 6.4 9.1 1.4 11.1 1.8 V ± 0.15 V 1.4 5.2 7.1 0.9 8.9 2.5 V ± 0.2 V 1.1 3.6 5.3 0.6 6.3 3.3 V ± 0.3 V 1 2.9 4.4 0.5 5.3 ns Switching Characteristics over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 6 and Figure 7) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN 0.8 V tpd In0, In1, or In2 Y TA = –40°C to 85°C TYP MAX MIN MAX UNIT 32.8 1.2 V ± 0.1 V 2.6 11 15.1 2.1 18.1 1.5 V ± 0.1 V 1.9 7.4 10.3 1.4 12.4 1.8 V ± 0.15 V 1.4 6 8.1 0.9 10 2.5 V ± 0.2 V 1.1 4.3 6.1 0.6 7.3 3.3 V ± 0.3 V 1 3.5 5.1 0.5 6.1 ns Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 6 and Figure 7) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN 0.8 V tpd In0, In1, or In2 Y TA = –40°C to 85°C TYP MAX MIN MAX UNIT 37 1.2 V ± 0.1 V 3.6 12.3 16.8 3.1 20.1 1.5 V ± 0.1 V 2.8 8.3 11.4 2.3 13.7 1.8 V ± 0.15 V 2.1 6.7 9 1.6 11.1 2.5 V ± 0.2 V 1.7 4.9 6.8 1.2 8.1 3.3 V ± 0.3 V 1.5 3.9 5.6 1 6.7 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 6 and Figure 7) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN 0.8 V tpd 6 In0, In1, or In2 Y TYP TA = –40°C to 85°C MAX MIN MAX UNIT 49.3 1.2 V ± 0.1 V 5 15.7 21.4 4.5 26.5 1.5 V ± 0.1 V 3.9 10.8 14.4 3.4 17.4 1.8 V ± 0.15 V 3.1 8.8 11.4 2.6 14 2.5 V ± 0.2 V 2.6 6.4 8.4 2.1 10.1 3.3 V ± 0.3 V 2.3 5.3 7 1.8 8.4 ns SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES503D – NOVEMBER 2003 – REVISED JUNE 2005 Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC TYP 0.8 V 4 1.2 V ± 0.1 V 4 1.5 V ± 0.1 V 4 1.8 V ± 0.15 V 4 2.5 V ± 0.2 V 4.1 3.3 V ± 0.3 V 4.3 UNIT pF 7 SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES503D – NOVEMBER 2003 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION (Propagation Delays, Setup and Hold Times, and Pulse Duration) From Output Under Test CL (see Note A) 1 MΩ LOAD CIRCUIT CL VM VI VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC tw VCC Input VCC/2 VCC/2 VI VM Input 0V VM VOLTAGE WAVEFORMS PULSE DURATION 0V tPHL tPLH VOH VM Output VM VOL tPHL VCC Timing Input 0V tPLH tsu VOH VM Output VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 6. Load Circuit and Voltage Waveforms 8 th VM VOL NOTES: A. B. C. D. E. VCC/2 SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES503D – NOVEMBER 2003 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) 2 × VCC S1 5 kΩ From Output Under Test GND CL (see Note A) 5 kΩ TEST S1 tPLZ/tPZL tPHZ/tPZH 2 × VCC GND LOAD CIRCUIT CL VM VI V∆ VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.3 V VCC Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 0V tPZL tPLZ VCC VCC/2 tPZH Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL + V∆ VOL tPHZ VCC/2 VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. All parameters and waveforms are not applicable to all devices. Figure 7. Load Circuit and Voltage Waveforms 9 PACKAGE OPTION ADDENDUM www.ti.com 12-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AUP1G57DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G57DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G57DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G57DBVTE4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G57DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G57DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G57DCKT ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G57DCKTE4 ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G57DRLR ACTIVE SOP DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G57YEPR ACTIVE WCSP YEP 6 3000 TBD SNPB Level-1-260C-UNLIM SN74AUP1G57YZPR ACTIVE WCSP YZP 6 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS114 – FEBRUARY 2002 DCK (R-PDSO-G6) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 6 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-3/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-203 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated