SANYO VPS10

Ordering number : EN5209
Wide-Bandwidth Output Module (video pack)
VPS10
CRT Display Video Output Amplifier:
High-Voltage, Wideband Amplification
Features
Package Dimensions
• High output voltage and wide bandwidth make the
VPS10 optimal for use in f H (horizontal deflection
frequency) = 85 kHz class color monitors.
(f = 100 MHz –3 dB at VOUT = 50 Vp-p)
• SIP molded 15-pin package with three channels in a
single package.
unit: mm
2127
[VPS10]
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
VCC max
120
V
VBB max
15
V
Allowable power dissipation
Pd max
Junction temperature
Tj max
Case temperature
Tc max
Storage temperature
Tc = 25°C with an ideal heat sink
Tstg
25
W
150
°C
100
°C
–20 to +110
°C
Ratings
Unit
Operating Conditions at Ta = 25°C
Parameter
Recommended supply voltage I
Recommended supply voltage II
Symbol
Conditions
VCC
80
V
VBB
10
V
VCC
90
V
VBB
10
V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
53096HA (OT) No. 5209-1/4
VPS10
Electrical Characteristics at Ta = 25°C (for a single channel)
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
Frequency band I (–3 dB)
fc
VCC = 80 V, VBB = 10 V, CL = 10 pF, VIN (DC) = 2.7 V,
VOUT (p-p) = 40 V
100
MHz
Frequency band II
tc
VCC = 90 V, VBB = 10 V, CL = 10 pF, VIN (DC) = 3.0 V,
VOUT (p-p) = 50 V
100
MHz
tr
VCC = 80 V, VBB = 10 V, CL = 10 pF, VIN (DC) = 2.7 V,
5.0
ns
tf
VOUT (p-p) = 40 V
3.5
Pulse response characteristics
Voltage gain
GV (DC)
17
19
ns
21
times
ICC1
VCC = 80 V, VBB = 10 V, CL = 10 pF, VIN (DC) = 2.5 V,
VOUT (p-p) = 40 V, f = 10 MHz clock
43
mA
ICC2
VCC = 80 V, VBB = 10 V, CL = 10 pF, VIN (DC) = 2.5 V,
VOUT (p-p) = 40 V, f = 100 MHz clock
60
mA
ICC1
VCC = 90 V, VBB = 10 V, CL = 10 pF, VIN (DC) = 2.8 V,
VOUT (p-p) = 50 V, f = 10 MHz clock
50
mA
ICC2
VCC = 90 V, VBB = 10 V, CL = 10 pF, VIN (DC) = 2.8 V,
VOUT (p-p) = 50 V, f = 100 MHz clock
75
mA
Current drain I
Current drain II
Internal Equivalent Circuit
Test Circuit (for a single channel)
No. 5209-2/4
VPS10
Thermal Design
Since the VPS10 includes three channels as shown in the internal equivalent circuit diagram, we first consider a single
channel. The chip temperature of each transistor under actual operating conditions is determined using the following
formula.
Tj (TRi) = θj-c (TRi) × PC (TRi) + ∆Tc + Ta (°C) ........................... (1)
θj-c (Tri): Thermal resistance of an individual transistor
PC (Tri):
Collector loss for an individual transistor
∆Tc:
Case temperature rise
Ta:
Ambient temperature
The θj-c (Tri) for each chip is:
θj-c (TR1) to (TR4) = 30°C/W.......................................................... (2)
Although the loss for each transistor in a video pack varies with frequency and is not uniform, if we assume operation at
the maximum operating frequency, f = 100 MHz (clock), then the chips with the largest loss will be the emitter-follower
stage transistors (TR3 and TR4) and that loss will be about 20% of the total loss. Thus from the Pd (shown in the figure)
for a single channel we have:
PC (E and F stages)f = 100 MHz = Pd (1ch)f = 100 MHz × 0.20 [W] ......... (3)
Here, we must select a heat sink with a capacity θh such that the Tj of these transistors does not exceed 150°C. Equation
(4) below gives the relationship between θh and ∆Tc.
∆Tc = Pd (TOTAL) × θh................................................................... (4)
The required θh is calculated using this equation and equation (1).
No. 5209-3/4
VPS10
VPS10 Thermal Design Example
Conditions: Using an fH = 85 kHz class monitor, fV = 100 MHz (clock)
VCC = 90 V, VBB = 10 V, VOUT = 50 Vp-p (CL = 10 pF)
Consider the case where the maximum clock frequency is 100 MHz, taking into account the fact that this class of monitor
can be operated at ambient temperatures up to Ta = 60°C.
As mentioned previously, the chips with the largest loss are the transistors in the emitter-follower stage. Determining
those values gives:
PC (E and F stages) = 7.2 × 0.20 = 1.44 [W]..................................... (5)
We determine ∆Tj by substituting the value for θj-c in equation (5).
∆Tj = 1.44 × 30 = 43.2 [°C]
Therefore, Tj (max) will be 43.2 + Tc (max) = 43.2 + 100. Since this will be under 100°C, it suffices to design a heat sink
that guarantees that Tc will be under 100°C.
Therefore, a heat sink such that Tc < 100°C will have the following thermal resistance:
θh = ∆Tc ÷ Pd (TOTAL) = (Tc – Ta) ÷ [Pd (1ch) × 3] = 40 ÷ (7.2 × 3) = 1.85°C/W
Thus the thermal resistance in this case is θh = 1.8°C/W.
In actual practice, the ambient temperature and operating conditions will allow a heat sink smaller than that indicated by
this calculation to be used. Therefore, design optimization taking the actual conditions into account is also required.
Item
VCC (V)
VBB (V)
VOUT (V)
VO (center)
1
90
10
50
50
2
80
10
40
45
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 1997. Specifications and information herein are subject to
change without notice.
No. 5209-4/4