SEMTECH SC9301

SC9301
10A EcoSpeed® Integrated FET
Regulator with 5V LDO and Hiccup Restart
POWER MANAGEMENT
Features
Description
„
The SC9301 is a stand-alone synchronous EcoSpeed® buck
regulator with adaptive on-time control architecture. It
features integrated power MOSFETs, a bootstrap switch,
and a fixed 5V LDO in a 5x5mm package. The device is
highly efficient and uses minimal PCB area. The SC9301
supports using standard capacitor types such as electrolytic or specialty polymer, in addition to ceramic, at switching frequencies up to 1MHz.
Power system
Input voltage — 3V to 28V
Bias Voltage — 5V LDO or 3V to 5.5V external
Up to 96% peak efficiency
Integrated bootstrap switch
LDO output current — up to 200mA
Reference tolerance — 1% TJ= -40 to +125 °C
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EcoSpeed® architecture with pseudo-fixed frequency adaptive on-time control
Pre-bias start-up
Logic input and output control
Independent enable control for LDO and
switcher
Programmable VIN UVLO threshold
Power good output
Programmable soft-start time
All protection: automatic restart on fault
Over-voltage and under-voltage
TC compensated RDS(ON) sensed current limit
Thermal shutdown
Smart gate drive reduces EMI
Capacitor types: SP, POSCAP, OSCON, and ceramic
Package — 5 x 5(mm), 32-pin MLPQ
Lead-free and halogen-free
RoHS and WEEE compliant
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„
Additional features include programmable cycle-by-cycle
current limit protection, programmable soft-start, under
and over-voltage protection, automatic fault recovery
(hiccup restart), and soft shutdown. The device also provides separate enable inputs for the PWM controller and
LDO as well as a power good output for the PWM
controller.
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Applications
„
Networking and telecommunication equipment
„ Printers, DSL, and STB applications
„ Point-of-load power supplies and module replacement
Typical Application Circuit
RTON
EN
ILIM
ENL
LXS
TON
PGOOD
RILIM
PGOOD
VOUT
VDD
L1
SC9301
VOUT
LX
1 μF
CSOFT
SS
LXBST
CIN
BST
VIN
VIN
RFB1
+
COUT
FB
RFB2
CBST
Rev. 2.0
© Semtech Corporation
1
SC9301
VLDO
5
VIN
6
SS
7
BST
8
LXS
ILIM
PGOOD
LX
AGND
EN
TON
25
SC9301EVB
AGND
PAD 1
LX
PAD 3
VIN
PAD 2
9
10
11
12
13
14
15
16
PGND
4
26
PGND
AGND
Evaluation Board
27
DL
3
MLPQ-32, 5 x 5(mm)
28
LXBST
VDD
Package
29
Top View
DH
2
30
VIN
VOUT
31
Device
SC9301MLTRT(1)(2)
VIN
1
32
Ordering Information
VIN
FB
ENL
Pin Configuration
24
LX
23
LX
22
PGND
21
PGND
20
PGND
19
PGND
18
PGND
17
PGND
Notes:
1) Available in tape and reel only. A reel contains 3000 devices.
2) Lead-free packaging only. Device is WEEE and RoHS compliant
and halogen-free.
MLPQ-UT32
Marking Information
9301
yyww
xxxx
yyww = Date Code
xxxx = Semtech Lot Number
2
SC9301
Absolute Maximum Ratings(1)
Recommended Operating Conditions
LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30
Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 to 28
LX to PGND (V) (transient — 100ns max.) . . . . . . -2 to +30
VDD to PGND (V) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5
DH, BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35
VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 to 5.5
DH, BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6
Thermal Information
DL to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6
VIN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30
Storage Temperature (°C) . . . . . . . . . . . . . . . . . . . . -60 to +150
EN, FB, ILIM, PGOOD to AGND (V) . . . . . . -0.3 to +(VDD + 0.3)
Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . . 150
SS, VLDO, VOUT to AGND (V) . . . . . . . . . -0.3 to +(VDD + 0.3)
Operating Junction Temperature (°C) . . . . . . . . -40 to +125
TON to AGND (V). . . . . . . . . . . . . . . . . . . . . -0.3 to +(VDD -1.5)
Thermal resistance, junction to ambient (2) (°C/W)
ENL to AGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN
High-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VDD to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 to +6
Low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to +0.3
PWM controller and LDO thermal resistance . . . . . 50
ESD Protection Level (1) (kV). . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Peak IR Reflow Temperature (°C) . . . . . . . . . . . . . . . . . . . . 260
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless specified: VIN =12V, VDD = 5V, TA = +25°C for Typ, -40 to +85 °C for Min and Max, TJ < 125°C, Typical Application Circuit
Parameter
Conditions
Min
VIN > VDD
Typ
Max
Units
3
28
V
3
5.5
V
Input Supplies
Input Supply Voltage
VDD Voltage
Sensed at ENL pin, rising edge
1.47
Sensed at ENL pin, falling edge
1.15
1.57
1.77
VIN UVLO Threshold(1)
VIN UVLO Hysteresis
V
Sensed at ENL pin; EN = 5V
1.35
0.3
V
Measured at VDD pin, rising edge
2.5
3.0
Measured at VDD pin, falling edge
2.4
2.9
VDD UVLO Threshold
V
VDD UVLO Hysteresis
0.18
Shutdown mode; ENL , EN = 0V
8.5
Standby mode; ENL = VDD, EN = 0V
130
VIN Supply Current
V
20
μA
3
SC9301
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
ENL , EN = 0V
3
7
μA
VDD =5V, fSW = 270kHz, EN = VDD, no load(2)
7.7
mA
VDD =3.3V, fSW = 280kHz, EN = VDD, no load(2)
5.1
mA
Input Supplies (continued)
VDD Supply Current
Static VIN and load, TJ= 0 to +125 °C
0.595
0.600
0.605
V
Static VIN and load, TJ= -40 to +125 °C
0.594
0.600
0.606
V
1000
kHz
FB Comparator Threshold
Frequency Range
Bootstrap Switch Resistance
17
Ω
Timing
On-Time
VIN = 15V, VOUT = 3V, RTON = 300kΩ, VDD = 5V
Minimum On-Time (2)
1395
1600
1805
ns
80
ns
VDD =5V
250
ns
VDD =3.3V
370
ns
3.0
μA
1.5
V
500
kΩ
Upper limit, VFB > internal 600mV reference
+20
%
Lower limit, VFB < internal 600mV reference
-10
%
1.2
%
VDD = 5V, CSS = 3.3nF
3.8
ms
VDD = 3.3V, CSS = 3.3nF
2.6
ms
5
μs
Minimum Off-Time(2)
Soft-Start
Soft-Start Charge Current
Soft-Start Voltage(2)
When VOUT reaches regulation
Analog Inputs/Outputs
VOUT Input Resistance
Power Good
Power Good Threshold
Power Good Hysteresis
Start-Up Delay Time(2)
(between PWM enable and PGOOD high)
Fault (noise immunity) Delay Time(2)
Leakage
Power Good On Resistance
PGOOD = high impedance (open)
1
10
μA
Ω
4
SC9301
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
VDD = 5V, RILIM = 7320, TJ = 0 to +125 °C
8.5
10
11.5
A
Fault Protection
Valley Current Limit(3)
ILIM Source Current
ILIM Comparator Offset
VDD = 3.3V, RILIM = 7320, TJ = 0 to +125 °C
9
A
Trimmed to match lower FET Rdson
9
μA
With respect to AGND
-8
0
+8
mV
Output Under-Voltage Threshold
VFB with respect to internal 600mV reference,
8 consecutive cycles
-25
%
Smart Power-Save Protection Threshold(2)
VFB with respect to internal 600mV reference
+10
%
Over-Voltage Protection Threshold
VFB with respect to internal 600mV reference
+20
%
5
μs
150
°C
Over-Voltage Fault Delay(2)
Over-Temperature Shutdown(2)
10°C hysteresis
Logic Inputs/Outputs
Logic Input High Voltage
EN, ENL
Logic Input Low Voltage
EN, ENL
1.0
EN Input Bias Current
EN = VDD or AGND
-10
ENL Input Bias Current
ENL = VIN = 28V
-1
FB Input Bias Current
FB = VDD or AGND
-1
VLDO load = 10mA
4.90
V
11
0.4
V
+10
μA
+18
μA
+1
μA
5.10
V
Linear Regulator (LDO)
VLDO Accuracy
Current Limit
VLDO Drop Out Voltage(4)
5.0
Short-circuit protection, VIN = 12V, VLDO < 1V
20
VIN = 12V, 1V < VLDO < 4.5V
115
Operating, VLDO > 4.5V
200
VIN to VLDO, VLDO load = 100mA
1.9
mA
V
Notes:
(1) VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
(2) Typical value measured on standard evaluation board.
(3) The device has first order temperature compensation for over current. Results vary based upon the PCB thermal layout.
(4) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point.
5
SC9301
Detailed Application Circuit
EN
PGOOD
RILIM
EN LDO
7.68KΩ
AGND
1
2
3
4
5
6
7
8
RBST
0Ω
VIN
CBST
1 μF
VIN
3.3nF
SC9301
LX
LX
PGND
PGND
PGND
PGND
PGND
PGND
LX
24
23
22
21
20
19
18
17
PAD 3
9
10
11
12
13
14
15
16
1μF
PAD 2 VIN
1 μF
FB
VOUT
VDD
AGND
VLDO
VIN
SS
BST
VIN
VIN
DH
LXBST
DL
PGND
PGND
PAD 1
ENL
TON
AGND
EN
LXS
ILIM
PGOOD
LX
32
31
30
29
28
27
26
25
RTON
130 KΩ
CIN
2 x 10 μF
(see note)
RGND
0
L1
1.5V @ 10A, 350kHz
1 .2μH
COUT
330μF
6mΩ
RFB1
10K Ω
+
VOUT
22μF
RFB2
6.65KΩ
Key Components
Part Number
Web
CIN (see note)
Component
2 x 10μF/25V
Value
Manufacturer
Murata
GRM32DR71E106KA12L
www.murata.com
COUT
330μF/6mΩ
Sanyo
2TPF330M6
www.sanyo.com
L1
1.2μH/1.8mΩ
Wurth Elektronik
744 325 120
www.we-online.com
NOTE: The quantity of 10μF input capacitors required varies with the application requirements.
6
SC9301
Typical Characteristics
Characteristics in this section are based upon using the Typical Application Circuit on page 6.
Efficiency/Power Loss Comparison
Efficiency/Power Loss vs. Load
LDO Bias, VDD = 5V, VOUT = 1.5V
95
VIN = 12V
VIN = 5V
0.300
3.3V Bias
90
4.0
85
0.250
3.0
VIN = 18V
70
65
2.0
Efficiency (%)
VIN = 25V
75
Power Loss (W)
85
80
VIN = 25V
60
1.0
55
VIN = 5V
50
0
1
2
3
4
5
VIN = 12V
6
7
8
9
0.0
10
0.200
5V Bias
80
0.150
75
0.100
70
65
0.000
60
-0.050
55
-0.100
50
0
1
2
3
4
5
IOUT (A)
External Bias, VDD = 5V, VOUT = 1.5V
VIN = 5V
95
5.0
100
VIN = 18V
4.0
8
-0.150
10
9
VDD = 5V, VIN = 12V, L = 2.2uH (4.6mΩ) for VOUT = 2.5V, 3.3V and 5V
VOUT = 5V
VOUT = 3.3V
90
85
3.0
75
70
2.0
VIN = 18V
Efficiency (%)
85
VIN = 25V
80
PLOSS (W)
Efficiency (%)
7
95
90
65
VOUT = 2.5V
80
VOUT = 1.5V
VOUT = 1V
75
70
65
VIN = 25V
60
55
VIN = 5V
50
0
1
2
3
4
5
IOUT (A)
1.0
60
55
VIN = 12V
6
7
8
9
0.0
10
50
0
1
Efficiency/Power Loss Comparison
3
4
5
IOUT (A)
6
7
8
9
10
External Bias, VDD = 5V, VOUT = 1.5V, VIN = 12V
100
400
0.200
95
2
Switching Frequency vs. Load
VDD = 5V, VOUT = 1.5V, VIN = 12V
0.180
Ext-Bias
350
LDO-Bias
0.140
80
0.120
75
0.100
70
0.080
LDO minus Ext
65
0.060
60
0.040
55
0.020
50
0.000
0
1
2
3
4
5
IOUT (A)
6
7
8
9
10
PLOSS (W)
85
Switching Frequency (kHz)
0.160
90
Efficiency (%)
6
Efficiency/Power Loss Comparison
Efficiency/Power Loss vs. Load
VIN = 12V
0.050
3.3V minus 5V
IOUT (A)
100
0.350
95
VIN = 18V
90
Efficiency (%)
External Bias, VIN = 12V, VOUT = 1.5V
100
5.0
PLOSS (W)
100
300
250
200
150
100
50
0
0
1
2
3
4
5
IOUT (A)
6
7
8
9
10
7
SC9301
Typical Characteristics
Characteristics in this section are based upon using the Typical Application Circuit on page 6.
Load Regulation
Load Regulation
External Bias, VDD = 3.3V, VOUT = 1.5V
External Bias, VDD = 5V, VOUT = 1.5V
1.530
1.530
1.525
1.525
1.520
Vout (V)
Vout (V)
VIN = 18V
VIN = 25V
1.520
VIN = 12V
1.515
1.510
VIN = 12V
1.515
1.510
VIN = 5V
1.505
1.505
1.500
0
1
2
3
4
5
6
7
8
9
1.500
10
0
1
2
3
4
IOUT (A)
LDO Bias, VDD = 5V, VOUT = 1.5V
1.530
7
8
9
10
External Bias, VDD = 3.3V, VOUT = 1.5V
1.525
1.525
VIN = 25V
VIN = 18V
1.520
Vout (V)
1.520
Vout (V)
6
Load Regulation vs. Temperature
Load Regulation
1.530
5
IOUT (A)
VIN = 12V
1.515
VIN = 12V TA = -40°C
VIN = 12V TA = 85°C
1.515
VIN = 5V TA = 85°C
1.510
1.510
VIN = 5V TA = -40°C
1.505
1.505
1.500
1.500
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
IOUT (A)
6
7
8
9
10
IOUT (A)
Load Regulation vs. Temperature
External Bias, VDD = 5V, VOUT = 1.5V
1.530
1.525
VIN = 12V TA = -40°C
VIN = 18V TA = -40°C
VIN = 25V TA = -40°C
VIN = 25V TA = 85°C
VIN = 18V TA = 85°C
VIN = 12V TA = 85°C
Vout (V)
1.520
1.515
1.510
1.505
1.500
0
1
2
3
4
5
IOUT (A)
6
7
8
9
10
8
SC9301
Typical Characteristics (continued)
Characteristics in this section are based upon using the Typical Application Circuit on page 6.
Start-up — Full Load
Shutdown — EN
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 10A
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 10A
VOUT
VOUT
(500mV/div)
(500mV/div)
EN
(5V/div)
(5V/div)
(10V/div)
EN
PGOOD
PGOOD
(5V/div)
(5V/div)
LX
LX
(10V/div)
Time (1ms/div)
Time (50μs/div)
Start-up — No Load
Steady State — No Load
VDD = 3.3V, VIN = 12V, VOUT = 1.5V, IOUT = 0A
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0A
VOUT
(500mV/div)
VOUT
EN
(5V/div)
(50mV/div)
PGOOD
(5V/div)
LX
LX
(10V/div)
(5V/div)
Time (1 ms/div)
Time (5μs/div)
Start-up — Prebias
Steady State — Full Load
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0A
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 10A
VOUT
(500mV/div)
EN
VOUT
(5V/div)
PGOOD
(50mV/div)
(5V/div)
LX
LX
(10V/div)
(10V/div)
Time (1ms/div)
Time (5μs/div)
9
SC9301
Typical Characteristics (continued)
Characteristics in this section are based upon using the Typical Application Circuit on page 6.
Transient Response
Protection — OCP then UV
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 9A to 0A to 9A
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 10A to 12A
540mV
VOUT
(50mV/div)
450mV
(500mV/div)
IOUT
(5A/div)
VOUT
FB
(200mV/div)
LX
IOUT
(5A/div)
(10V/div)
PGOOD
(5V/div)
Time (20μs/div)
Time (2ms/div)
Transient Response
Protection — OVP
VDD = 5V, VIN = 18V, VOUT = 1.5V, IOUT = 9A to 0A to 9A
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0A
VOUT
(500mV/div)
(200mV/div)
FB
VOUT
(50mV/div)
DL
IOUT
(5A/div)
(5V/div)
LX
Soft-Start
(5V/div)
(10V/div)
Time (20μs/div)
Protection: OCP, UVP then Hiccup
Time (50ms/div)
Start-up—Short & Over Current Protection
VIN = 12V, VOUT = 1.5V, IOUT = 5A to 12A
VIN = 12V, VOUT = 1.5V, IOUT = OC regulated at valley 10.2A
VOUT
IOUT
Inductor Current
(100mV/div)
Zoom-In Above
(500mV/div)
(5A/div)
(2V/div)
(5V/div)
(5A/div)
VOUT
(5A/div)
IOUT
Soft-Start
(5V/div)
LX
PGOOD
Time: Above (20ms/div), Bottom (1ms/div)
Time (500μs/div)
10
SC9301
Pin Descriptions
Pin #
Pin Name
Pin Function
1
FB
2
VOUT
Switcher output voltage sense pin.
3
VDD
Bias supply for the IC.
4, 30, PAD 1
AGND
Analog ground
5
VLDO
LDO output. Connect to VDD when using the internal LDO as a bias power supply.
6, 9-11,
PAD 2
VIN
Input supply voltage
7
SS
The soft-start ramp will be programmed by an internal current source charging a capacitor on this pin.
8
BST
Bootstrap pin — connect a capacitor of at least 100nF from BST to LXBST to develop the floating supply for
the high-side gate drive.
12
DH
High-side gate drive
13
LXBST
23-25, PAD 3
LX
Switching (phase) node
14
DL
Low-side gate drive
15-22
PGND
26
PGOOD
27
ILIM
Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LXS.
28
LXS
LX sense — connects to RILIM
29
EN
Enable input for the switching regulator — connect to AGND to disable the switching regulator, connect to
VDD or float to operate in forced continuous mode.
31
TON
On-time programming input — set the on-time by connecting through a resistor to AGND
32
ENL
Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic signal for logic control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
Feedback input for switching regulator used to program the output voltage — connect to an external resistor divider from VOUT to AGND.
LX Boost — connect to the BST capacitor.
Power ground
Open-drain power good indicator — high impedance indicates power is good. An external pull-up
resistor is required.
11
SC9301
Block Diagram
PGOOD
26
EN
VIN
29
A
VIN
VDD
VDD
Bootstrap
Switch
AGND
D
Control & Status
Reference
8
BST
12
DH
B
LX
13
LXBST
28
LXS
C
PGND
27
ILIM
14
DL
VDD
VIN UVLO
SS
FB
DL
High
MOSFET
Soft Start
7
Gate Drive
Control
On-- time
Generator
1
VDD
FB Comparator
TON
31
VOUT
2
DL
Valley Current Limit
VDD
VDD
VLDO
3
Low
MOSFET
VIN
VIN UVLO
5V
LDO
VIN UVLO
Detector
5
32
ENL
A = connected to pins 6, 9-11, PAD 2
B = connected to pins 23-25, PAD 3
C = connected to pins 15-22
D = connect to pins 4, 30, PAD 1
12
SC9301
Applications Information
Synchronous Buck Converter
The SC9301 is a step down synchronous DC-DC buck converter with integrated power MOSFETs and a 200mA
capable 5V LDO. The device is capable of 10A operation at
very high efficiency. A space saving 5x5 (mm) 32-pin
package is used. The programmable operating frequency
of up to 1MHz enables optimizing the configuration for
PCB area and efficiency.
The buck controller uses a pseudo-fixed frequency adaptive on-time control. This allows fast transient response
which permits the use of smaller output capacitors.
TON
VIN
VLX
CIN
Q1
VFB
FB Threshold
VLX
VOUT
L
Q2
ESR
FB
+
COUT
Input Voltage Requirements
The SC9301 requires two input supplies for normal operation: VIN and VDD. VIN operates over the wide range of 3V
to 28V. VDD requires a 3V to 5.5V supply which can be
from an external source or from the internal fixed 5V
LDO.
Power Up Sequence
When the SC9301 uses an external power source at the
VDD pin, the switching regulator initiates the start up
when VIN, VDD and EN are above their respective thresholds. When EN is at a logic high, VDD can be applied after
VIN rises. It is also recommended to use a10Ω resistor
between an external power source and the VDD pin. To
start up using the EN pin when both VDD and VIN are above
their respective thresholds, apply EN to enable the startup process. For SC9301 in self-biased mode, refer to the
LDO section for a full description.
Shutdown
The SC9301 can be shutdown by pulling either VDD or EN
below its threshold. When VDD is active and EN at low
logic, the output voltage discharges through an internal
FET.
Psuedo-fixed Frequency Adaptive On-time Control
The PWM control method used by the SC9301 is pseudofixed frequency, adaptive on-time, as shown in Figure 1.
The ripple voltage generated at the output capacitor ESR
is used as a PWM ramp signal. This ripple is used to trigger
the on-time of the controller.
Figure 1 — PWM Control Method, VOUT Ripple
The adaptive on-time is determined by an internal oneshot timer. When the one-shot is triggered by the output
ripple, the device sends a single on-time pulse to the highside MOSFET. The pulse period is determined by VOUT and
VIN. The period is proportional to output voltage and
inversely proportional to input voltage. With this adaptive
on-time configuration, the device automatically anticipates the on-time needed to regulate VOUT for the present
VIN condition and at the selected frequency.
The advantages of adaptive on-time control are:
•
•
•
•
•
Predictable operating frequency compared to
other variable frequency methods.
Reduced component count by eliminating the
error amplifier and compensation components.
Reduced component count by removing the
need to sense and control inductor current.
Fast transient response — the response time is
controlled by a fast comparator instead of a typically slow error amplifier.
Reduced output capacitance due to fast transient response.
One-Shot Timer and Operating Frequency
One-shot timer operation is shown in Figure 2. The FB comparator output goes high when VFB is less than the internal
600mV reference. This feeds into the DH gate drive and
turns on the high-side MOSFET, and also starts the one-shot
13
SC9301
Applications Information (continued)
timer. The one-shot timer uses an internal comparator and
a capacitor. One comparator input is connected to VOUT, the
other input is connected to the capacitor. When the ontime begins, the internal capacitor charges from zero volts
through a current which is proportional to VIN. When the
capacitor voltage reaches VOUT, the on-time is completed
and the high-side MOSFET turns off.
FB
VREF
FB Comparator
Gate
Drives
RTON _ MAX
VOUT Voltage Selection
The switcher output voltage is regulated by comparing
VOUT as seen through a resistor divider at the FB pin to the
internal 600mV reference voltage (see Figure 3).
VOUT
VIN
+
VOUT
VIN
One-Shot
Timer
RTON
DH
Q1
VLX
DL
Q2
ESR
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN.
Under steady-state conditions, the switching frequency
can be determined from the on-time by the following
equation.
VOUT
TON u VIN
The SC9301 uses an external resistor to set the on-time
which indirectly sets the frequency. The on-time can be
programmed to provide an operating frequency from
200kHz to 1MHz using a resistor between the TON pin and
ground. The resistor value is selected by the following
equation.
k
26.75pF u fSW
The constant, k, equals 1 when VDD is greater than 4.5V. If
VDD is less than 4.5V and VIN is greater than (VDD -1.8) x 10,
k is shown by the following equation.
k
R2
FB
Figure 2 — On-Time Generation
R TON
To FB pin
+
On-time = K x RTON x (VOUT/VIN)
fSW
R1
VOUT
L
COUT
VIN _ MIN
10 u 1.5PA
VDD 1.8 u 10
VIN
Figure 3 — Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC value of
VOUT is offset by the output ripple according to the following equation.
VOUT
§ R · §V
·
0.6 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸
R
2
©
¹
2 ¹
©
When a large capacitor is placed in parallel with R1 (CTOP)
VOUT is shown by the following equation.
VOUT
§
R · §V
·
0.6 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸ u
R
2
©
¹
2 ¹
©
1 (R1ȦCTOP )2
§ R u R1
·
1 ¨¨ 2
ȦCTOP ¸¸
© R 2 R1
¹
2
The switcher output voltage can be programmed higher
than 5V with careful design. In this case the VOUT pin
cannot connect directly to the switcher output due to its
the maximum voltage rating. An additional resistor
divider network is required to connect from the switcher
output to the VOUT pin. When the SC9301 operates from
an external 5V supply and the LDO is disabled by grounding the ENL pin, the voltage at the VOUT pin can be as
high as shown in the Recommended Operating Conditions.
Note that RTON must be adjusted higher by the same
divider ratio to maintain the desired on-time; on-time is
calculated according to the voltage at the VOUT pin.
The maximum RTON value allowed is shown by the following equation.
14
SC9301
Applications Information (continued)
Current Limit Protection
Forced Continuous Mode Operation
The SC9301 operates the switcher in FCM (Forced
Continuous Mode) as shown in Figure 4. In this mode one
of the power MOSFETs is always on, with no intentional
dead time other than to avoid cross-conduction. This
feature results in uniform frequency across the full load
range. DH is the gate signal to drive upper MOSFET. DL is
the lower gate signal to drive lower MOSFET.
FB Ripple
Voltage (VFB)
FB threshold
DC Load Current
Inductor
Current
On-time
(TON)
DH on-time is triggered when
VFB reaches the FB Threshold.
The device features programmable current limiting, which
is accomplished by using the RDSON of the lower MOSFET
for current sensing. The current limit is set by RILIM resistor.
The RILIM resistor connects from the ILIM pin to the LXS pin
which is also the drain of the low-side MOSFET. When the
low-side MOSFET is on, an internal ~9μA current flows
from the ILIM pin and through the RILIM resistor, creating a
voltage drop across the resistor. While the low-side
MOSFET is on, the inductor current flows through it and
creates a voltage across the RDSON. The voltage across the
MOSFET is negative with respect to ground. If this MOSFET
voltage drop exceeds the voltage across RILIM, the voltage
at the ILIM pin will be negative and current limit will activate. The current limit then keeps the low-side MOSFET on
and will not allow another high-side on-time, until the
current in the low-side MOSFET reduces enough to bring
the ILIM voltage back up to zero. This method regulates
the inductor valley current at the level shown by IOC in
Figure 5.
DL
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Inductor Current
DH
IPEAK
ILOAD
IOC
Figure 4 — Forced Continuous Mode Operation
Time
SmartDriveTM
For each DH pulse, the DH driver initially turns on the
high-side MOSFET at a slower speed, allowing a softer,
smooth turn-off of the low-side diode. Once the diode is
off and the LX voltage has risen 0.5V above PGND, the
SmartDrive circuit automatically drives the high-side
MOSFET on at a rapid rate. This technique reduces switching noise while maintaining high efficiency, reducing the
need for snubbers or series resistors in the gate drive.
Enable Input
The EN pin is used to enable or disable the switching regulator. When EN is low, the switching regulator is off and in
its lowest power state. When off, the output of the switching regulator soft-discharges the output into a 15Ω internal resistor via the VOUT pin.
Figure 5 — Valley Current Limit
Setting the valley current limit to 10A results in a peak
inductor current of 10A plus the peak-to-peak ripple
current. In this situation, the average (load) current
through the inductor is 10A plus one-half the peak-topeak ripple current.
The internal 9μA current source is temperature compensated at 4100ppm in order to provide tracking with the
RDSON.
The RILIM value is calculated by the following equations.
For VDD>4V; RILIM = 732 x IOC
For VDD<4V; RILIM = 834 x IOC
15
SC9301
Applications Information (continued)
When selecting a value for RILIM be sure not to exceed the
absolute maximum voltage value for the ILIM pin. Note
that because the low-side MOSFET with low RDSON is used
for current sensing, the PCB layout, solder connections,
and PCB connection to the LX node must be done carefully to obtain good results. RILIM should be connected
directly to LXS (pin 28).
Soft-Start of PWM Regulator
SC9301 has a programmable soft-start time that is controlled by an external capacitor at the SS pin. After the
controller meets both UVLO and EN thresholds, the controller has an internal current source of 3μA flowing
through the SS pin to charge the capacitor. During the
start up process (Figure 6), 40% of the voltage at the SS
pin is used as the reference for the FB comparator. The
PWM comparator issues an on-time pulse when the
voltage at the FB pin is less than 40% of the SS pin. As
result, the output voltage follows the SS start voltage. The
output voltage reaches and maintains regulation when
the SS pin voltage is > 1.5V. The time between the first LX
pulse and when VOUT meets regulation is the soft-start
time (tSS). The calculation for the soft-start time is shown
by the following equation.
t SS
CSS u 1.5 V
3PA
The voltage at the SS pin continues to ramp up and eventually is equal to 67% of VDD. After soft-start completes,
the FB pin voltage is compared to an internal reference of
600mV. The delay time between the VOUT regulation
point and PGOOD going high is shown by the following
equation.
t PGOOD
CSS § 2 u VIN
·
u¨
1 .5 V ¸
3PA © 3
¹
Figure 6 — Soft-start Timing Diagram
Pre-Bias Startup
SC9301 can start up as if in a soft-start condition with an
existing output voltage level. The soft-start time is still the
same as normal start up (when the output voltage starts
from zero). The output voltage starts to ramp up when
40% of the voltage at SS pin meets the pre-charge FB
voltage level. Pre-bias startup is achieved by turning off
the lower gate when the inductor current falls below zero.
This method prevents the output voltage from
decreasing.
Power Good Output
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the
FB pin is 10% below the nominal voltage, PGOOD is pulled
low. It remains low until the FB voltage returns above -8%
of nominal. During start-up PGOOD is held low and will
not be allowed to transition high until the PGOOD startup delay time has passed and soft-start is completed
(when VFB reaches 600mV).
PGOOD will transition low if the FB voltage exceeds +20%
of nominal (720mV), which is also the over-voltage shutdown threshold. PGOOD also pulls low if the EN pin is low
when VDD is present.
16
SC9301
Applications Information (continued)
Output Over-Voltage Protection
OVP (Over-voltage protection) becomes active as soon as
the device is enabled. The OVP threshold is set at 600mV
+ 20% (720mV). When VFB exceeds the OVP threshold, DL
latches high and the low-side MOSFET is turned on. DL
remains high and the controller remains off until the overvoltage condition is removed. At this point a hiccup delay
cycle initiates and the part will re-start. There is a 5μs
delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event.
circuitry and then the SC9301 begins the soft-start cycle.
The switcher will shut off if VDD falls below 2.4V.
LDO Regulator
When the LDO is providing bias power to the device, a
minimum 0.1μF capacitor referenced to AGND is required,
along with a minimum 1μF capacitor referenced to PGND
to filter the gate drive pulses. Refer to the PCB Layout
Guidelines section.
ENL Pin and VIN UVLO
Output Under-Voltage Protection
When VFB falls 25% below its nominal voltage (falls to
450mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tristate the MOSFETs and enters hiccup mode.
Hiccup Cycling and Automatic Fault Recovery
The SC9301 includes an automatic recovery feature
(hiccup mode upon fault). If the switcher output is shut
down due to a fault condition, the device will use the SS
capacitor as a timer. Upon fault shutdown the SS pin is
pulled low, and then will begin charging through the
internal 3μA current source. When the SS capacitor
reaches 67% of VDD, the SS pin is again pulled low, after
which the SS capacitor begins another charging cycle.
The SS capacitor will be used for 15 cycles of charging
from 0 to 67% of VDD. During this time, the switcher is off
and there is no MOSFET switching.
During the 16th SS cycle, a normal soft-start cycle is implemented and the MOSFETs will start a switching cycle.
Switching continues until the soft-start delay time is
reached. If the switcher output is still in a fault condition,
the switcher will shut down again and wait another fifteen
soft-start cycles before attempting the next soft-start.
The long delay between soft-start cycles reduce average
power loss in the power components.
The ENL pin also acts as the VIN under-voltage lockout for
the switcher. The VIN UVLO voltage is programmable via a
resistor divider at the VIN, ENL and AGND pins.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM
output turning off. If ENL goes below the VIN UVLO threshold and stays above 1V, then the switcher will turn off but
the LDO will remain on.
The next table summarizes the function of the ENL and EN
pins, with respect to the rising edge of ENL.
EN
ENL
LDO status
Switcher status
low
high
low
high
low
high
low, < 0.4V
low, < 0.4V
high, < 1.57V
high, < 1.57V
high, > 1.57V
high, > 1.57V
off
off
on
on
on
on
off
on
off
off
off
on
Figure 7 shows the ENL voltage thresholds and their effect
on LDO and Switcher operation.
VDD UVLO and POR
The VDD Under-Voltage Lock-Out (UVLO) circuitry inhibits
switching and tri-states the DH/DL drivers until VDD rises
above 2.5V. When VDD exceeds 2.5V, an internal POR
(Power-On Reset) resets the fault latch and the soft-start
17
SC9301
Applications Information (continued)
ENL voltage
VLDO
5V
LDO on
Switcher on if EN = high
4.5V
1.57V
voltage regulating with
200mA current limit
VIN UVLO hysteresis
1.57V
ENL low
threshold
(min 0.4V)
AGND
LDO on
Switcher off by VIN UVLO
increasing current
1.0V
20mA constant current
LDO off
Switcher on if EN = high
Figure 8 — LDO Start-Up
Figure 7 — ENL Thresholds
ENL Logic Control of PWM Operation
When the ENL input exceeds the VIN UVLO threshold of
1.57V, internal logic checks the PGOOD signal. If PGOOD
is high, the switcher is already running and the LDO will
start without affecting the switcher. If PGOOD is low, the
device disables PWM switching until the LDO output has
reached 90% of its final value. This delay prevents the
additional current needed by the DH and DL gate drives
from overloading the LDO at start-up.
Using the Internal LDO to Bias the SC9301
The following steps must be followed when using the
internal LDO to bias the device.
•
•
Connect VDD to VLDO before enabling the
LDO.
During the initial start-up the LDO, when the
LDO output is less than 1V, the external load
should not exceed 20mA. Above 1V, any external load on VLDO should not exceed 115mA
until the LDO voltage has reached 90% of final
value.
LDO Start-up
Before LDO start-up, the device checks the status of the
following signals to ensure proper operation can be
maintained.
1. ENL pin
2. VLDO output
3. VIN input voltage
When the ENL pin is high and VIN is available, the LDO will
begin start-up. During the initial phase, when VLDO is
below 1V, the LDO initiates a current-limited start-up
(typically 20mA). This protects the LDO from thermal
damage if the VLDO is shorted to ground. As VLDO exceeds
1V, the start-up current gradually increases to 115mA.
When VLDO reaches 4.5V, the LDO current limit is increased
to 200mA and the LDO output rises quickly to 5.0V. The
LDO start-up is shown in Figure 8.
18
SC9301
Applications Information (continued)
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor
ripple current must be specified.
k
26.75pF u fSW
RTON
Substituting for RTON results in the following solution.
The maximum input voltage (VINMAX) is the highest specified
input voltage. The minimum input voltage ( VINMIN) is determined by the lowest input voltage including the voltage
drops due to connectors, fuses, switches, and PCB traces.
The following parameters define the design.
•
•
•
•
Nominal output voltage (VOUT )
Static or DC output tolerance
Transient response
Maximum load current (IOUT )
There are two values of load current to evaluate — continuous load current and peak load current. Continuous
load current relates to thermal stresses which drive the
selection of the inductor and input capacitors. Peak load
current determines instantaneous component stresses and
filtering requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
The following values are used in this design.
•
•
•
•
VIN = 12V + 10% and LDO bias
VOUT = 1.5V + 3%
fSW = 300kHz
Load = 10A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the
power conversion efficiency.
The desired switching frequency is 300kHz which results
from using components selected for optimum size and
cost.
RTON = 124.6kΩ
Inductor Selection
In order to determine the inductance, the ripple current
must first be defined. Low inductor values result in smaller
size but create higher ripple current which can reduce
efficiency. Higher inductor values will reduce the ripple
current/voltage and for a given DC resistance are more
efficient. However, larger inductance translates directly
into larger packages and higher cost. Cost, size, output
ripple, and efficiency are all used in the selection process.
The ripple current will also set the boundary for powersave operation. The switching will typically enter powersave mode when the load current decreases to 1/2 of the
ripple current. For example, if ripple current is 4A then
Power-save operation will typically start for loads less than
2A. If ripple current is set at 40% of maximum load current,
then power-save will start for loads less than 20% of
maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25% to 50% of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the DH on-time, voltage across the inductor is
(VIN - VOUT ). The following equation for determining inductance is shown.
L
( VIN VOUT ) u TON
IRIPPLE
Example
A resistor, RTON is used to program the on-time (indirectly
setting the frequency) using the following equation.
In this example, the inductor ripple current is set equal to
35% of the maximum load current. Therefore ripple
current will be 35% x 10A or 3.5A. To find the minimum
inductance needed, use the VIN and TON values that correspond to VINMAX.
19
SC9301
Applications Information (continued)
T ON
V OUT
V INMAX u f SW
TON = 379 ns at 13.2VIN, 1.5VOUT, 300kHz
L
(13.2 1.5 ) u 379ns
3 .5 A
1.27PH
A slightly smaller value of 1.2μH is selected. This will
increase the maximum IRIPPLE to 3.7A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
25pF u R TON u VOUT
VINMIN
TON _ VINMIN
IRIPPLE
(10.8 1.5) u 451ns
3 .5 A
1.2PH
Capacitor Selection
The output capacitors are chosen based upon required
ESR and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal
to the valley of the output ripple plus 1/2 of the peak-topeak ripple. A change in the output ripple voltage will
lead to a change in DC voltage at the output.
The design goal for output voltage ripple is 2% of 1.5V or
30mV. The maximum ESR value allowed is shown by the
following equations.
ESRMAX
VRIPPLE
IRIPPLEMAX
COUTMIN
30mV
3 .7 A
1
§
·2
L¨ IOUT u IRIPPLEMAX ¸
2
©
¹
VPEAK VOUT 2
COUT
MIN
1
§
·2
1.2PH¨ 10 u 3.7 ¸
2
©
¹
2
2
1.65 1.5 357PF
During the load release time, the voltage cross the inductor is approximately -VOUT. This causes a down-slope or
falling di/dt in the inductor. If the load di/dt is not much
faster than the di/dt of the inductor, then the inductor
current will tend to track the falling load current. This will
reduce the excess inductive energy that must be absorbed
by the output capacitor, therefore a smaller capacitance
can be used.
The following can be used to calculate the needed capacitance for a given dILOAD/dt.
Peak inductor current is shown by the next equation.
ILPK = IMAX + 1/2 x IRIPPLEMAX
ILPK = 10 + 1/2 x 3.7 = 11.85A
Rate of change of Load Current
dlLOAD
dt
IMAX = maximum load release = 10A
ESRMAX = 8.1 mΩ
The output capacitance is usually chosen to meet transient requirements. A worst-case load release, from
maximum load to no load at the exact moment when
inductor current is at the peak, determines the required
2
Assuming a peak voltage VPEAK of 1.65V (150mV rise upon
load release), and a 10A load release, the required capacitance is shown by the next equation.
451ns
( VIN VOUT ) u TON
L
IRIPPLE _ VINMIN
capacitance. If the load release is instantaneous (load
changes from maximum to zero in < 1μs), the output
capacitor must absorb all the inductor’s stored energy.
This will cause a peak voltage on the capacitor according
to the following equation.
Lu
COUT
ILPK u
ILPK
I
MAX u dt
VOUT dlLOAD
2VPK VOUT 20
SC9301
Applications Information (continued)
lated unless it can be confirmed that double-pulsing
exists. Adding the C TOP capacitor will couple more ripple
into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor.
Example
dlLOAD
dt
2 .5 A
1Ps
This would cause the output current to move from 10A to
0A in 4μs, giving the minimum output capacitance
requirement shown in the following equation.
COUT
11.85 u
11.85 10
u 1Ps
1 .5
2 .5
21.65 1.5 1.2PH u
CTOP
VOUT
To FB pin
R1
R2
COUT = 216 μF
Note that COUT is much smaller in this example, 216μF
compared to 357μF based on a worst-case load release. To
meet the two design criteria of minimum 357μF and
maximum 8.1mΩ ESR, select one capacitor of 330μF and
6mΩ ESR.
It is recommended that an additional small capacitor be
placed in parallel with COUT in order to filter high frequency
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250ns minimum off-time has expired. In extreme cases
the noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation. This form of instability can usually be avoided by
providing the FB pin with a smooth, clean ripple signal
that is at least 10mVp-p, which may dictate the need to
increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout as discussed in the
Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a
small capacitor across the upper feedback resistor, as
shown in Figure 9. This capacitor should be left unpopu-
Figure 9 — Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
One simple way to solve this problem is to add trace resistance in the high current output path. A side effect of
adding trace resistance is decreased load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and discharging during the switching cycle. For most applications the minimum ESR ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching frequency. The formula for minimum ESR is shown by the
following equation.
21
SC9301
Applications Information (continued)
ESR MIN
3
2 u S u C OUT u f sw
When the system is using high ESR value capacitors, the
feedback voltage ripple lags the phase node voltage by 90
degrees. Therefore, the converter is easily stabilized.
When the system is using ceramic output capacitors, the
ESR value is normally too small to meet the above ESR criteria. As a result, the feedback voltage ripple is 180
degrees from the phase node and behaves in an unstable
manner. In this application it is necessary to add a small
virtual ESR network that is composed of two capacitors
and one resistor, as shown in Figure 10.
DCR
L
RL
+- D x VIN
VL
RL
L
Using Ceramic Output Capacitors
+-
VL
D x VIN
CL
DCR
FB
pin
COUT
R2
Vc L u
R1 // R2 u S u C C
R1 // R2 u S u C C 1
Figure 12 shows the magnitude of the ripple contribution
due to the output voltage ripple at the FB pin.
L
RL
Figure 10 — Virtual ESR Ramp Circuit
R2
It is shown by the following equation.
VFBc L
R1
R1
Figure 11 — FB Voltage by CL Voltage
CL
CC
FB
pin
CC
DCR
VOUT
VOUT
VL
CL
CC
R1
CC
R1
COUT
The ripple voltage at FB is a superposition of two voltage
sources: the voltage across CL and output ripple voltage.
They are defined in the following equations.
Vc L
'VOUT
IL u DCR(s u L / DCR 1)
S u RLCL 1
'IL
8C u fSW
Figure 11 shows the magnitude of the ripple contribution
due to CL at the FB pin.
R2
FB
pin
COUT
FB
pin
R2
Figure 12 — FB Voltage by Output Voltage
It is shown by the following equation.
VFB'VOUT
'VOUT u
R2
1
R1 //
R2
S u CC
The purpose of this network is to couple the inductor
current ripple information into the feedback voltage such
that the feedback voltage has 90 degrees phase lag to the
switching node similar to the case of using standard high
ESR capacitors. This is illustrated in Figure 13.
22
SC9301
Applications Information (continued)
VOUT
FB contribution by
output voltage ripple
LX
FB contribution
by CL
IL
Figure 13 — FB voltage in Phasor Diagram
The magnitude of the feedback ripple voltage, which is
dominated by the contribution from CL , is controlled by
the value of R1, R2 and CC . If the corner frequency of (R1//
R2) x CC is too high, the ripple magnitude at the FB pin will
be smaller, which can lead to double-pulsing. Conversely,
if the corner frequency of (R1// R2) x CC is too low, the ripple
magnitude at FB pin will be higher. Since the SC9301
regulates to the valley of the ripple voltage at the FB pin,
a high ripple magnitude is undesirable as it significantly
impacts the output voltage regulation. As a result, it is
desirable to select a corner frequency for (R1// R2) x CC to
achieve enough, but not excessive, ripple magnitude and
phase margin. The component values for R1, R2, and CC
should be calculated using the following procedure.
Select CL (typical 10nF) and RL to match with L and DCR
time constant using the following equation.
L
DCR u CL
Select CC by using the following equation.
CC |
The duty-factor limitation is shown by the following
equation.
DUTY
Combined FB
RL
low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times.
1
3
u
R1 // R 2 2 u S u fsw
The resistor values (R1 and R2) in the voltage divider circuit
set the VOUT for the switcher. The typical value for CC is
from 10pF to 1nF.
Dropout Performance
The output voltage adjust range for continuous-conduction operation is limited by the fixed 250ns (typical)
minimum off-time of the one-shot. When working with
TON(MIN)
TON(MIN) TOFF(MAX )
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static conditions it trips when the feedback pin is 600mV, + 1%.
The on-time pulse from the SC9301 in the design example
is calculated to give a pseudo-fixed frequency of 250kHz.
Some frequency variation with line and load is expected.
This variation changes the output ripple voltage. Because
adaptive on-time converters regulate to the valley of the
output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the output ripple is 50mV with
VIN = 6 volts, then the measured DC output will be 25mV
above the comparator trip point. If the ripple increases to
80mV with VIN = 25V, then the measured DC output will be
40mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple.
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at
full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps
are reduced as seen at the load.
The use of 1% feedback resistors contributes up to 1%
error. If tighter DC accuracy is required, 0.1% resistors
should be used.
23
SC9301
Applications Information (continued)
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor effect on the DC output voltage. The output ESR
also affects the output ripple and thus has a minor effect
on the DC output voltage.
PCB Layout Guidelines
Switching Frequency Variations
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
The switching frequency will vary depending on line and
load conditions. The line variations are a result of fixed
propagation delays in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
VIN increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net effect is
that frequency tends to falls slightly with increasing input
voltage.
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. A adaptive on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from VIN as losses increase). Because the on-time is
essentially constant for a given VOUT/VIN combination, to
offset the losses the off-time will reduce slightly as load
increases. The net effect is that switching frequency
increases slightly with increasing load.
The optimum layout for the SC9301 is shown in Figure 16.
This layout shows an integrated FET buck regulator with a
maximum current of 10A. The total PCB area is approximately 25 x 29 mm with single side components.
•
•
•
•
•
•
•
IC Decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
CSS
BST, ILIM, and LX
CIN and COUT placement and Current Loops
IC Decoupling Capacitors
A 1 μF capacitor must be located as close as possible to the IC and directly connected to pins 3
(VDD) and 4 (AGND).
Another 1 μF capacitor must be located as close
as possible to the IC and directly connected to
pins 3 (VDD) and PGND plane.
•
•
PGND Plane
PGND requires its own copper plane with no
other signal traces routed on it.
Copper planes, multiple vias and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the IC.
The PGND copper area between the input
capacitors, output capacitors and PGND pins
must be as tight and compact as possible to
reduce the area of the PCB that is exposed to
noise due to current flow on this node.
AGND Island
AGND should have its own island of copper with
no other signal traces routed on this layer that
connects the AGND pins and pad of the IC to the
analog control components.
All of the components for the analog control circuitry should be located so that the connections
to AGND are done by wide copper traces or vias
down to AGND.
•
•
•
•
•
24
SC9301
Applications Information (continued)
•
Connect PGND to AGND with a short trace or 0Ω
resistor. This connection should be as close to
the IC as possible.
FB, VOUT, and Other Analog Control Signals
The connection from the V OUT power to the
analog control circuitry must be routed from the
output capacitors and located on a quiet layer.
The traces between Vout and the analog control
circuitry (VOUT, and FB pins) must be wide, short
and routed away from noise sources, such as
BST, LX, VIN, and PGND between the input
capacitors, output capacitors, and the IC.
The feedback components for the switcher and
the LDO need to be as close to the FB and FBL
pins of the IC as possible to reduce the possibility of noise corrupting these analog signals.
•
•
•
BST, ILIM,TON,SS and LX
The connections for the boost capacitor
between the BST and LXBST must be short, wide
and directly connected.
ILIM and TON nodes must be as short as possible
to ensure the best accuracy in current limit and
on time.
RILIM should be close to the IC and connected
between LXS (pin 28) and ILIM (pin 27) only.
RTON should be close to the IC and connected
between TON (pin 31) and AGND (pin 30).
CSOFT should be close to the IC and kept away
from the boost capacitor. Connect the AGND
end of CSOFT to the AGND plane at pin 4.
The LX node between the IC and the inductor
should be wide enough to handle the inductor
current and short enough to eliminate the possibility of LX noise corrupting other signals.
Multiple vias should be used on the LX PAD to
provide good thermals and connection to an
internal or bottom layer LX plane.
•
•
•
•
•
•
•
Capacitors and Current Loops
Figure 14 shows the placement of input/output
capacitors and inductor. This placement shows
the smallest current loops between the input/
output capacitors, the SC9301 and the inductor
to reduce the IR drop across the copper.
•
25
SC9301
Applications Information (continued)
IC with vias for
LX, AGND, VIN
VDD Decoupling Capacitor
RTON
AGND plane on
inner layer
Css
CBST
Vout sense trace
on inner layer
L
VDD
RFB2
RFB1
CTOP
RILIM
Pin 1 marking
CIN
CIN
LX plane on top and
bottom layer
VOUT Plane on top
and bottom layer
SP or
POSCAP
COUT
PGND on inner
or bottom layer
Cer.
RGND — AGND connects to VIN plane on
top and/or
PGND close to IC
bottom layer
PGND on top
layer
Figure 14 — PCB Layout
26
SC9301
Outline Drawing — MLPQ-UT32 5x5
DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
.039 0.80
.031
1.00
A
.002 0.00
0.05
A1 .000
(.008)
(0.20)
A2
b
.007 .010 .012 0.18 0.25 0.30
D
.193 .197 .201 4.90 5.00 5.10
D1 .076 .078 .080 1.92 1.97 2.02
E
.193 .197 .201 4.90 5.00 5.10
E1 .135 .137 .139 3.43 3.48 3.53
e
.020 BSC
0.50 BSC
L
.012 .016 .020 0.30 0.40 0.50
32
32
N
aaa
.003
0.08
.004
bbb
0.10
B
D
A
PIN 1
INDICATOR
(LASER MARK)
E
A2
A
aaa
SEATING
PLANE
C
C
A1
3.48
D1
0.76
1.05
LxN
1.49
E1
3.61
1.66
2
1
0.76
N
R0.20
PIN 1
IDENTIFICATION
bxN
e
bbb
C A
B
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
27
SC9301
Land Pattern — MLPQ-UT32 5x5
3.48
K1
K
DIMENSIONS
1.74
H2
1.74
(C)
H
3.61
G
Z
H1
Y
X
P
DIM
INCHES
MILLIMETERS
C
(.195)
(4.95)
G
.165
4.20
H
.137
3.48
H1
.059
1.49
H2
.065
1.66
K
.078
1.97
K1
.041
1.05
P
.020
0.50
X
.012
0.30
Y
.030
0.75
Z
.224
5.70
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS.
28
SC9301
© Semtech 2011
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Contact Information
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Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
29