SC417/SC427

SC417/SC427
10A EcoSpeedTM Integrated FET
Regulator with Programmable LDO
POWER MANAGEMENT
Features







Description
Power system:
Input voltage — 3V to 28V
Integrated bootstrap switch
Programmable LDO output — 200mA
1% reference tolerance -40 to +85 °C
Selectable internal/external bias power supply
EcoSpeedTM architecture with pseudo-fixed frequency adaptive on-time control
Logic input/output control
Independent control EN for LDO and switcher
Programmable VIN UVLO threshold
Power good output
Selectable ultrasonic/power save methods
Protections
Over-voltage/under-voltage
TC compensated RDS(ON) sensed current limit
Thermal shutdown
Output capacitor types
High ESR — SP, POSCAP, OSCON
Ceramic capacitors
Package — 5x5mm, 32-pin MLPQ
Lead-free and halogen free
RoHS and WEEE compliant
The SC417/SC427 is a stand-alone synchronous
EcoSpeedTM buck regulator which incorporates Semtech’s
advanced, patented adaptive on-time control architecture
to provide excellent light-load efficiency and fast transient
response. It features integrated power MOSFETs, a bootstrap switch, and a programmable LDO in a 5x5mm
package. The device is highly efficient and uses minimal
15x20mm PCB area for a total converter solution. Refer to
page 16 for information on the C-SIM simulation tool.
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The SC417/SC427 supports using standard capacitor types
such as electrolytic or special polymer, in addition to
ceramic, at switching frequencies up to 1MHz. The programmable frequency, synchronous operation, and selectable power-save provide high efficiency operation over a
wide load range. In power-save mode, the minimum operating frequency for the SC417 is 25kHz whereas the SC427
has no minimum.
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Additional features include internal soft-start, programmable cycle-by-cycle over-current limit protection, under
and over-voltage protections and soft shutdown. The
device also provides separate enable inputs for the PWM
controller and LDO as well as a power good output for the
PWM controller.
Applications
Office automation and computing
 Networking and telecommunication equipment
 Point-of-load power supplies and module replacement.

The wide input voltage range, programmable frequency,
and programmable LDO make the device extremely flexible
and easy to use in a broad range of applications. Support is
provided for single cell or multi-cell battery systems in addition to traditional DC power supply applications.
Typical Application Circuit
E N A B LE /P S A V E
ENL
E N A B LE LD O
E N /P S V
R ILIM
LX S
ILIM
VOUT
RTO N
LX
V5V
V E X T /LD O
S C 4 1 7 /S C 4 2 7
1µF
V IN
V IN
C IN
VOUT
L1
RFB1
+
COUT
FB
BST
RFB2
LX B S T
AGND
PGND
CBST
Rev 2.0
PGOOD
PGOOD
TO N
US Patent: 7,714,547 B2
© 2015 Semtech Corporation
SC417/SC427
5
V IN
6
VLD O
7
BST
8
E N /P S V
IL IM
PGOOD
LX
AGND
LXS
TON
25
AGND
PAD 1
LX
PAD 3
V IN
PAD 2
9
10
11
12
13
14
15
16
PGND
VOUT
26
PGND
4
27
DL
AGND
28
DH
3
29
T o p V ie w
LXBST
V5V
30
V IN
2
31
V IN
FBL
32
Ordering Information
V IN
FB
1
ENL
Pin Configuration
Device
Package
SC417MLTRT(1)(2)
MLPQ-32 5X5
SC427MLTRT(1)(2)
MLPQ-32 5X5
LX
SC417MLTRC
(1)(2)(3)
MLPQ-32 5X5
LX
SC427MLTRC (1)(2)(3)
MLPQ-32 5X5
SC417EVB
Evaluation Board
SC427EVB
Evaluation Board
24
23
22
PGND
21
PGND
20
PGND
19
PGND
18
PGND
17
PGND
Notes:
1) Available in tape and reel only. A reel contains 3000 devices.
2) Pb-free, Halogen free, and RoHS/WEEE compliant.
3) Device has copper bond wires.
SC417 and SC427
MLPQ-32; 5x5, 32 LEAD
Marking Information
SC417
yyw w #
xxxxxx
xxxxxx
SC427
yyw w #
xxxxxx
xxxxxx
yyww = Date Code
xxxxxx = Semtech Lot Number
xxxxxx = Semtech Lot Number
# = Copper Bond Wire (SC417MLTRC only)
yyww = Date Code
xxxxxx = Semtech Lot Number
xxxxxx = Semtech Lot Number
# = Copper Bond Wire (SC427MLTRC only)
SC417/SC427
Absolute Maximum Ratings
Recommended Operating Conditions
LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30
Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28
LX to PGND (V) (transient — 100ns max.) . . . . . . . -2 to +30
V5V to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5
VIN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30
VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to 5.5
EN/PSV, PGOOD, ILIM, to GND (V). . . . . . -0.3 to +(V5V + 0.3)
Thermal Information
VOUT, VLDO, FB, FBL, to GND (V). . . . . . . . -0.3 to +(V5V + 0.3)
V5V to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6
Storage Temperature (°C). . . . . . . . . . . . . . . . . . . . . -60 to +150
TON to PGND (V). . . . . . . . . . . . . . . . . . . . . . -0.3 to +(V5V - 1.5)
Maximum Junction Temperature (°C). . . . . . . . . . . . . . . 1 5 0
ENL (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN
Operating Junction Temperature (°C). . . . . . -40 to +125
BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
Thermal resistance, junction to ambient (2) (°C/W)
BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35
High-side MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AGND to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3
Low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
PWM controller and LDO thermal resistance . . . . . . 50
Peak IR Reflow Temperature (°C). . . . . . . . . . . . . . . . . . . . . 260
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless specified: VIN =12V, TA = +25°C for Typ, -40 to +85 °C for Min and Max, TJ < 125°C, V5V = +5V, Typical Application Circuit
Parameter
Conditions
Min
Typ
Max
Units
3
28
V
4.5
5.5
V
Input Supplies
Input Supply Voltage
V5V Voltage
Sensed at ENL pin, rising edge
2.40
2.60
2.95
Sensed at ENL pin, falling edge
2.23
2.40
2.57
VIN UVLO Threshold(1)
VIN UVLO Hysteresis
V
EN/PSV = High
0.2
V
Measured at V5V pin, rising edge
3.7
3.9
4.1
Measured at V5V pin, falling edge
3.5
3.6
3.75
V5V UVLO Threshold
V
V5V UVLO Hysteresis
VIN Supply Current
0.3
ENL , EN/PSV = 0V, VIN = 28V
8.5
Standby mode; ENL=V5V, EN/PSV = 0V
130
V
20
μA
SC417/SC427
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
ENL , EN/PSV = 0V
3
7
μA
SC417, EN/PSV = V5V, no load (fSW = 25kHz),
VFB > 500mV(2)
2
SC427, EN/PSV = V5V, no load, VFB > 500mV(2)
0.7
fSW = 250kHz, EN/PSV = floating , no load(2)
10
Input Supplies (continued)
V5V Supply Current
FB On-Time Threshold
Static VIN and load, 0 to +85 °C
0.496
Static VIN and load, -40 to +85 °C
Continuous mode operation
0.500
mA
0.504
V
0.495
0.505
V
200
1000
Frequency Range
kHz
Minimum fSW, (SC417 only), EN/PSV = V5V, no load
25
Bootstrap Switch Resistance
10
Ω
Timing
On-Time
Continuous mode operation,
VIN = 15V, VOUT = 5V, fSW= 300kHz, RTON = 133kΩ
999
1110
1220
ns
Minimum On-Time (2)
80
ns
Minimum Off-Time (2)
250
ns
850
μs
500
kΩ
Soft-Start
Soft-Start Ramp Time (2)
Analog Inputs/Outputs
VOUT Input Resistance
Current Sense
Zero-Crossing Detector Threshold
LX - PGND
-3
0
+3
mV
Power Good
Upper limit, VFB > internal 500mV reference
+20
%
Lower limit, VFB < internal 500mV reference
-10
%
Start-Up Delay Time
2
ms
Fault (noise immunity) Delay Time(2)
5
µs
Power Good Threshold
Leakage
Power Good On-Resistance
1
10
µA
Ω
SC417/SC427
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
RILIM = 5.9k Ω
6
8
10
A
Fault Protection
Valley Current Limit
ILIM Source Current
ILIM Comparator Offset
10
With respect to AGND
-10
0
μA
+10
mV
Output Under-Voltage Fault
VFB with respect to internal 500mV reference,
8 consecutive clocks
-25
%
Smart Power-save Protection Threshold (2)
VFB with respect to internal 500mV reference
+10
%
Over-Voltage Protection Threshold
VFB with respect to internal 500mV reference
+20
%
5
μs
150
°C
Over-Voltage Fault Delay(2)
Over-Temperature Shutdown(2)
10°C hysteresis
Logic Inputs/Outputs
Logic Input High Voltage
ENL
Logic Input Low Voltage
ENL
EN/PSV Input for PSAVE Operation (2)
V5V = 5V
EN/PSV Input for Forced Continuous Operation (2)
1.0
V
0.4
V
2.2
5
V
1
2
V
0.4
V
+10
μA
18
μA
+1
μA
EN/PSV Input for Disabling Switcher (2)
EN/PSV Input Bias Current
ENL Input Bias Current
FBL, FB Input Bias Current
EN/PSV= V5V or AGND
-10
VIN = 28V
FBL, FB = V5V or AGND
11
-1
SC417/SC427
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
VLDO load = 10mA
0.735
0.75
0.765
V
Linear Regulator (LDO)
FBL Accuracy
LDO Current Limit
Start-up and foldback, VIN = 12V
Operating current limit, VIN = 12V
85
mA
135
200
VLDO to VOUT Switch-over Threshold (3)
-140
+140
mV
VLDO to VOUT Non-switch-over Threshold (3)
-450
+450
mV
VLDO to VOUT Switch-over Resistance
LDO Drop Out Voltage (4)
VOUT = +5V
2
Ω
From VIN to VVLDO, VVLDO = +5V, IVLDO = 100mA
1.2
V
Notes:
(1) VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
(2) Guaranteed by design.
(3) The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures
that VLDO will not switch-over to VOUT.
(4) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point.
SC417/SC427
Detailed Application Circuit
E N A B LE
LD O
E N A B LE /
PSAVE
PGOOD
R IL IM
10KΩ
RLDO 1
5 7 .6 K Ω
S C 417 /S C 427
1 µF
PAD 2
CBST
1 µF
V IN
+ 12 V
V IN
1 µF
FB
FBL
V5V
AGND
VOUT
V IN
V LD O
BST
V IN
RLDO 2
10KΩ
AGND
LX
LX
PGND
PGND
PGND
PGND
PGND
PGND
V IN
V IN
DH
LX B S T
DL
PGND
PGND
1
2
3
4
5
6
7
8
ENL
TON
AGND
E N /P S V
LX S
ILIM
PGOOD
LX
PAD 1
V 5 V is tie d to V L D O
LX
24
23
22
21
20
19
18
17
PAD 3
9
10
11
12
13
14
15
16
N o te :
32
31
30
29
28
27
26
25
RTO N
1 5 4K Ω
C IN
4 x 1 0 µF
(se e n o te)
RGND
0
1.05 V @ 10 A , 250 kH z
L1
0 .8 8 µH
CFF
100pF
COUT1
2 2 0 µF
15m Ω
RFB1
11KΩ
+
CO UT2
2 2 0µF
15m Ω
+
VOUT
10nF
RFB2
10KΩ
K ey C o m p o n en ts
C o m p o n en t
V alu e
M an u factu rer
P art N u m b er
W eb
C IN
4 x 10 µF /25 V
M urata
G R M 32 D R 71 E 106 K A 12 L
w w w .m urata.com
C O U T 1,2 (option 1)
2 x 220 µF /15m Ω
P anasonic
E E F U E 0 J221 R
w w w .panasonic .com
C O U T 1,2 (option 2)
330 µF /9m Ω
P anasonic
E E F -S X 0E 331 E R
w w w .panasonic .com
L1 (option 1)
0.88 µH /2.3m Ω
N E C -T okin
M P C 1040 LR 88 C
w w w .nec-tokin.com
L1 (option 2)
1.0µH /2.3m Ω
V ishay
IH LP 4040 D Z E R 1R 0M 11
w w w .vishay .com
A ll other sm all signal com ponents (resistors and capacitors ) are standard S M T devices .
N O T E : T he quantity of 10µF input capacitors required varies w ith the application requirem ents .
SC417/SC427
Typical Characteristics
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
SC417 Efficiency/Power Loss — PSAVE vs. FCM
2 .2 5
95
2 .0 0
90
85
1 .7 5
85
80
1 .5 0
E fficien cy (% )
1 2 V IN
6 V IN
90
E fficie n cy
1 9 V IN
75
1 .2 5
P o w e r L o ss
70
65
1 2 V IN
6 V IN
60
1 .0 0
55
50
1 9 V IN
0
1
2
3
4
5
I O U T (A )
6
7
8
9
10
E xte rn a l b ia se d : V 5 V = 5 V , V O U T = 1 .0 5 V
1 2 V IN
0 .5 0
60
0 .2 5
55
0 .0 0
50
E fficie n cy
90
E ffic ie n c y (% )
1 9 V IN
80
1 .5 0
75
70
1 .0 0
P o w e r L o ss
65
1 2 V IN
1 9 V IN
60
100
0
2
3
4
5
I O U T (A )
6
7
8
9
10
6 V IN
E fficie n cy
85
1 9 V IN
80
1 2 V IN
60
1 9 V IN
55
6 V IN
0
1
2
3
4
5
I O U T (A )
6
7
8
9
10
8
9
10
-0 .0 2 5
0 .2 2 5
0 .1 2 5
75
70
2 .5 0
100
2 .2 5
95
2 .0 0
90
1 .7 5
85
1 .0 0
P o w e r L o ss
65
7
0 .0 7 5
0 .0 2 5
P o w e r L o ss F C M -P S M
0
1
2
3
4
5
I O U T (A )
6
7
8
9
10
-0 .0 2 5
SC417 Efficiency/Power Loss — FCM
1 .2 5
70
I O U T (A )
6
FCM
80
50
0 .0 0
1 .5 0
75
5
65
E ffic ie n c y (% )
1 2 V IN
4
0 .1 7 5
60
P o w e r L o s s (W )
E xte rn a l b ia se d: V 5 V = 5V , V O U T = 1 .0 5V
90
E ffic ie n cy (% )
3
PSM
85
0 .5 0
6 V IN
1
95
50
2
E xte rn a l b ia se d : V 5 V = 5 V , V IN = 1 2 v, V O U T = 1 .0 5 V
SC417 Efficiency/Power Loss vs. Load — FCM
100
1
55
0
0 .0 2 5
P o w e r L o ss F C M -P S M
90
55
50
0 .0 7 5
95
2 .0 0
85
0 .1 2 5
SC417 Efficiency/Power Loss — PSAVE vs. FCM
E ffic ie n c y (% )
6 V IN
FCM
70
65
P o w e r L o s s (W )
95
0 .1 7 5
75
0 .7 5
2 .5 0
0 .2 2 5
PSM
80
SC417 Efficiency/Power Loss vs. Load — PSAVE Mode
100
In te rn a l b ia se d: V L D O = 5 V , V IN = 1 2 v, V O U T = 1 .0 5 V
D elta P o w e r L o s s (W )
95
E ffic ie n cy (% )
100
P o w er L o ss (W )
2 .5 0
V IN = 1 2 v, V O U T = 1 .0 5 V
0 .1 4
E xte rn a l B ia s
0 .1 2
In te rn a l B ia s
80
0 .1 0
P o w e r L o ss F C M -P S M
75
70
0 .7 5
65
0 .5 0
60
0 .2 5
55
0 .0 0
50
0 .0 8
D e lta P o w e r L o s s (W )
In te rn a l b ia se d: V L D O = 5 V , V O U T = 1.0 5 V
100
D e lta P o w e r L o s s (W )
SC417 Efficiency/Power Loss vs. Load — PSAVE Mode
0 .0 6
0
1
2
3
4
5
I O U T (A )
6
7
8
9
10
0 .0 4
SC417/SC427
Typical Characteristics (continued)
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
SC427 Efficiency/Power Loss vs. Load — FCM
6 V IN
90
E fficie n cy
E ffic ie n cy (% )
85
1 9V IN
80
2 .2 5
95
2 .0 0
90
1 .7 5
85
1 .5 0
75
1 .2 5
70
1 .0 0
P o w e r L o ss
65
1 2V IN
60
1 9V IN
55
50
100
6 V IN
0
1
2
3
4
5
I O U T (A )
6
7
8
9
10
E xternal biased : V 5 V = 5 V , V O U T = 1 .05 V
80
SC427
80
SC417
E fficie n c y (% )
70
65
60
0 .2 5
55
0 .0 0
50
100
0.0 2 2
95
0.0 1 9
90
0.0 1 6
85
0.0 1 3
50
0.0 1 0
40
0.0 0 7
30
0.0 0 4
P o w e r L o ss S C 4 1 7 – S C 4 2 7
1 .25
P ow er Loss
0
1
50
0 .1 6
0 .1 8
0 .2 0 0 .2 2
I O U T (A )
6
7
8
9
10
0 .00
0 .1 5
0 .1 4
0 .1 3
In te rn a l B ia s
0 .1 2
0 .0 8
P o w e r L o ss: In te rn a l-E xte rn a l B ia se d
0 .0 7
0 .0 6
0
1
2
3
4
5
I O U T (A )
6
7
8
9
10
0 .0 5
SC427 Load Regulation —PSAVE Mode
E xte rn a l b ia se d ; V 5 V = 5 V , V O U T = 1 .0 5 V
1 .0 8
E xte rn a l b ia se d; V 5 V = 5 V , V O U T = 1 .0 5V
1 .0 7
1.0 7
19V
1.0 6
1 .0 6
19V
V O U T (V )
V o u t (V )
12V
6V
1.0 5
12V
6V
1 .0 5
1 .0 4
1.0 4
1.0 3
5
E xte rn a l B ia s
SC417 Load Regulation —PSAVE Mode
1.0 8
4
V IN = 1 2 V , V O U T = 1 .0 5 V
65
-0 .0 0 5
0 .1 4
3
0 .0 9
55
0 .1 0 0 .1 2
I O U T (A )
2
0 .1 0
-0 .0 0 2
0 .0 8
0 .25
6 V IN
70
10
0.0 6
0 .50
19V IN
75
60
0 .0 4
0 .75
12V IN
0 .1 1
0.0 0 1
0 .0 2
1 .00
80
20
0
0 .0 0
1 .50
SC427 Efficiency/Power Loss — FCM
0.0 2 5
60
1 .75
70
0 .5 0
E ffic ie n c y (% )
90
2 .00
75
0 .7 5
D e lta P o w e r L o s s (W )
E xte rn a l B ia se d: V 5V = 5V , V O U T = 1 .0 5V
2 .25
E fficiency
19V IN
SC417 vs. SC427 Efficiency/Power Loss — PSAVE Mode
100
12V IN
6 V IN
2 .50
D e lta P o w e r L o ss (W )
1 2V IN
95
2 .5 0
E ffic ie n c y (% )
E xte rn a l b ia se d : V 5 V = 5 V , V O U T = 1 .0 5 V
P o w e r L o s s (W )
100
P o w er L o s s (W )
SC427 Efficiency/Power Loss vs. Load — PSAVE Mode
N o te: M e a su re d V O U T = 1 .0 5V p lu s ½ o f o u tp u t rip p le vo lta g e
0
2
4
I O U T (A )
6
8
10
1 .0 3
N o te: M e a su re d V O U T = 1.0 5 V p lu s ½ o f o u tp u t rip p le vo lta g e
0
2
4
I O U T (A )
6
8
10
SC417/SC427
Typical Characteristics (continued)
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
SC417 Load Regulation —FCM
1 .08
SC427 Load Regulation —FCM
E xternal biased; V 5V = 5V , V O U T = 1 .05V
1 .07
1.0 8
1.0 7
19V
12V
1 .06
1.0 6
N ote: M easured V O U T = 1 .05 V plus ½ of output ripple voltage
0
2
4
I O U T (A )
6
8
1.0 3
10
E xte rn a l b ia se d ; V 5 V = 5 V , V O U T = 1.0 5 V , V IN = 1 2V
350
300
250
PSM
200
150
100
50
0
2
4
I O U T (A )
6
8
6
8
10
FCM
250
200
PSM
150
100
0
10
0
2
4
I O U T (A )
6
8
10
SC427 VOUT Ripple —FCM vs. PSAVE Mode
E xternal biased ; V 5 V = 5 V , V O U T = 1 .05 V , V IN = 12 V
0 .0 4 0
E xte rn a l b ia se d ; V 5 V = 5 V , V O U T = 1.0 5 V , V IN = 1 2V
0 .0 3 5
V O U T R ip p le (V )
V O U T R ip p le (V )
I O U T (A )
50
0 .035
PSM
0 .030
PSM
FCM
0 .0 3 0
FCM
0 .025
0 .020
4
E xte rn a l b ia se d ; V 5 V = 5 V , V O U T = 1 .0 5 V , V IN = 1 2 V
SC417 VOUT Ripple —FCM vs. PSAVE Mode
0 .040
2
300
FCM
S w itc h in g F re q u en c y (k H z)
S w itc h in g F re q u e n c y (k H z)
N o te : M e a su re d V O U T = 1.0 5 V p lu s ½ o f o u tp u t rip p le vo lta g e
0
SC427 Switching Freq. — FCM vs. PSAVE Mode
SC417 Switching Freq. — FCM vs. PSAVE Mode
0
6V
1.0 4
1 .04
350
12V
1.0 5
1 .05
1 .03
19V
V O U T (V )
V O U T (V )
6V
E xte rn a l b ia se d ; V 5 V = 5 V , V O U T = 1 .0 5 V
0 .0 2 5
0
2
4
I O U T (A )
6
8
10
0 .0 2 0
0
2
4
I O U T (A )
6
8
10
10
SC417/SC427
Typical Characteristics (continued)
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
Ultrasonic Powersave Mode — No Load (SC417)
VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
Δ V ~ 29mV
1.073V
(50mV/div)
1.044V
(10V/div)
f=26.22kHz
(10V/div)
(5V/div)
Time (10µ������
s�����
/div)
Forced Continuous Mode — No Load
Self-Biased Start-Up — Power Good True
VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = ENL = 5V, EN/PSV= float
VIN = 0V to 12V step, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
1.078V
Δ V ~ 30mV
(50mV/div)
(10V/div)
1.048V
1.05V
f=227.4kHz
(10V/div)
ΔV/ΔT ~
(500mV/div)
(2V/div)
1.4 V/ms
0V
(10V/div)
(5V/div)
(5V/div)
Time (2µ������
s�����
/div)
Time (400µ������
s�����
/div)
Enabled Loaded Output — Full Scale
Enabled Loaded Output — Power Good True
VIN = 12V, VOUT = 1.05V, IOUT = 1A, VLDO = V5V = ENL = 5V. EN/PSV= 5V
VIN = 12V, VOUT = 1.05V, IOUT = 1A, VLDO = V5V = ENL = 5V. EN/PSV= 5V
1.05V
1.05V
ΔV/ΔT ~
(50mV/div)
0V
1.4V/ms
(500mV/div)
(10V/div)
(10V/div)
(5V/div)
(5V/div)
Time (100µ������
s�����
/div)
0V
~2ms
Time (400µ������
s�����
/div)
11
SC417/SC427
Typical Characteristics (continued)
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
Transient Response — Load Rising (SC417)
VIN = 12V, VOUT = 1.05V, IOUT = 0A to 10A, VLDO = V5V = EN/PSV= ENL = 5V
Transient Response — Load Falling (SC417)
VIN = 12V, VOUT = 1.05V, IOUT = 10A to 0A, VLDO = V5V = EN/PSV= ENL = 5V
1.101V
1.063V
(50mV/div)
(50mV/div)
1.055V
1.025V
(10V/div)
(10V/div)
(10A/div)
(10A/div)
(5V/div)
(5V/div)
Time (10µ������
s�����
/div)
Time (10µ������
s�����
/div)
Transient Response — Load Rising (SC427)
VIN = 12V, VOUT = 1.05V, IOUT = 0A to 10A, VLDO = V5V = EN/PSV= ENL = 5V
Transient Response — Load Falling (SC427)
VIN = 12V, VOUT = 1.05V, IOUT = 10A to 0A, VLDO = V5V = EN/PSV= ENL = 5V
(50mV/div)
(50mV/div)
(10V/div)
(10V/div)
(5A/div)
(5A/div)
(5V/div)
(5V/div)
Time (10µ������
s�����
/div)
Time (10µ������
s�����
/div)
Output Under-voltage Response — Normal Operation
VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = ENL = 5V, floating EN/PSV
Output Over-current Response — Normal Operation
VIN = 12V, VOUT = 1.05V, VLDO = V5V = ENL = 5V, EN/PSV= floating; IOUT ramped to trip point
(500mV/div)
1.05V
(10V/div)
0V
(500mV/div)
V2~710mV
(10A/div)
IOUT = 10.37A
(10V/div)
(5V/div)
(5V/div)
Time (100µ������
s�����
/div)
Time (100µ������
s�����
/div)
12
SC417/SC427
Typical Characteristics (continued)
Characteristics in this section are based on using the Detailed Application Circuit on page 7 (SC417/SC427).
Shorted Output Response — Normal Operation
Shorted Output Response — Power-UP Operation
VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
VIN = 12V, VOUT = 1.05V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
(500mV/div)
1.05V
~1.7ms
(500mV/div)
0V
(10A/div)
(10A/div)
(10V/div)
(10V/div)
(5V/div)
(5V/div)
Time (40µ������
s�����
/div)
Time (400µ������
s�����
/div)
13
SC417/SC427
Pin Descriptions
Pin #
Pin Name
Pin Function
1
FB
Feedback input for switching regulator used to program the output voltage — connect to an external resistor divider from VOUT to AGND.
2
FBL
Feedback input for the LDO — connect to an external resistor divider from VLDO to AGND — used to program the LDO output.
3
V5V
5V power input for internal analog circuits and gate drives — connect to external 5V supply or configure
the LDO for 5V and connect to VLDO.
4, 30, PAD 1
AGND
Analog ground
5
VOUT
Switcher output voltage sense pin — also the input to the internal switch-over between VOUT and VLDO.
The voltage at this pin must be less than or equal to the voltage at the V5V pin.
6, 9-11,
PAD 2
VIN
7
VLDO
8
BST
Bootstrap pin — connect a capacitor of at least 100nF from BST to LX to develop the floating supply for the
high-side gate drive.
12
DH
High-side gate drive — do not connect this pin
13
LXBST
23-25, PAD 3
LX
Switching (phase) node
14
DL
Low-side gate drive — do not connect this pin
15-22
PGND
26
PGOOD
27
ILIM
Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LX.
28
LXS
LX sense — connects to RILIM.
Input supply voltage
LDO output — The voltage at this pin must be less than or equal to the voltage at the V5V pin.
LX Boost — connect to the BST capacitor.
Power ground
Open-drain power good indicator — high impedance indicates power is good. An external pull-up
resistor is required.
Enable/power-save input for the switching regulator — connect to AGND to disable the switching regulator.
Float to operate in forced continuous mode (power-save disabled). SC417 — connect to V5V to operate with
ultra-sonic power-save mode enabled. SC427 — connect to V5V to operate with power-save mode enabled
with no minimum frequency.
29
EN/PSV
31
TON
On-time programming input — set the on-time by connecting through a resistor to AGND
32
ENL
Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic to +3V for logic control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
14
SC417/SC427
Block Diagram
V 5V
PGOOD
3
E N /P S V
V IN
29
A
26
V5V
AGND
D
V5V
V IN
B ootstrap
S w itch
C ontrol & S tatus
R eference
DL
G ate D rive
C ontrol
O n-- tim e
G enerator
1
F B C om parator
TO N
V5V
DL
31
Z ero C ross D etector
VOUT
5
A
7
DH
B
LX
13
LX B S T
28
LX S
C
PGND
27
ILIM
14
DL
Lo-side
M O SFET
V IN
Y
B
LD O
V LD O S w itchover M U X
FBL
12
B ypass C om parator
V alley C urrent Lim it
V LD O
BST
H i-side
M O SFET
S oft S tart
FB
8
2
32
ENL
A
B
C
D
=
=
=
=
connected
connected
connected
connect to
to pins 6, 9 -11 , P A D 2
to pins 23 -25 , P A D 3
to pins 15-22
pins 4, 30, P A D 1
15
SC417/SC427
Applications Information
Synchronous Buck Converter
The SC417/SC427 is a step down synchronous DC-DC buck
converter with integrated power MOSFETs and a programmable LDO. The device is capable of 10A operation at very
high efficiency. A space saving 5x5 (mm) 32-pin package
is used. The programmable operating frequency range of
200kHz to 1MHz enables optimizing the configuration for
PCB area and efficiency.
The buck controller uses a pseudo-fixed frequency adaptive on-time control. This control method allows fast transient response which permits the use of smaller output
capacitors.
Figure 1. The ripple voltage generated at the output
capacitor ESR is used as a PWM ramp signal. This ripple is
used to trigger the on-time of the controller.
The adaptive on-time is determined by an internal oneshot timer. When the one-shot is triggered by the output
ripple, the device sends a single on-time pulse to the highside MOSFET. The pulse period is determined by VOUT and
VIN; the period is proportional to output voltage and
inversely proportional to input voltage. With this adaptive
on-time arrangement, the device automatically anticipates the on-time needed to regulate VOUT for the present
VIN condition and at the selected frequency.
In addition to the following information, the user can
click on the applicable link to go to the SC417 online
C-SIM design and simulation tool or to go to the SC427
online C-SIM design and simulation tool, which will
lead the user through the design process.
V LX
F B T hreshold
V OUT
L
Q2
ESR
+
Power Up Sequence
FB
C OUT
Figure 1 — PWM Control Method, VOUT Ripple
The advantages of adaptive on-time control are:
•
•
•
Shutdown
•
The SC417/SC427 can be shutdown by pulling either V5V
or EN/PSV below its threshold. When V5V is active and
EN/PSV at low logic, the output voltage discharges
through an internal FET.
•
The PWM control method used by the SC417/SC427 is
pseudo-fixed frequency, adaptive on-time, as shown in
V FB
V LX
The SC417/SC427 requires two input supplies for normal
operation: VIN and V5V. VIN operates over the wide range
from 3V to 28V. V5V requires a 5V supply input that can be
an external source or the internal LDO configured to
supply 5V from VIN.
Psuedo-fixed Frequency Adaptive On-time Control
C IN
Q1
Input Voltage Requirements
When the SC417/SC427 uses an external power source at
the V5V pin, the switching regulator initiates the start-up
process when VIN, V5V, and EN/PSV are above their respective thresholds. When EN/PSV is at a logic high, V5V needs
to be applied after VIN rises. To start using the EN/PSV pin
when both V5V and VIN are above their respective thresholds, apply EN/PSV to enable the start-up process. For
SC417/SC427 in self-biased mode, refer to the LDO section
for a full description.
TON
V IN
Predictable operating frequency compared to
other variable frequency methods.
Reduced component count by eliminating the
error amplifier and compensation components.
Reduced component count by removing the
need to sense and control inductor current.
Fast transient response — the response time is
controlled by a fast comparator instead of a typically slow error amplifier.
Reduced output capacitance due to fast transient response
One-Shot Timer and Operating Frequency
The one-shot timer operates as shown in Figure 2. The FB
Comparator output goes high when VFB is less than the
16
SC417/SC427
Applications Information (continued)
internal 500mV reference. This feeds into the gate drive
and turns on the high-side MOSFET, and also starts the
one-shot timer. The one-shot timer uses an internal comparator and a capacitor. One comparator input is connected to VOUT, the other input is connected to the capacitor.
When the on-time begins, the internal capacitor charges
from zero volts through a current which is proportional to
VIN. When the capacitor voltage reaches VOUT, the on-time is
completed and the high-side MOSFET turns off.
F B C o m p a ra to r
FB
5 0 0m V
+
V OUT
V IN
G a te
D rive s
O n e -S h o t
T im e r
R TON
V IN
DH
Q1
V LX
DL
Q2
V OUT
L
ESR
C OUT
+
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN.
Under steady-state conditions, the switching frequency
can be determined from the on-time by the following
equation.
VOUT
TON u VIN
The SC417/SC427 uses an external resistor to set the ontime which indirectly sets the frequency. The on-time can
be programmed to provide operating frequency from
200kHz to 1MHz using a resistor between the TON pin and
ground. The resistor value is selected by the following
equation.
(TON 10ns) u VIN
25pF u VOUT
The maximum RTON value allowed is shown by the following equation.
R TON _ MAX
VIN _ MIN
15PA
VOUT Voltage Selection
To FB pin
R1
R2
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to the
following equation.
FB
Figure 2 — On-Time Generation
RTON
V OUT
Figure 3 — Output Voltage Selection
O n -tim e = K x R T O N x (V O U T /V IN )
fSW
Figure 3) to the internal 500mV reference voltage, see the
Detailed Application Circuit.
The switcher output voltage is regulated by comparing
VOUT as seen through a resistor divider at the FB pin (see
VOUT
§ R · §V
·
0.5 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸
R
2
©
¹
2
¹
©
When a large capacitor is placed in parallel with R1 (CTOP)
VOUT is shown by the following equation.
VOUT
§ R · §V
·
0.5 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸ u
© R2 ¹ © 2 ¹
1 (R1ZCTOP )2
§ R u R1
·
1 ¨¨ 2
ZCTOP ¸¸
© R2 R1
¹
2
The switcher output voltage can be programmed higher
than 5V. The VOUT pin is not allowed to connect directly
to the switcher output due to its the maximum voltage
rating. An additional resistor divider network is required
to connect from the switcher output to the VOUT pin.
When SC417/SC427 operates in self-biased mode, the
minimum difference between the voltages for the VOUT
and the VLDO pins should be ±500mV to avoid unwanted
switchover function due to resistor divider voltage drop.
For example, the voltage at the VOUT pin can be 4V if
VLDO is set for 5V. When the SC417/SC427 operates from
an external power source and the LDO is disabled, the
voltage at the VOUT pin can be as high as shown in
Recommended Operating Conditions. R TON is calculated
according to the voltage at the VOUT pin not the voltage
of the switcher output.
Enable and Power-save Input
The EN/PSV input is used to enable or disable the switching regulator. When EN/PSV is low (grounded), the switching regulator is off and in its lowest power state. When off,
17
SC417/SC427
Applications Information (continued)
the output of the switching regulator soft-discharges the
output into a 15Ω internal resistor via the VOUT pin. When
EN/PSV is allowed to float, the pin voltage will float to 33%
of the voltage at V5V. The switching regulator turns on
with power-save disabled and all switching is in forced
continuous mode.
When EN/PSV is high (above 44% of the voltage at V5V)
for SC417, the switching regulator turns on with ultrasonic power-save enabled. The SC417 ultra-sonic powersave operation maintains a minimum switching frequency
of 25kHz, for applications with stringent audio
requirements.
When EN/PSV is high (above 44% of the voltage at V5V)
for SC427, the switching regulator turns on with powersave enabled. The SC427 power-save operation is designed
to maximize efficiency at light loads with no minimum
frequency limits. This makes the SC427 an excellent choice
for portable and battery-operated systems.
Forced Continuous Mode Operation
The SC417/SC427 operates the switcher in Forced
Continuous Mode (FCM) by floating the EN/PSV pin (see
Figure 4). In this mode one of the power MOSFETs is
always on, with no intentional dead time other than to
avoid cross-conduction. This feature results in uniform
frequency across the full load range with the trade-off
being poor efficiency at light loads due to the high-frequency switching of the MOSFETs.
F B R ipple
V oltage (V F B )
F B threshold
(500 m V )
D C Load C urrent
Inductor
C urrent
O n-tim e
(T O N )
D H on -tim e is triggered w hen
V F B reaches the F B T hreshold .
DH
DL
D L drives high w hen on -tim e is com pleted.
D L rem ains high until V F B falls to the F B threshold.
Figure 4 — Forced Continuous Mode Operation
Ultra-sonic Power-save Operation (SC417)
The SC417 provides ultra-sonic power-save operation at
light loads, with the minimum operating frequency fixed
at 25kHz. This is accomplished using an internal timer that
monitors the time between consecutive high-side gate
pulses. If the time exceeds 40µs, DL drives high to turn the
low-side MOSFET on. This draws current from VOUT through
the inductor, forcing both VOUT and VFB to fall. When VFB
drops to the 500mV threshold, the next DH on-time is triggered. After the on-time is completed the high-side
MOSFET is turned off and the low-side MOSFET turns on.
The low-side MOSFET remains on until the inductor
current ramps down to zero, at which point the low-side
MOSFET is turned off.
Because the on-times are forced to occur at intervals no
greater than 40µs, the frequency will not fall below
~25kHz. Figure 5 shows ultra-sonic power-save
operation.
18
SC417/SC427
Applications Information (continued)
m inim um f S W ~ 25kH z
F B R ipple
V oltage (V F B )
F B threshold
(500 m V )
(0A )
Inductor
C urrent
O n-tim e
(T O N )
D ead tim e varies
according to load
F B R ipple
V oltage
(V F B )
F B threshold
(500 m V )
Inductor
C urrent
Z ero (0A )
D H O n-tim e is triggered w hen
V F B reaches the F B T hreshold
DH
O n-tim e (T O N )
D H O n -tim e is triggered w hen
V F B reaches the F B T hreshold .
DH
40µs tim e-out
DL
DL
A fter the 40µsec tim e-out, D L drives high if V F B
has not reached the F B threshold.
Figure 5 — Ultrasonic Power-save Operation
Power-save Mode Operation (SC427)
The SC427 provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors
the inductor current via the voltage across the low-side
MOSFET during the off-time. If the inductor current falls to
zero for 8 consecutive switching cycles, the controller
enters power-save operation. It will turn off the low-side
MOSFET on each subsequent cycle provided that the
current crosses zero. At this time both MOSFETs remain
off until VFB drops to the 500mV threshold. Because the
MOSFETs are off, the load is supplied by the output capacitor. If the inductor current does not reach zero on any
switching cycle, the controller immediately exits powersave and returns to forced continuous mode. Figure 6
shows power-save operation at light loads.
D L drives high w hen on -tim e is com pleted.
D L rem ains high until inductor current reaches zero.
Figure 6 — Power-save Operation
Smart Power-save Protection
Active loads may leak current from a higher voltage into
the switcher output. Under light load conditions with
power-save enabled, this can force VOUT to slowly rise and
reach the over-voltage threshold, resulting in a hard shutdown. Smart power-save prevents this condition. When
the FB voltage exceeds 10% above nominal (exceeds
550mV), the device immediately disables power-save, and
DL drives high to turn on the low-side MOSFET. This draws
current from VOUT through the inductor and causes VOUT to
fall. When VFB drops back to the 500mV trip point, a normal
TON switching cycle begins. This method prevents a hard
OVP shutdown and also cycles energy from VOUT back to
VIN. It also minimizes operating power by avoiding forced
conduction mode operation. Figure 7 shows typical waveforms for the Smart Power-save feature.
SmartDriveTM
For each DH pulse the DH driver initially turns on the highside MOSFET at a lower speed, allowing a softer, smooth
turn-off of the low-side diode. Once the diode is off and
the LX voltage has risen 0.5V above PGND, the SmartDrive
circuit automatically drives the high-side MOSFET on at a
rapid rate. This technique reduces switching while maintaining high efficiency and also avoids the need for snubbers or series resistors in the gate drive.
19
SC417/SC427
Applications Information (continued)
V O U T d rifts u p to d u e to le a ka g e
cu rre n t flo w in g in to C O U T
V O U T d isch a rg e s via in d u cto r
a n d lo w -sid e M O S F E T
S m a rt P o w e r S a ve
T h re sh o ld (5 5 0 m V )
N o rm a l V O U T rip p le
FB
th re sh o ld
D H a n d D L o ff
Setting the valley current limit to 10A results in a peak
inductor current of 10A plus peak ripple current. In this
situation, the average (load) current through the inductor
is 10A plus one-half the peak-to-peak ripple current.
The internal 10μA current source is temperature compensated at 4100ppm in order to provide tracking with the
RDSON.
H ig h-sid e
D rive (D H )
S in g le D H o n-tim e p u lse
a fte r D L tu rn -o ff
The RILIM value is calculated by the following equation.
L o w -sid e
D rive (D L )
D L tu rn s o n w h e n S m a rt
P S A V E th re sh o ld is re a ch e d
N o rm a l D L p u lse a fte r D H
o n -tim e p u lse
D L tu rn s o ff w h e n F B
th re sh o ld is re a ch e d
Figure 7 — Smart Power-save
Current Limit Protection
In d u c to r C u rren t
The device features programmable current limiting, which
is accomplished by using the RDSON of the lower MOSFET
for current sensing. The current limit is set by RILIM resistor.
The RILIM resistor connects from the ILIM pin to the LX pin
which is also the drain of the low-side MOSFET. When the
low-side MOSFET is on, an internal ~10μA current flows
from the ILIM pin and through the RILIM resistor, creating a
voltage drop across the resistor. While the low-side MOSFET
is on, the inductor current flows through it and creates a
voltage across the RDSON. The voltage across the MOSFET is
negative with respect to ground. If this MOSFET voltage
drop exceeds the voltage across RILIM, the voltage at the ILIM
pin will be negative and current limit will activate. The
current limit then keeps the low-side MOSFET on and will
not allow another high-side on-time, until the current in the
low-side MOSFET reduces enough to bring the ILIM voltage
back up to zero. This method regulates the inductor valley
current at the level shown by ILIM in Figure 8.
IP E A K
I LO A D
I LIM
RILIM = 735 x ILIM
When selecting a value for RILIM be sure not to exceed the
absolute maximum voltage value for the ILIM pin. Note
that because the low-side MOSFET with low RDSON is used
for current sensing, the PCB layout, solder connections,
and PCB connection to the LX node must be done carefully to obtain good results. RILIM should be connected
directly to LXS (pin 28).
Soft-Start of PWM Regulator
Soft-start is achieved in the PWM regulator by using an
internal voltage ramp as the reference for the FB
Comparator. The voltage ramp is generated using an
internal charge pump which drives the reference from
zero to 500mV in ~1.2mV increments, using an internal
~500kHz oscillator. When the ramp voltage reaches
500mV, the ramp is ignored and the FB comparator
switches over to a fixed 500mV threshold. During soft-start
the output voltage tracks the internal ramp, which limits
the start-up inrush current and provides a controlled softstart profile for a wide range of applications. Typical softstart ramp time is 850μs.
Pre-Bias Startup
SC417/427 can start up into a pre-biased output voltage.
The start up time is approximately 850μs from enable to
regulation. The output voltage starts to ramp up when
the internal ramp meets the pre-charged FB voltage level.
Pre-bias startup is achieved by turning off the lower gate
when the inductor current falls below zero. This method
prevents output voltage discharge.
T im e
Figure 8 — Valley Current Limit
20
SC417/SC427
Applications Information (continued)
Power Good Output
The power good (PGOOD) output is an open-drain output
which requires a pull-up resistor. When the output voltage
is 10% below the nominal voltage, PGOOD is pulled low. It
is held low until the output voltage returns above -8% of
nominal. PGOOD is held low during start-up and will not
be allowed to transition high until soft-start is completed
(when VFB reaches 500mV) and typically 2ms has passed.
PGOOD will transition low if the VFB pin exceeds +20% of
nominal, which is also the over-voltage shutdown threshold (600mV). PGOOD also pulls low if the EN/PSV pin is
low when V5V is present.
Output Over-Voltage Protection
used as the bias supply, the LDO can be programmed to
provide a different voltage (see Figure 9).
VLD O
R LDO 1
T o F B L p in
R LDO 2
Figure 9 — LDO Start-Up
The LDO output voltage is set by the following equation.
VLDO
·
§
R
750mV u ¨¨1 LDO1 ¸¸
R
LDO 2 ¹
©
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 500mV + 20%
(600mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off, until the EN/PSV input
is toggled or V5V is cycled. There is a 5μs delay built into
the OVP detector to prevent false transitions. PGOOD is
also low after an OVP event.
A minimum capacitance of 1μF referenced to AGND is
normally required at the output of the LDO for stability. If
the LDO is providing bias power to the device, then a
minimum 0.1μF capacitor referenced to AGND is required
along with a minimum 1.0μF capacitor referenced to
PGND to filter the gate drive pulses. Refer to the layout
guidelines section.
Output Under-Voltage Protection
The ENL input is used to enable/disable the internal LDO.
When ENL is a logic low, the LDO is off. When ENL is a high
but below the VIN UVLO threshold (2.6V typical), then the
LDO is on and the switcher is off. When ENL is above the VIN
UVLO threshold, the LDO is enabled and the switcher is also
enabled if the EN/PSV pin is not grounded. The table below
summarizes the function of ENL and EN/PSV pins.
When VFB falls 25% below its nominal voltage (falls to
375mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tristate the MOSFETs. The controller stays off until EN/PSV is
toggled or V5V is cycled.
V5V UVLO, and POR
Under-Voltage Lock-Out (UVLO) circuitry inhibits switching
and tri-states the DH/DL drivers until V5V rises above 3.9V.
An internal Power-On Reset (POR) occurs when V5V exceeds
3.9V, which resets the fault latch and soft-start counter to
prepare for soft-start. The SC417/SC427 then begins a softstart cycle. The PWM will shut off if V5V falls below 3.6V.
LDO Regulator
The LDO output is programmable from 0.75V to 5.25V
using external resistors. The feedback pin (FBL) for the
LDO is regulated to 750mV. There is also an enable pin
(ENL) for the LDO that provides independent control. The
LDO voltage can also be used to provide the bias voltage
for the switching regulator. When a separate source is
LDO ENL Functions
EN/PSV
ENL
LDO
Switcher
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Low, < 0.4V
Low, < 0.4V
1.0V < High < 2.6V
1.0V < High < 2.6V
High, > 2.6V
High, > 2.6V
OFF
OFF
ON
ON
ON
ON
OFF
ON
OFF
OFF
OFF
ON
The ENL pin also acts as the switcher under-voltage lockout
for the VIN supply. When SC417/SC427 is self-biased from
the LDO and runs from the VIN power source only, the VIN
UVLO feature can be used to prevent false UV faults for the
PWM output by programming with a resistor divider at the
VIN, ENL and AGND pins. When SC417/SC427 has an exter21
SC417/SC427
Applications Information (continued)
nal bias voltage at V5V and the ENL pin is used to program
the VIN UVLO feature, the voltage at FBL needs to be higher
than 750mV to force the LDO off.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM
output turning off. If ENL goes below the VIN UVLO
threshold and stays above 1V, then the switcher will turn
off but the LDO will remain on.
Additional protection logic is included in the SC417/SC427
to allow for maximum flexibility of the IC and controlled
starting in self-biased mode. In self-biased mode where the
LDO and PWM are started at the same time, the PWM
output will not start until the LDO reaches 90% of it’s final
value. This prevents overloading the current limited LDO
output during LDO start up. When using the LDO as an
independent output, it is desirable to be able to turn the
LDO on and off independent of the PWM output. This is
accomplished by checking the PWM PGOOD output during
start-up. If PGOOD is high when the LDO turns on then the
two outputs are assumed to be independent and the LDO
start-up will not effect the PWM. If the PGOOD output is
low then the part is assumed to be in self-biased mode and
the PWM turn-on is delayed until the LDO start-up is 90%
complete.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
1. ENL pin
2. VLDO output
3. VIN input voltage
When the ENL pin is high and VIN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when
the LDO output voltage is near zero, the LDO initiates a
current-limited start-up (typically 85mA) to charge the output
capacitor. When VLDO has reached 90% of the final value (as
sensed at the FBL pin), the LDO current limit is increased to
~200mA and the LDO output is quickly driven to the nominal
value by the internal LDO regulator (see Figure 10).
V V L D O F inal
V oltage regulating w ith
~ 200 m A current lim it
90 % of V V L D O F inal
C onstant current startup
Figure 10 — LDO Start-Up
LDO Switch-Over Operation
The SC417/SC427 includes a switch-over function for the
LDO. The switch-over function is designed to increase
efficiency by using the more efficient DC-DC converter to
power the LDO output, avoiding the less efficient LDO
regulator when possible. The switch-over function connects the VLDO pin directly to the VOUT pin using an
internal switch. When the switch-over is complete the
LDO is turned off, which results in a power savings and
maximizes efficiency. If the LDO output is used to bias the
SC417/SC427, then after switch-over the device is selfpowered from the switching regulator with the LDO
turned off.
The switch-over logic waits for 32 switching cycles before
it starts the switch-over. There are two methods that
determine the switch-over of VLDO to VOUT.
In the first method, the LDO is already in regulation and
the DC-DC converter is later enabled. As soon as the
PGOOD output goes high, the 32 cycles are started. The
voltages at the VLDO and VOUT pins are then compared;
if the two voltages are within ±300mV of each other, the
VLDO pin connects to the VOUT pin using an internal
switch, and the LDO is turned off.
In the second method, the DC-DC converter is already
running and the LDO is enabled. In this case the 32 cycles
are started as soon as the LDO reaches 90% of its final
value. At this time, the VLDO and VOUT pins are compared,
and if within ±300mV the switch-over occurs and the LDO
is turned off.
Switch-over Limitations on VOUT and VLDO
Because the internal switch-over circuit always compares
the VOUT and VLDO pins at start-up, there are limitations
on permissible combinations of these pins. Consider the
case where VOUT is programmed to 3.0V and VLDO is pro22
SC417/SC427
Applications Information (continued)
grammed to 3.3V. After start-up, the device would connect
VOUT to VLDO and disable the LDO, since the two voltages are within the ±300mV switch-over window. To avoid
unwanted switch-over, the minimum difference between
the voltages for VOUT and VLDO should be ±500mV.
It is not recommended to use the switch-over feature for
an output voltage less than 3V since this does not provide
sufficient voltage for the gate-source drive to the internal
p-channel switch-over MOSFET.
Switch-over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that
are inherent to its construction, as shown in Figure 11.
S w itchover
control
S w itchover
M O SFET
V OUT
V LDO
P arasitic diode
P arasitic diode
V5V
Figure 11— Switch-over MOSFET Parasitic Diodes
There are some important design rules that must be followed to prevent forward bias of these diodes. The following two conditions need to be satisfied in order for the
parasitic diodes to stay off.
•
•
V5V ≥ VLDO
V5V ≥ VOUT
If either VLDO or VOUT is higher than V5V, then the respective
diode will turn on and the SC417/SC427 operating current
will flow through this diode. This has the potential of
damaging the device.
Using the On-chip LDO to Bias the SC417/SC427
The following steps must be followed when using the onchip LDO to bias the device.
•
•
Connect V5V to VLDO before enabling the LDO.
The LDO has an initial current limit of 85mA at
start-up, therefore, do not connect any external
load to VLDO during start-up.
•
When VLDO reaches 90% of its final value, the
LDO current limit increases to 200mA. At this
time the LDO may be used to supply the required
bias current to the device.
Attempting to operate in self-powered mode in any other
configuration can cause unpredictable results and may
damage the device.
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor
ripple current must be specified.
The maximum input voltage (VINMAX) is the highest specified input voltage. The minimum input voltage ( VINMIN) is
determined by the lowest input voltage after evaluating
the voltage drops due to connectors, fuses, switches, and
PCB traces.
The following parameters define the design.
•
•
•
•
Nominal output voltage (VOUT )
Static or DC output tolerance
Transient response
Maximum load current (IOUT )
There are two values of load current to evaluate — continuous load current and peak load current. Continuous
load current relates to thermal stresses which drive the
selection of the inductor and input capacitors. Peak load
current determines instantaneous component stresses and
filtering requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
The following values are used in this design.
•
•
•
•
VIN = 12V + 10%
VOUT = 1.05V + 4%
fSW = 250kHz
Load = 10A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the
power conversion efficiency.
23
SC417/SC427
Applications Information (continued)
The desired switching frequency is 250kHz which results
from using components selected for optimum size and
cost.
A resistor (RTON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
RTON
(TON 10ns) u VIN
25pF u VOUT
To select RTON, use the maximum value for VIN, and for TON
use the value associated with maximum VIN.
T ON
V OUT
V INMAX u f SW
TON = 318 ns at 13.2VIN, 1.05VOUT, 250kHz
Substituting for RTON results in the following solution.
RTON = 154.9kΩ, use RTON = 154kΩ
Inductor Selection
In order to determine the inductance, the ripple current
must first be defined. Low inductor values result in smaller
size but create higher ripple current which can reduce
efficiency. Higher inductor values will reduce the ripple
current/voltage and for a given DC resistance are more
efficient. However, larger inductance translates directly
into larger packages and higher cost. Cost, size, output
ripple, and efficiency are all used in the selection process.
The ripple current will also set the boundary for powersave operation. The switching will typically enter powersave mode when the load current decreases to 1/2 of the
ripple current. For example, if ripple current is 4A then
Power-save operation will typically start for loads less than
2A. If ripple current is set at 40% of maximum load current,
then power-save will start for loads less than 20% of
maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25% to 50% of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the DH on-time, voltage across the inductor is
(VIN - VOUT ). The equation for determining inductance is
shown next.
L
( VIN VOUT ) u TON
IRIPPLE
Example
In this example, the inductor ripple current is set equal to
50% of the maximum load current. Therefore ripple
current will be 50% x 10A or 5A. To find the minimum
inductance needed, use the VIN and TON values that correspond to VINMAX.
L
(13.2 1.05) u 318ns
5A
0.77PH
A slightly larger value of 0.88µH is selected. This will
decrease the maximum IRIPPLE to 4.4A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
TON _ VINMIN
IRIPPLE
25pF u RTON u VOUT
10ns
VINMIN
384ns
( VIN VOUT ) u TON
L
IRIPPLE _ VINMIN
(10.8 1.05 ) u 384ns
088PH
4.25 A
Output Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. Change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal is that the output voltage regulation be
±4% under static conditions. The internal 500mV reference tolerance is 1%. Allowing 1% tolerance from the FB
resistor divider, this allows 2% tolerance due to VOUT ripple.
24
SC417/SC427
Applications Information (continued)
Since this 2% error comes from 1/2 of the ripple voltage,
the allowable ripple is 4%, or 42mV for a 1.05V output.
The following can be used to calculate the needed capacitance for a given dILOAD/dt.
The maximum ripple current of 4.4A creates a ripple
voltage across the ESR. The maximum ESR value allowed
is shown by the following equations.
Peak inductor current is shown by the next equation.
ESRMAX
VRIPPLE
42mV
4 .4 A
IRIPPLEMAX
ILPK = IMAX + 1/2 x IRIPPLEMAX
ILPK = 10 + 1/2 x 4.4 = 12.2A
Rate of change of Load Current
ESRMAX = 9.5 mΩ
The output capacitance is usually chosen to meet transient requirements. A worst-case load release, from
maximum load to no load at the exact moment when
inductor current is at the peak, determines the required
capacitance. If the load release is instantaneous (load
changes from maximum to zero in < 1µs), the output
capacitor must absorb all the inductor’s stored energy.
This will cause a peak voltage on the capacitor according
to the following equation.
COUTMIN
1
§
·2
L¨ IOUT u IRIPPLEMAX ¸
2
©
¹
2
VPEAK VOUT 2
COUTMIN
2
1.15 1.05 2
COUTMIN = 595µF
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 500mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately
-VOUT. This causes a down-slope or falling di/dt in the
inductor. If the load di/dt is not much faster than the
-di/dt in the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor, therefore a smaller capacitance can be used.
IMAX = maximum load release = 10A
Lu
COUT
ILPK u
ILPK
I
MAX u dt
VOUT dlLOAD
2VPK VOUT Example
dlLOAD
dt
2 .5 A
Ps
This would cause the output current to move from 10A to
0A in 4µs, giving the minimum output capacitance
requirement shown in the following equation.
Assuming a peak voltage VPEAK of 1.150 (100mV rise upon
load release), and a 10A load release, the required capacitance is shown by the next equation.
1
§
·2
0.88PH¨10 u 4.4 ¸
2
©
¹
dlLOAD
dt
COUT
12.2 u
12.2 10
u 1Ps
1.05 2.5
21.15 1.05 0.88PH u
COUT = 379 µF
Note that COUT is much smaller in this example, 379µF
compared to 595µF based on a worst-case load release. To
meet the two design criteria of minimum 379µF and
maximum 9mΩ ESR, select two capacitors rated at 220µF
and 15mΩ ESR.
It is recommended that an additional small capacitor be
placed in parallel with COUT in order to filter high frequency
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or
ESR loop instability.
25
SC417/SC427
Applications Information (continued)
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250ns minimum off-time has expired. In extreme cases
the noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation. This form of instability can usually be avoided by
providing the FB pin with a smooth, clean ripple signal
that is at least 10mVp-p, which may dictate the need to
increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout as discussed in the
Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a
small (~ 10pF) capacitor across the upper feedback resistor, as shown in Figure 13. This capacitor should be left
unpopulated until it can be confirmed that double-pulsing
exists. Adding the CTOP capacitor will couple more ripple
into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor.
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and discharging during the switching cycle. For most applications the minimum ESR ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching frequency. The formula for minimum ESR is shown by the
following equation.
ESR MIN
3
2 u S u C OUT u f sw
Using Ceramic Output Capacitors
C TOP
V OUT
ESR Requirements
T o F B pin
R1
R2
Figure 13 — Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
One simple way to solve this problem is to add trace resistance in the high current output path. A side effect of
adding trace resistance is a decrease in load regulation.
For applications using ceramic output capacitors, the ESR
is normally too small to meet the above ESR criteria. In
these applications it is necessary to add a small virtual ESR
network composed of two capacitors and one resistor, as
shown in Figure 14. This network creates a ramp voltage
across CL, analogous to the ramp voltage generated across
the ESR of a standard capacitor. This ramp is then capacitively coupled into the FB pin via capacitor CC.
L
H ig hsid e
Lowsid e
RL
CL
R1
CC
FB
p in
C OUT
R2
Figure 14 — Virtual ESR Ramp Current
26
SC417/SC427
Applications Information (continued)
The component values used in this circuit are calculated
using the following procedure.
Select CL (100nF) and RL to provide a 25mV ripple across
CL (VCL).
RL
VIN VOUT
ICL
where
ICL
Dropout Performance
CL u 'VCL
TON
The output voltage adjust range for continuous-conduction operation is limited by the fixed 250ns (typical)
minimum off-time of the one-shot. When working with
low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times.
and
TON
VOUT
VIN u fSW
The duty-factor limitation is shown by the next equation.
Next choose a value for CC so that
CC
TON
REQ
DUTY
where
REQ
tance of ceramic capacitors varies under DC bias and temperature. Another factor of selecting the input capacitors
is its voltage rating which needs to be higher than the
maximum input voltage because the ringing on the LX
node. While a single capacitor is sufficient to handle the
ripple current, additional ceramic capacitors or bulk
capacitors may be needed to provide local energy storage
and a low impedance input source to account for any PCB
or input connector impedances.
TON(MIN)
TON(MIN) TOFF(MAX )
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
R1 u R 2
R1 R 2
The resistor values (R1 and R2) in the voltage divider circuit
set the VOUT for the switcher.
Choosing Input Capacitors
Input capacitors bank is used to provide AC current to the
power stage when the high side FET turns on and especially during the output current step up. The ripple current
rating of the input capacitors must meet or exceed I RMS
ripple caused by the switching currents. The ripple current
generated is calculated using the following equation.
IRMS
IOUT u
VOUT u ( VIN VOUT )
VIN
IRMS
10 A u
1.05 V u (12V 1.05 V )
12V
2.83 A
Because of their low ESR and ESL, ceramic capacitors are
typically used. High quality dielectric capacitors should
be used (for example X5R or X7R). The effective capaci-
System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static conditions it trips when the feedback pin is 500mV, 1%.
The on-time pulse from the SC417/SC427 in the design
example is calculated to give a pseudo-fixed frequency of
250kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple
voltage. Because constant on-time converters regulate to
the valley of the output ripple, ½ of the output ripple
appears as a DC regulation error. For example, if the
output ripple is 50mV with VIN = 6 volts, then the measured
DC output will be 25mV above the comparator trip point.
If the ripple increases to 80mV with VIN = 25V, then the
measured DC output will be 40mV above the comparator
trip. The best way to minimize this effect is to minimize
the output ripple.
27
SC417/SC427
Applications Information (continued)
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at
full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps
are reduced as seen at the load.
The use of 1% feedback resistors may result in up to 1%
error. If tighter DC accuracy is required, 0.1% resistors
should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor effect on the DC output voltage. The output ESR
also affects the output ripple and thus has a minor effect
on the DC output voltage.
Switching Frequency Variations
propagation delays in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
VIN increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net effect is
that frequency tends to falls slightly with increasing input
voltage.
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. A constant on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from VIN as losses increase). The on-time is essentially constant for a given VOUT/VIN combination, to offset
the losses the off-time will tend to reduce slightly as load
increases. The net effect is that switching frequency
increases slightly with increasing load.
The switching frequency will vary depending on line and
load conditions. The line variations are a result of fixed
28
SC417/SC427
Applications Information (continued)
PCB Layout Guidelines
The optimum layout for the SC417/SC427 is shown in
Figure 15. This layout shows an integrated FET buck regulator with a maximum current of 10A. The total PCB area is
approximately 20 x 25 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
•
•
•
•
•
•
IC Decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
BST, ILIM, and LX
CIN and COUT placement and Current Loops
IC Decoupling Capacitors
A 0.1 μF capacitor must be located as close as
possible to the IC and directly connected to pins
3 (V5V) and 4 (AGND).
All other decoupling capacitors must be located
as close as possible to the IC.
•
•
PGND Plane
PGND requires its own copper plane with no
other signal traces routed on it.
Copper planes, multiple vias and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the IC.
The PGND copper area between the input
capacitors, output capacitors and PGND pins
must be as tight and compact as possible to
reduce the area of the PCB that is exposed to
noise due to current flow on this node.
Connect PGND to AGND with a short trace or
0Ω resistor. This connection should be as close
to the IC as possible.
•
•
•
•
AGND Island
AGND should have its own island of copper with
no other signal traces routed on this layer that
connects the AGND pins and pad of the IC to the
analog control components.
All of the components for the analog control circuitry should be located so that the connections
•
•
V 5 V D e co u p lin g C a p a cito r
R G N D — A G N D co n n e cts to
P G N D clo se to S C 4 1 7/S C 4 2 7
A G N D p la n e o n
in n e r la ye r
R IL IM
RLDO 2
CLDO
RFB1
CFF
RFB2
PG ND on
T o p L a ye r
CBST
C IN
P in 1 m a rkin g
S C 4 1 7/S C 4 2 7
w ith via s fo r L X ,
A G N D , V IN
CV5V
A ll co m p o n e n ts
sh o w n T o p S id e
RLDO 1
V IN p la n e o n in n e r
o r b o tto m la ye r
C OUT
V O U T P la n e
o n T o p la ye r
L
P G N D o n in n e r
o r b o tto m la ye r
L X p la n e o n in n e r
o r b o tto m la ye r
PGND
Figure 15 — PCB Layout
29
SC417/SC427
Applications Information (continued)
•
to AGND are done by wide copper traces or vias
down to AGND.
Connect PGND to AGND with a short trace or 0Ω
resistor. This connection should be as close to
the IC as possible.
FB, VOUT, and Other Analog Control Signals
The connection from the V OUT power to the
analog control circuitry must be routed from the
output capacitors and located on a quiet layer.
The traces between Vout and the analog control
circuitry (VOUT, and FB pins) must be short and
routed away from noise sources, such as BST, LX,
VIN, and PGND between the input capacitors,
output capacitors, and the IC.
ILIM and TON nodes must be as short as possible
to ensure the best accuracy in current limit and
on time.
RILIM should be close to the IC and connected to
LX with a Kelvin trace to pin 28 on the IC. All of
the LX pins are connected to the LX PAD on the
IC, which should be a sufficient connection and
will prevent the need to connect the resistor
further into the LX plane.
The feedback components for the switcher and
the LDO need to be as close to the FB and FBL
pins of the IC as possible to reduce the possibility of noise corrupting these analog signals.
•
•
•
•
•
BST, ILIM and LX
LX and BST are very noisy nodes and must be
routed to minimized the PCB area that is exposed
to these signals.
The connections for the boost capacitor
between the IC and LX must be short and directly
connected to the LXBST (pin 13).
The connections for the current limit resistor
between the ILIM pin and LX must be as short as
possible and directly connected to pin 28 (LXS).
The LX node between the IC and the inductor
should be wide enough to handle the inductor
current and short enough to eliminate the possibility of LX noise corrupting other signals.
Multiple vias should be used to provide a good
connection to LX between the IC and the
inductor.
•
•
•
•
•
Capacitors and Current Loops
The current loops between the input capacitors,
the IC, the inductor, and the output capacitors
must be as close as possible to each other to
reduce IR drop across the copper.
All bypass and output capacitors must be connected as close as possible to the pin on the IC.
•
•
30
SC417/SC427
Outline Drawing — MLPQ-5x5-32
B
D
A
D IM
P IN 1
IN D IC A T O R
(LA S E R M A R K )
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
E
A2
A
aaa
S E A T IN G
D IM E N S IO N S
IN C H E S
M ILLIM E T E R S
M IN N O M M A X M IN N O M M A X
.031
.039 0.80
1.00
.000
.002 0.00
0.05
(.008 )
(0.20 )
.007 .010 .012 0.18 0.25 0.30
.193 .197 .201 4.90 5.00 5.10
.076 .078 .080 1.92 1.97 2.02
.193 .197 .201 4.90 5.00 5.10
3.43 3.48 3.53
.135 .137 .139
.020 B S C
0.50 B S C
.012 .016 .020 0.30 0.40
0.50
32
32
.003
0.08
.004
0.10
P LA N E
C
C
A1
3.48
D1
0.76
1.05
LxN
1.49
E1
3.61
1.66
2
1
0.76
N
R 0.20
P IN 1
ID E N T IF IC A T IO N
bxN
e
bbb
C
A
B
NO TES:
1. C O N T R O LLIN G D IM E N S IO N S A R E IN M ILLIM E T E R S (A N G LE S IN D E G R E E S ).
2. C O P LA N A R IT Y A P P LIE S T O T H E E X P O S E D P A D A S W E LL A S T H E T E R M IN A LS .
31
SC417/SC427
Land Pattern — MLPQ-5x5-32
3 .48
K1
K
D IM E N S IO N S
1 .74
(C )
H2
1.74
H
3.61
G
Z
H1
D IM
IN C H E S
M ILLIM E T E R S
C
(.195 )
(4 .95 )
G
.165
4 .20
H
.137
3 .48
H1
.059
1 .49
H2
.065
1 .66
K
.078
1 .97
K1
.041
1 .05
P
.020
0 .50
X
.012
0 .30
Y
.030
0 .75
Z
.224
5 .70
Y
X
P
NO TES:
1.
C O N T R O LLIN G D IM E N S IO N S A R E IN M ILLIM E T E R S (A N G LE S IN D E G R E E S ).
2. T H IS LA N D P A T T E R N IS F O R R E F E R E N C E P U R P O S E S O N LY .
C O N S U LT Y O U R M A N U F A C T U R IN G G R O U P T O E N S U R E Y O U R
C O M P A N Y 'S M A N U F A C T U R IN G G U ID E LIN E S A R E M E T .
3. T H E R M A L V IA S IN T H E LA N D P A T T E R N O F T H E E X P O S E D P A D
S H A LL B E C O N N E C T E D T O A S Y S T E M G R O U N D P LA N E .
F A ILU R E T O D O S O M A Y C O M P R O M IS E T H E T H E R M A L A N D /O R
F U N C T IO N A L P E R F O R M A N C E O F T H E D E V IC E .
4. S Q U A R E P A C K A G E -D IM E N S IO N S A P P LY IN B O T H X A N D Y D IR E C T IO N S .
32
SC417/SC427
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200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
33