SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine GENERAL DESCRIPTION KEY PRODUCT FEATURES The SX1507QB, SX1508QB and SX1509QB are complete ultra low voltage General Purpose parallel Input/Output (GPIO) expanders ideal for low power handheld battery powered equipment. This family of GPIOs comes in 4-, 8-, 16-channel configuration and allows easy serial expansion of I/O through a 2 standard 400kHz I C interface. GPIO devices can provide additional control and monitoring when the microcontroller or chipset has insufficient I/O ports, or in systems where serial communication and control from a remote location is advantageous. • • • These devices can also act as a level shifter to connect a microcontroller running at one voltage level to a component running at a different voltage level, thus eliminating the need for extra level translating circuits. The core is operating as low as 1.2V (SX1507QB) while the dual I/O banks can operate between 1.2V and 5.5V (SX1507QB) independent of the core voltage and each other (5.5V tolerant). • • The SX1507QB, SX1508QB and SX1509QB feature a fully programmable LED Driver with internal oscillator for enhanced lighting control such as intensity (via 256-step PWM), blinking and breathing (fade in/out) make them highly versatile for a wide range of LED applications. • • In addition, keypad applications are also supported with an on-chip scanning engine that enables continuous keypad monitoring up to 64 keys without any additional host interaction reducing bus activity. • • • • • • • • The SX1507QB, SX1508QB and SX1509QB have the ability to generate mask-programmable interrupts based on a falling/rising edge of any of its GPIO lines. A dedicated pin (NINT) indicates to a host controller that a state change occurred on one or more of the lines. Each GPIO is programmable via a bank of 8-bit configuration registers that include data, direction, pull-up/pull-down, interrupt mask and interrupt registers. These I/O expanders feature small footprint packages and are rated from -40°C to +85°C temperature range. TYPICAL APPLICATIONS • • • ORDERING INFORMATION I/Os 4 8 16 8 16 Package QFN-UT-14 QFN-UT-20 QFN-UT-28 Evaluation Kit Evaluation Kit Marking HAB7 HCA5 - Cell phones, PDAs, MP3 players Digital camera, Notebooks, GPS Units Any battery powered equipment OSCIO Part Number (1) SX1507QBXXX SX1508QBIULTRT SX1509QBIULTRT SX1508BEVK SX1509BEVK 1.2V to 5.5V (SX1507QB) Low Operating Voltage with Dual Independent I/O Rails (VCC1, VCC2) Enable Direct Level Shifting Between I/O Banks and Host Controller 5.5V Tolerant I/Os, Up to 15mA Output Sink on All I/Os (No Total Sink Current Limit) Integrated LED Driver for Enhanced Lighting Intensity Control (256-step PWM) Blink Control (224 On/Off values) Breathing Control (224 Fade In/Out values) On-Chip Keypad Scanning Engine Support Up to 8x8 Matrix (64 Keys) Configurable Input Debouncer 4/8/16 Channels of True Bi-directional Style I/O Programmable Pull-up/Pull-down Push/Pull or Open-drain outputs Programmable Polarity Open Drain Active Low Interrupt Output (NINT) Bit Maskable Programmable Edge Sensitivity Built-in Clock Management (Internal 2MHz Oscillator/External Clock Input, 7 clock values) OSCIO can be Configured as GPO 2 400kHz I C Compatible Slave Interface 4 User-Selectable I²C Slave Addresses Power-On Reset and Reset Input (NRESET) Ultra Low Current Consumption: 1uA Typ -40°C to +85°C Operating Temperature Range Up to 2kV HBM ESD Protection Small Footprint Packages Pb & Halogen Free, RoHS/WEEE compliant LEVEL SHIFTING VCC1 1.2 - 3.6V IO0 IO1 VDDM 1.425 - 3.6V Host Controller (1) Future product IO2 IO3 I2C NINT SX1508QB NRESET FULL LED DRIVE VCC2 1.2 - 3.6V IO4 IO5 IO6 KEYPAD SCANNING ADDR1 ADDR0 IO7 BUTTON CONTROL th Rev 3 – 9 Sept. 2010 1 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING Table of Contents GENERAL DESCRIPTION ..................................................................................................................... 1 ORDERING INFORMATION................................................................................................................... 1 KEY PRODUCT FEATURES.................................................................................................................. 1 TYPICAL APPLICATIONS ..................................................................................................................... 1 1 PIN DESCRIPTION ...................................................................................................................... 4 2 1.1 1.2 1.3 1.4 2 SX1507QB 4-channel I C GPIO with LED Driver 2 SX1508QB 8-channel I C GPIO with LED Driver and Keypad Engine 2 SX1509QB 16-channel I C GPIO with LED Driver and Keypad Engine I/Os Feature Summary 4 5 6 7 ELECTRICAL CHARACTERISTICS ............................................................................................... 8 2.1 2.2 Absolute Maximum Ratings Electrical Specifications 8 8 3 TYPICAL OPERATING CHARACTERISTICS ............................................................................... 11 4 BLOCK DETAILED DESCRIPTION ............................................................................................. 12 2 4.1 4.2 4.3 4.4 SX1507QB 4-channel I C GPIO with LED Driver 2 SX1508QB 8-channel I C GPIO with LED Driver and Keypad Engine 2 SX1509QB 16-channel I C GPIO with LED Driver and Keypad Engine Reset 4.4.1 Hardware (NRESET) 4.4.2 Software (RegReset) 2 4.5 2-Wire Interface (I C) 4.5.1 WRITE 4.5.2 READ 4.6 I/O Banks 4.6.1 Input Debouncer 4.6.2 Keypad Scanning Engine 4.6.3 Level Shifter 4.6.4 Polarity Inverter 4.7 Interrupt (NINT) 4.8 Clock Management 4.9 LED Driver 4.9.1 Overview 4.9.2 Static Mode 4.9.3 Single Shot Mode 4.9.4 Blink Mode 4.9.5 LED Driver Modes 4.9.6 Synchronization of LED Drivers across several ICs 4.9.7 Tutorial 5 12 12 13 13 13 14 14 14 15 15 15 15 16 17 17 18 18 18 19 19 20 20 21 21 CONFIGURATION REGISTERS .................................................................................................. 23 5.1 5.2 5.3 6 SX1507QB 4-channel GPIO with LED Driver SX1508QB 8-channel GPIO with LED Driver and Keypad Engine SX1509QB 16-channel GPIO with LED Driver and Keypad Engine 23 26 30 APPLICATION INFORMATION ................................................................................................... 36 6.1 6.2 Typical Application Circuit Typical LED Connection th Rev 3 – 9 Sept. 2010 36 36 2 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 7 PACKAGING INFORMATION ..................................................................................................... 37 7.1 7.2 7.3 7.4 7.5 7.6 QFN-UT 14-pin Outline Drawing QFN-UT 14-pin Land Pattern QFN-UT 20-pin Outline Drawing QFN-UT 20-pin Land Pattern QFN-UT 28-pin Outline Drawing QFN-UT 28-pin Land Pattern 37 37 38 38 39 39 8 SOLDERING PROFILE .............................................................................................................. 40 9 MARKING INFORMATION ......................................................................................................... 41 th Rev 3 – 9 Sept. 2010 3 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 1 1.1 PIN DESCRIPTION 2 SX1507QB 4-channel I C GPIO with LED Driver Pin Symbol Type 1 2 3 4 5 6 SDA SCL NRESET NINT ADDR0 ADDR1 DIO DI DI DO DI DI 7 I/O[0] DIO (*1) 8 I/O[1] DIO (*1) 9 10 VCC1 GND P P 11 I/O[2] DIO (*1) 12 I/O[3] DIO (*1) Description I2C serial data line I2C serial clock line Active low reset input Active low interrupt output Address input bit 0, connect to VDDM or GND Address input bit 1, connect to VDDM or GND I/O[0], at power-on configured as an input LED driver : Intensity control (PWM), Blinking I/O[1], at power-on configured as an input LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) I/O supply voltage Ground Pin I/O[2], at power-on configured as an input LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) I/O[3], at power-on configured as an input LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) Oscillator input/output, can also be used as GPO Main supply voltage 14 OSCIO DIO (*1) 13 VDDM P D/I/O/P: Digital/Input/Output/Power (*1) This pin is programmable through the I2C interface Table 1 – SX1507QB Pin Description Figure 1 – SX1507QB QFN-UT-14 Pinout th Rev 3 – 9 Sept. 2010 4 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 1.2 2 SX1508QB 8-channel I C GPIO with LED Driver and Keypad Engine Pin Symbol Type 1 2 3 4 NRESET SDA SCL ADDR0 DI DIO DI DI 5 I/O[0] DIO (*1) 6 I/O[1] DIO (*1) 7 8 VCC1 GND 9 I/O[2] DIO (*1) 10 I/O[3] DIO (*1) 11 12 13 14 NINT ADDR1 OSCIO VDDM 15 I/O[4] DIO (*1) 16 I/O[5] DIO (*1) 17 18 VCC2 GND 19 I/O[6] DIO (*1) 20 I/O[7] DIO (*1) P P DO DI DIO (*1) P P P Description Active low reset input I2C serial data line I2C serial clock line Address input bit 0, connect to VDDM or GND I/O[0], at power-on configured as an input LED driver : Intensity control (PWM) I/O[1], at power-on configured as an input LED driver : Intensity control (PWM) Supply voltage for Bank A I/O[3-0] Ground Pin I/O[2], at power-on configured as an input LED driver : Intensity control (PWM), Blinking I/O[3], at power-on configured as an input LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) Active low interrupt output Address input bit 1, connect to VDDM or GND Oscillator input/output, can also be used as GPO Main supply voltage I/O[4], at power-on configured as an input LED driver : Intensity control (PWM) I/O[5], at power-on configured as an input LED driver : Intensity control (PWM) Supply voltage for Bank B I/O[7-4] Ground Pin I/O[6], at power-on configured as an input LED driver : Intensity control (PWM), Blinking I/O[7], at power-on configured as an input LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) D/I/O/P: Digital/Input/Output/Power This pin is programmable through the I2C interface (*1) I/O[5] VCC2 GND I/O[6] I/O[7] Table 2 – SX1508QB Pin Description NRESET I/O[4] SDA VDDM SCL OSCIO ADDR0 ADDR1 I/O[3] NINT I/O[2] VCC1 I/O[1] I/O[0] GND GND (PAD) Figure 2 – SX1508QB QFN-UT-20 Pinout th Rev 3 – 9 Sept. 2010 5 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 1.3 2 SX1509QB 16-channel I C GPIO with LED Driver and Keypad Engine Pin Symbol Type Description I/O[2], at power-on configured as an input LED driver : Intensity control (PWM), Blinking I/O[3], at power-on configured as an input 2 I/O[3] DIO (*1) LED driver : Intensity control (PWM), Blinking 3 GND P Ground Pin 4 VCC1 P Supply voltage for Bank A I/O[7-0] I/O[4], at power-on configured as an input (*1) 5 I/O[4] DIO LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) I/O[5], at power-on configured as an input (*1) 6 I/O[5] DIO LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) I/O[6], at power-on configured as an input 7 I/O[6] DIO (*1) LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) I/O[7], at power-on configured as an input 8 I/O[7] DIO (*1) LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) 9 NINT DO Active low interrupt output 10 ADDR1 DI Address input bit 1, connect to VDDM or GND 11 OSCIO DIO (*1) Oscillator input/output, can also be used as GPO 12 VDDM P Main supply voltage I/O[8], at power-on configured as an input (*1) 13 I/O[8] DIO LED driver : Intensity control (PWM), Blinking I/O[9], at power-on configured as an input (*1) 14 I/O[9] DIO LED driver : Intensity control (PWM), Blinking I/O[10], at power-on configured as an input 15 I/O[10] DIO (*1) LED driver : Intensity control (PWM), Blinking I/O[11], at power-on configured as an input (*1) 16 I/O[11] DIO LED driver : Intensity control (PWM), Blinking 17 GND P Ground Pin 18 VCC2 P Supply voltage for Bank B I/O[15-8] I/O[12], at power-on configured as an input (*1) 19 I/O[12] DIO LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) I/O[13], at power-on configured as an input (*1) 20 I/O[13] DIO LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) I/O[14], at power-on configured as an input 21 I/O[14] DIO (*1) LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) I/O[15], at power-on configured as an input (*1) 22 I/O[15] DIO LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out) 23 NRESET DI Active low reset input 24 SDA DIO I2C serial data line 25 SCL DI I2C serial clock line 26 ADDR0 DI Address input bit 0, connect to VDDM or GND I/O[0], at power-on configured as an input (*1) 27 I/O[0] DIO LED driver : Intensity control (PWM), Blinking I/O[1], at power-on configured as an input 28 I/O[1] DIO (*1) LED driver : Intensity control (PWM), Blinking (*1) This pin is programmable through the I2C interface 1 I/O[2] DIO (*1) 22 I/O[15] 23 NRESET 24 SDA 25 SCL 26 ADDR0 27 I/O[0] 28 I/O[1] Table 3 – SX1509QB Pin Description I/O[3] 2 20 I/O[13] TOP VIEW 19 I/O[12] GND (PAD) 18 VCC2 I/O[4] 5 17 GND I/O[5] 6 16 I/O[6] 7 15 ADDR1 10 NINT 9 I/O[7] 8 VCC1 4 I/O[11] I/O[10] I/O[9] 14 GND 3 I/O[8] 13 I/O[14] VDDM 12 21 OSCIO 11 I/O[2] 1 Figure 3 – SX1509QB QFN-UT-28 Pinout th Rev 3 – 9 Sept. 2010 6 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 1.4 I/Os Feature Summary SX1507QB LED Driver I/O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PWM Blink √ √ √ √ √ √ √ √ SX1508QB LED Driver Keypad Breathe √ √ √ PWM √ √ √ √ √ √ √ √ Blink √ √ √ √ Breathe Row √ √ √ √ √ √ Col. √ √ √ √ SX1509QB LED Driver Keypad PWM Blink √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ Breathe Row √ √ √ √ √ √ √ √ √ √ √ √ Col. √ √ √ √ √ √ √ √ √ √ √ √ Table 4 – I/Os Feature Summary Please note that in addition to table above, all I/Os feature bank-to-bank and bank-to-host level shifting. th Rev 3 – 9 Sept. 2010 7 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 2 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings Stress above the limits listed in the following table may cause permanent failure. Exposure to absolute ratings for extended time periods may affect device reliability. The limiting values are in accordance with the Absolute Maximum Rating System (IEC 134). All voltages are referenced to ground (GND). Symbol Description Min Max Unit Vmax_VDDM Vmax_VCC1-2 VES_HBM VES_CDM VES_MM Main supply voltage (SX1507QB) - 0.4 6 V Main supply voltage (SX1508/9QB) - 0.4 3.7 V Digital I/O pin supply voltage (SX1507QB) - 0.4 6 V Digital I/O pin supply voltage (SX1508/9QB) V - 0.4 3.7 (1) - 2000 Electrostatic handling HBM model (SX1509QB) (1) - 1500 Electrostatic handling CDM model - 1000 Electrostatic handling MM model (SX1507/8QB) - 200 Electrostatic handling MM model (SX1509QB) - 150 Electrostatic handling HBM model (SX1507/8QB) V V V TA Operating ambient temperature range -40 +85 °C TC Junction temperature range -40 +125 °C TSTG Storage temperature range -55 +150 °C +/-100 - mA Ilat (2) Latchup-free input pin current (1) Tested according to JESD22-A114A (2) Static latch-up values are valid at maximum temperature according to JEDEC 78 specification Table 5 - Absolute Maximum Ratings 2.2 Electrical Specifications Table below assumes default registers values, unless otherwise specified. Typical values are given for +25°C, VDDM=VCC1=VCC2=3.3V. Symbol Description Conditions Min Typ Max Supply SX1507QB 1.2 5.5 VDDM Main supply voltage SX1508/9QB 1.425 3.6 SX1507QB 1.2 5.5 VCC1,2 I/O banks supply voltage SX1508/9QB 1.2 3.6 Oscillator OFF 1 5 Main supply current Internal osc. (2MHz) TBD TBD 2 (SX1507QB, I C inactive) External osc. (32kHz) 10 Oscillator OFF 1 5 Main supply current IDDM Internal osc. (2MHz) 175 235 2 (SX1508QB, I C inactive) External osc. (32kHz) 10 Oscillator OFF 1 5 Main supply current Internal osc. (2MHz) 365 460 2 (SX1509QB, I C inactive) External osc. (32kHz) 10 (1) ICC1,2 I/O banks supply current 1 2 I/Os set as Input 0.7* (8) VCC1,2 >= 2V 5.5 VCC1,2 VIH High level input voltage 0.8* (8) VCC1,2 < 2V 5.5 VCC1,2 0.3* VCC1,2 >= 2V -0.4 VCC1,2 VIL Low level input voltage 0.2* VCC1,2 < 2V -0.4 VCC1,2 Assuming no active ILEAK Input leakage current -1 1 pull-up/down CI Input capacitance 10 th Rev 3 – 9 Sept. 2010 8 TA = Unit V V µA µA µA µA V V µA pF www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING Symbol Description I/Os set as Output Conditions VOH High level output voltage - VOL Low level output voltage IOH High level output source current IOL Low level output sink current VCC1,2 >= 2V VCC1,2 < 2V VCC1,2 >= 2V VCC1,2 < 2V Cf. Figure 10 tPV Output data valid timing NINT (Output) VOL Low level output voltage IOLM Low level output sink current tIV Interrupt valid timing tIR Interrupt reset timing VDDM >= 2V VDDM < 2V From input data change From RegInterruptSource clearing Min Typ Max Unit - VCC1,2 V - 0.3 (2) 8 (2) 2 (2) 15 (2) 8 425 V -0.4 - - 0.3 8 4 4 mA - - 4 µs VCC1,2 – 0.3 -0.4 - mA mA ns V µs NRESET (Input) VIHMR High level input voltage VILM Low level input voltage ILEAK Input leakage current CI Input capacitance VPOR Power-On-Reset voltage VDROPH High brown-out voltage VDROPL Low brown-out voltage tRESET Reset time tPULSE Reset pulse from host uC ADDR0, ADDR1 (Inputs) VIHMA High level input voltage VILM Low level input voltage ILEAK Input leakage current CI Input capacitance OSCIO (Input/Output) VIHMO High level input voltage VILMO Low level input voltage ILEAK CI VOHM VOL Input leakage current Input capacitance High level output voltage Low level output voltage IOHM High level output source current IOLM Low level output sink current SCL (Input) and SDA (Input/Output) th Rev 3 – 9 Sept. 2010 VDDM >= 2V VDDM < 2V VDDM >= 2V VDDM < 2V Cf. Figure 8 Cf. Figure 8 Cf. Figure 8 Cf. Figure 8 Cf. Figure 8 0.7*VDDM 0.8*VDDM -0.4 -0.4 -1 0.8 VDDM-1 0.2 200 - VDDMmax VDDMmax 0.3*VDDM 0.2*VDDM 1 10 2.5 - VDDM >= 2V VDDM < 2V VDDM >= 2V VDDM < 2V - 0.7*VDDM 0.8*VDDM -0.4 -0.4 -1 - - VDDM+0.3 V VDDM+0.3 0.3*VDDM V 0.2*VDDM 1 µA 10 pF VDDM >= 2V 1.425V =< VDDM < 2V VDDM < 1.425V VDDM >= 2V 1.425V =< VDDM < 2V VDDM < 1.425V VDDM >= 2V VDDM < 2V VDDM >= 2V VDDM < 2V 0.7*VDDM 0.8*VDDM 0.9*VDDM -0.4 -0.4 -0.4 -1 VDDM-0.3 -0.4 - - VDDM+0.3 VDDM+0.3 VDDM+0.3 0.3*VDDM 0.2*VDDM 0.1*VDDM 1 10 VDDM 0.3 8 2 8 4 V V µA pF V V V ms ns V V µA pF V V mA mA (3) 9 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING Symbol Description Conditions Min Typ Max Unit 2 2 Interface complies with slave F/S mode I C interface as described by Philips I C specification version 2.1 2 dated January, 2000. Please refer to that document for more detailed I C specifications. VOL Low level output voltage IOLM Low level output sink current VIHMR High level input voltage VILM Low level input voltage fSCL SCL clock frequency Hold time (repeated) START tHD;STA condition tLOW LOW period of the SCL clock tHIGH HIGH period of the SCL clock Set-up time for a repeated tSU;STA START condition tHD;DAT Data hold time tSU;DAT Data set-up time tr Rise time of both SDA and SCL tf Fall time of both SDA and SCL tSU;STO Set-up time for STOP condition Bus free time between a STOP tBUF and START condition Cb Capacitive load for each bus line Noise margin at the LOW level VnL for each connected device (including hysteresis) Noise margin at the HIGH level VnH for each connected device (including hysteresis) Pulse width of spikes tSP suppressed by the input filter Miscellaneous Programmable pull-up/down RPULL resistors for IO[0-7] fOSC Oscillator frequency VDDM >= 2V VDDM < 2V VDDM >= 2V VDDM < 2V VDDM >= 2V VDDM < 2V - -0.4 0.7*VDDM 0.8*VDDM -0.4 -0.4 - - 0.3 V 8 mA 4 VDDMmax V VDDMmax 0.3*VDDM V 0.2*VDDM 400 kHz - 0.6 - - µs - 1.3 0.6 - - µs µs - 0.6 - - - (4) 0 (6) 100 (7) 20+0.1Cb (7) 20+0.1Cb 0.6 - 0.9 300 300 - µs ns ns ns µs - 1.3 - - µs - - - 400 pF - - 0.1* VDDM - V - - 0.2* VDDM - V - - - 50 ns - - 42 - kΩ Internal (SX1507QB) Internal (SX1508/9QB) External from OSCIN (40-60% duty cycle) 1.1 1.3 2 2 3 2.6 - - 2.6 µs (5) MHz (1) Assuming no load connected to outputs and inputs fixed to VCC1,2 or GND. (2) Can be increased by tying together and driving simultaneously several I/Os. (3) All values referred to VIHMR min and VILM max levels. (4) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to VIHMR min) to bridge the undefined region of the falling edge of SCL. (5) The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW ) of the SCL signal. (6) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max+ tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. (7) Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed. (8) SX1508/9QB: with RegHighInput bit enabled (VCCx min =1.65V), else 3.6V (VCCx min = 1.2V) Table 6 – Electrical Specifications th Rev 3 – 9 Sept. 2010 10 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 3 TYPICAL OPERATING CHARACTERISTICS SX1509QB IDDM vs.VDDM (Oscillator Enabled) SX1509QB IDDM vs.VDDM (Oscillator Enabled) 360 340 340 320 320 300 300 280 280 260 260 I D D M (u A ) ID D M (u A ) 360 240 240 220 220 200 200 180 180 160 160 140 140 120 120 100 100 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 1.3 3.5 1.5 1.7 1.9 2.1 2.3 2.7 2.9 3.1 3.3 3.5 2.7 2.9 3.1 3.3 3.5 Fosc vs. VDDM Fosc vs.Temperature (VDDM = 3.6V) 2.5 2.3 2.3 2.1 2.1 F o s c (M H z ) F o s c (M H z ) 2.5 1.9 1.9 1.7 1.7 1.5 1.5 1.3 1.3 -50 -30 -10 10 30 50 70 1.3 90 1.5 1.7 1.9 2.1 2.3 2.5 VDDM (V) Temp (oC) VOL vs.Temperature (VCCx = 3.6V, IOL = 15mA) VOL vs. IOL (VCCx = 3.6V, Temp 25C) 0.3 0.25 0.25 0.2 0.2 V O L (V ) V O L (V ) 0.3 0.15 0.15 0.1 0.1 0.05 0.05 0 0 0 2 4 6 8 10 12 14 -50 -30 -10 10 IOL (mA) 30 50 70 90 70 90 Temp (oC) VOH vs. IOH (VDDM = 3.6V, Temp 25C) VOH vs. Temperature (VCCx = 3.6V, IOH = 8mA) 3.6 3.6 3.55 3.55 3.5 3.45 V O H (V ) 3.5 3.45 V O H (V ) 2.5 VDDM (V) VDDM (V) 3.4 3.35 3.4 3.35 3.3 3.3 3.25 3.25 3.2 3.2 -8 -7 -6 -5 -4 -3 -2 -1 -50 0 -30 -10 10 30 50 Temp (oC) IOH (mA) Figure 4 – Typical Operating Characteristics th Rev 3 – 9 Sept. 2010 11 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 4 4.1 BLOCK DETAILED DESCRIPTION 2 SX1507QB 4-channel I C GPIO with LED Driver OSCIO Clock Mgmt LED Driver External Clock Intensity (PWM) Blink (Timer) Internal Oscillator Breathe (Ramp) VDDM Reset NRESET 2 I C Bus Control SCL 4-Bit R/W I/O Bank A A Input VCC1 I/O[0] I/O[1] I/O[2] I/O[3] Filter SDA ADDR1 ADDR0 SX1507QB Interrupt NINT GND Figure 5 – 4-channel Low Voltage GPIO with LED Driver 4.2 2 SX1508QB 8-channel I C GPIO with LED Driver and Keypad Engine OSCIO Keypad Engine 16 Keys Max Clock Mgmt LED Driver External Clock Intensity (PWM) Internal Oscillator Breathe (Ramp) Blink (Timer) VDDM I/O Bank A Reset NRESET SCL SDA A 2 I C Bus 8-Bit Control R/W Input I/O Bank B Filter A VCC1 I/O[0] I/O[1] I/O[2] I/O[3] VCC2 I/O[4] I/O[5] I/O[6] I/O[7] ADDR1 ADDR0 SX1508QB Interrupt NINT GND Figure 6 – 8-channel Low Voltage GPIO with LED Driver and Keypad Engine th Rev 3 – 9 Sept. 2010 12 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 4.3 2 SX1509QB 16-channel I C GPIO with LED Driver and Keypad Engine OSCIO Keypad Engine 64 Keys Max Auto Sleep/Wakeup Clock Mgmt LED Driver External Clock Intensity (PWM) Internal Oscillator Breathe (Ramp) Blink (Timer) I/O Bank A VDDM 8-Bit A Reset R/W NRESET 2 I C Bus Control SCL SDA Input 8-Bit Filter R/W I/O Bank B A ADDR1 ADDR0 VCC1 I/O[0] I/O[1] I/O[2] I/O[3] I/O[4] I/O[5] I/O[6] I/O[7] VCC2 I/O[8] I/O[9] I/O[10] I/O[11] I/O[12] I/O[13] I/O[14] I/O[15] SX1509QB Interrupt NINT GND Figure 7 – 16-channel Low Voltage GPIO with LED Driver and Keypad Engine 4.4 Reset 4.4.1 Hardware (NRESET) The SX1507QB, SX1508QB and SX1509QB generate their own power on reset signal after a power supply is connected to the VDDM pin. NRESET input pin can be used to reset the chip anytime, it must be connected to VDDM (or greater) either directly (if not used), or via a resistor. Figure 8 – Power-On / Brown-out Reset Conditions 1. Device behavior is undefined until VDDM rises above VPOR, at which point internal reset procedure is started. 2. After tRESET, the reset procedure is completed. 3. In operation, the SX1507QB, SX1508QB and SX1509QB may be reset (POR like or LED driver counters only depending on RegMisc setting) at anytime by an external device driving NRESET low for tPULSE or longer. Chip can be accessed normally again after NRESET rising edge. th Rev 3 – 9 Sept. 2010 13 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 4. During a brown-out event, if VDDM drops above VDROPH a reset will not occur. 5. During a brown-out event, if VDDM drops between VDROPH and VDROPL a reset may occur. 6. During a brown-out event, if VDDM drops below VDROPL a reset will occur next time VPOR is crossed. Please note that a brown-out event is defined as a transient event on VDDM. If VDDM is attached to a battery, then the gradual decay of the battery voltage will not be interpreted as a brown-out event. Please also note that a sharp rise in VDDM (> 1V/us) may induce a circuit reset. 4.4.2 Software (RegReset) Writing consecutively 0x12 and 0x34 to RegReset register will reset all registers to their default values. 2 4.5 2-Wire Interface (I C) The SX1507QB, SX1508QB and SX1509QB 2-wire interface operates only in slave mode. In this configuration, the device has one or 4 possible devices addresses defined by ADDR[1:0] pins: Device SX1508QB SX1507QB & SX1509QB ADDR[1:0] 00 01 10 11 00 01 10 11 Address Description First address of the 2-wire interface 0x20 (0100000) Second address of the 2-wire interface 0x21 (0100001) Third address of the 2-wire interface 0x22 (0100010) Fourth address of the 2-wire interface 0x23 (0100011) First address of the 2-wire interface 0x3E (0111110) Second address of the 2-wire interface 0x3F (0111111) Third address of the 2-wire interface 0x70 (1110000) Fourth address of the 2-wire interface 0x71 (1110001) Table 7 - 2-Wire Interface Address 2 lines are used to exchange data between an external master host and the slave device: • SCL : Serial CLock • SDA : Serial DAta 2 The SX1507QB, SX1508QB and SX1509QB are read-write slave-mode I C devices and comply with the Philips 2 I C standard Version 2.1 dated January, 2000. The SX1507QB, SX1508QB and SX1509QB have a few useraccessible internal 8-bits registers to set the various parameters of operation (Cf. §5 for detailed configuration 2 registers description). The I C interface has been designed for program flexibility, in that once the slave address has been sent to the SX1507QB, SX1508QB or SX1509QB enabling it to be a slave transmitter/receiver, any register can be written or read independently of each other. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary. Seven bit addressing is used and ten bit addressing is not allowed. Any general call address will be ignored by the SX1507QB, SX1508QB and SX1509QB. The SX1507QB, SX1508QB and SX1509QB are not CBUS compatible and can operate in standard mode (100kbit/s) or fast mode (400kbit/s). 4.5.1 WRITE After the start condition [S], the slave address (SA) is sent, followed by an eighth bit (‘0’) indicating a Write. The slave then Acknowledges [A] that it is being addressed, and the Master sends an 8 bit Data Byte consisting of the slave Register Address (RA). The Slave Acknowledges [A] and the master sends the appropriate 8 bit Data Byte (WD0). Again the slave Acknowledges [A]. In case the master needs to write more data, a succeeding 8 bit Data Byte will follow (WD1), acknowledged by the slave [A]. This sequence will be repeated until the master terminates the transfer with the Stop condition [P]. Figure 9 - 2-Wire Serial Interface, Write Operation th Rev 3 – 9 Sept. 2010 14 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING When successive register data (WD1...WDn) is supplied by the master, the register address can be automatically incremented or kept fixed depending on the setting programmed in RegMisc. 1 tpv Figure 10 – Example: Write RegData Register 4.5.2 READ After the start condition [S], the slave address (SA) is sent, followed by an eighth bit (‘0’) indicating a Write. The slave then Acknowledges [A] that it is being addressed, and the Master responds with an 8 bit Data consisting of the Register Address (RA). The slave Acknowledges [A] and the master sends the Repeated Start Condition [Sr]. Once again, the slave address (SA) is sent, followed by an eighth bit (‘1’) indicating a Read. The slave responds with an Acknowledge [A] and the read Data byte (RD0). If the master needs to read more data it will acknowledge [A] and the slave will send the next read byte (RD1). This sequence can be repeated until the master terminates with a NACK [N] followed by a stop [P]. Figure 11 - 2-Wire Serial Interface, Read Operation When successive register data (RD1...RDn) is read by the master, the register address will be automatically incremented or kept fixed depending on the setting programmed in RegMisc. 4.6 4.6.1 I/O Banks Input Debouncer Each input can be individually debounced by setting corresponding bits in RegDebounce register. At power up the debounce function is disabled. After enabling the debouncer, the change of the input value is accepted only if the input value is identical at two consecutive sampling times. The debounce time common to all IOs can be set in RegDebounceConfig register from 0.5 to 64ms (fOSC = 2MHz). 4.6.2 Keypad Scanning Engine SX1508QB, and SX1509QB integrate a fully programmable keypad scanning engine to implement keypad applications up to 8x8 matrix (i.e. 64 keys). Please note that SX1509QB also implements an Auto Sleep/Wakeup feature to save power consumption when no key has been pressed for a programmed time. th Rev 3 – 9 Sept. 2010 15 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING Y SX1508QB IO3 IO2 IO1 IO0 X IO4 IO5 IO6 IO7 - IO[3-0] as outputs (scanning) - IO[7-4] as inputs RegKeyData = X Y Figure 12 – 4x4 Keypad Connection to SX1508QB Following procedure should be implemented on the host controller for a 4x4 keypad: 1. Set RegDir to 0xF0 (IO[3-0] as outputs, IO[7-4] as inputs) , set RegOpenDrain to 0x0F (IO[3-0] as open-drain outputs), set RegPullup to 0xF0 (pull-ups enabled on inputs IO[7-4]). 2. Enable and configure debouncing on IO[7-4] (RegDebounceEnable = 0xF0, Ex : RegDebounceConfig = 0x05) 3. Enable and configure keypad scanning engine (Ex : RegKeyConfig = 0x7D) This will start an infinite loop with the following sequence to IO[3:0]: ZZZ0, ZZ0Z, Z0ZZ, 0ZZZ. Make sure that scan interval is set to higher value than the debounce time. 4. When a key is pressed, NINT goes low, key scan is halted and the key coordinates are stored in RegKeyData: • The column data will be stored in RegKeyData[7:4] (Note: column indication is active low) • The row data will be stored in RegKeyData[3:0] (Note: row indication is active low) • When RegKeyData is read, this data along with the interrupt is automatically cleared (same behavior as reading RegData) and the key scan continues to the next row. 5. Restart from point 4. This implementation allows the host to handle both single and multi-touches easily (fast AAAAAA sequence is a long press of key A, fast ABABABAB sequence is key A and key B pressed together, etc) 4.6.3 Level Shifter Because of their 5.5V tolerant I/O banks with independent supply voltages between 1.2V and 3.6V, the SX1508QB and SX1509QB can perform level shifting of signals from one I/O bank to another without uC activity by programming the corresponding configuration register bits accordingly in RegLevelShifter (and RegDir). This can save significant BOM cost in a final application where only a few signals need to be level-shifted (no need for an additional external level shifter IC). 1.2-3.6V VCC1 1.2-5.5V IO0 tLevelShiftMin SX1508/9QB 1.2-3.6V 1.2-3.6V VCC2 IO4 th Rev 3 – 9 Sept. 2010 Figure 13 – Level Shifting Example 16 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING The minimum pulse width tLevelShiftMin which can be level shifted properly depends on VCCx and VDDM: tLevelShiftMin = Input Delay + Core Delay + Output Delay Input/Core/Output delays vs VCCx/VDDM are given in figures below. IO Input Delay vs. Supply Voltage 10.000 9.000 8.000 (ns) 6.000 Tdelay 7.000 5.000 4.000 3.000 2.000 1.000 0.000 1.000 1.500 2.000 2.500 3.000 3.500 VCCx (V) Typical Worst Case SX1509QB Digital Core Delay vs. Supply Voltage 26 26 24 24 (ns) 22 22 20 Tdelay (ns) 28 Tdelay SX1508QB Digital Core Delay vs. Supply Voltage 28 20 18 18 16 16 14 14 1 1.5 2 2.5 3 3.5 1 1.5 2 2.5 VDDM (V) Typical Worst Case Typical IO Output Delay vs. Supply Voltage ( LowDriveEn=0, 20pF Load) (ns) 100.000 80.000 80.000 60.000 Tdelay 120.000 100.000 (ns) 120.000 Tdelay 140.000 60.000 40.000 40.000 20.000 20.000 1.500 2.000 2.500 3.000 0.000 1.000 3.500 VCCx (V) Typical 3.5 Worst Case IO Output Delay vs. Supply Voltage (LowDriveEn=1, 20pF Load) 140.000 0.000 1.000 3 VDDM (V) 1.500 2.000 2.500 3.000 3.500 VCCx (V) Worst Case Typical Worst Case Figure 14 – Level Shifter Max Frequency Calculation Data 4.6.4 Polarity Inverter Each IO’s polarity can be individually inverted by setting corresponding bit in RegPolarity register. Please note that polarity inversion can also be combined with level shifting feature. 4.7 Interrupt (NINT) At start-up, the transition detection logic is reset, and NINT is released to a high-impedance state. The interrupt mask register is set to 0xFF, disabling the interrupt output for transitions on all I/O ports. The transition flags are cleared to indicate no data changes. An interrupt NINT can be generated on any programmed combination of I/Os rising and/or falling edges through the RegInterruptMask and RegSense registers. If needed, the I/Os which triggered the interrupt can then be identified by reading RegInterruptSource register. th Rev 3 – 9 Sept. 2010 17 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING When NINT is low (i.e. interrupt occurred), it can be reset back high (i.e. cleared) by writing 0xFF in RegInterruptSource (this will also clear corresponding bits in RegEventStatus register). The interrupt can also be cleared automatically when reading RegData register (Cf. RegMisc) Example: We want to detect rising edge of I/O[1] on SX1508QB (NINT will go low). 1. We enable interrupt on I/O[1] in RegInterruptMask RegInterruptMask =“XXXXXX0X” 2. We set edge sense for I/O[1] in RegSense RegSenseLow =“XXXX01XX” Please note that independently from the “user defined” process described above the keypad engine, when enabled, also uses NINT to indicate a key press. Hence we have NINT = “user defined condition occurred” OR “keypad engine condition occurred”. 4.8 Clock Management A main oscillator clock fOSC is needed by the LED driver, keypad engine and debounce features. Clock management block is illustrated in figure below. OSCIO Clock Mgmt External Clock Div fOSC Internal Oscillator Figure 15 – Clock Management Overview The block is configured in register RegClock (Cf §5 for more detailed information): Selection of internal clock source: none (OFF) or internal oscillator or external clock input from OSCIN. Definition of OSCIO pin function (OSCIN or OSCOUT) OSCOUT frequency setting (sub-multiple of fOSC) Please note that if needed the OSCOUT feature can be used as an additional GPO (Cf. RegClock) 4.9 LED Driver 4.9.1 Overview Every IO has its own independent LED driver (Cf §6.2 for typical LED connection) , all IOs can perform intensity control (PWM) while some of them additionally include blinking and breathing features (Cf pin description §1) The LED drivers of all I/Os share the same clock ClkX configurable in RegMisc[6:4]. Please note that for power consumption reasons ClkX is OFF by default. Assuming ClkX is not OFF, LED driver for IO[X] is enabled when RegLEDDriverEnable[X] = 1 in which case it can operate in one of the three modes below: • Static mode (all I/Os, with or without fade in/out) • Single shot mode (blinking capable I/Os only, with or without fade in/out) • Blink mode (blinking capable I/Os only, with or without fade in/out) th Rev 3 – 9 Sept. 2010 18 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING RegData[X] 1 0 t IO[X] Intensity (PWM value) 100% ON IOnX Fade In Fade Out OFF IOffX 0 TRiseX TOnX TFallX t TOffX Figure 16 – LED Driver Overview Each IO[X] has its own set of programmable registers (Cf §5 for more detailed information): RegTOnX (blinking capable I/Os only): TOnX, ON time of IO[X] RegIOnX (all I/Os): IOnX, ON intensity of IO[X] RegOffX (blinking capable I/Os only): TOffX and IOffX, OFF time and intensity of IO[X] RegTRiseX(breathing capable I/Os only): TRiseX, fade in time of IO[X] RegTFallX(breathing capable I/Os only): TFallX, fade out time of IO[X] Please note that the LED driver mode is selectable for each IO bank between linear and logarithmic. (Cf §4.9.5) All the figures assume normal IO polarity, for inverse polarity RegData control must be inverted (does not invert the polarity of the IO signal itself). 4.9.2 Static Mode Only mode available for non blinking capable IOs (with Off intensity = 0), else invoked when TOnX = 0. If the I/O doesn’t support fading the LED intensity will step directly to the IOnX/IOffX value. RegData(X) On intensity(max) determined by register RegIOnX IOLED(X) level Off intensity(min) determined by register RegIOffX Fade in rate determined by register RegTRiseX Fade out rate determined by register RegTFallX Figure 17 – LED Driver Static Mode 4.9.3 Single Shot Mode Invoked when TOnX != 0 and TOffX = 0. If the I/O doesn’t support fading the LED intensity will step directly to the IOnX/IOffX value. th Rev 3 – 9 Sept. 2010 19 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING RegData(X) On intensity(max) IOLED(X) level Off intensity(min) Fade in rate determined by register RegTRiseX Minimum intensity duration determined by register RegData(x) Fade out rate determined by register RegTFallX Figure 18 – LED Driver Single Shot Mode 4.9.4 Blink Mode Invoked when TOnX != 0 and TOffX != 0. If the I/O doesn’t support fading the LED intensity will step directly to the IOnX/IOffX value. When RegData(X) is cleared, the LED will complete any current ramp, and then stay at minimum intensity RegData(X) On intensity(max) IOLED(X) level Off intensity(min) Fade in rate determined by register RegTRiseX Minimum intensity duration determined by register RegTOffX Maximum intensity duration determined by register RegTOnX Fade out rate determined by register RegTFallX Figure 19 – LED Driver Blink Mode 4.9.5 LED Driver Modes For each IO bank, the LED driver mode of fading capable IOs can be selected between linear or logarithmic in RegMisc. Lin. 0 1 2 3 4 5 6 7 8 9 10 11 12 Log. 0 0 0 0 0 0 0 0 1 1 1 1 1 th Lin. 32 33 34 35 36 37 38 39 40 41 42 43 44 Log. 4 4 4 4 5 5 5 5 6 6 6 6 7 Rev 3 – 9 Sept. 2010 Lin. 64 65 66 67 68 69 70 71 72 73 74 75 76 Log. 13 13 13 13 14 14 14 14 16 16 17 17 18 Lin. 96 97 98 99 100 101 102 103 104 105 106 107 108 Log. 28 28 30 30 31 31 32 32 34 34 35 35 36 Lin. 128 129 130 131 132 133 134 135 136 137 138 139 140 20 Log. 53 53 53 53 56 56 56 56 60 60 60 60 65 Lin. 160 161 162 163 164 165 166 167 168 169 170 171 172 Log. 88 88 88 88 93 93 93 93 98 98 98 98 104 Lin. 192 193 194 195 196 197 198 199 200 201 202 203 204 Log. 135 135 135 135 142 142 142 142 150 150 150 150 157 Lin. 224 225 226 227 228 229 230 231 232 233 234 235 236 Log. 198 198 198 198 207 207 207 207 216 216 216 216 225 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 7 7 7 8 8 8 8 9 9 9 9 10 10 10 10 11 11 12 12 77 18 109 36 141 65 173 104 78 19 110 38 142 65 174 104 79 19 111 38 143 65 175 104 80 20 112 39 144 69 176 110 81 20 113 39 145 69 177 110 82 21 114 41 146 69 178 110 83 21 115 41 147 69 179 110 84 22 116 42 148 73 180 116 85 22 117 42 149 73 181 116 86 23 118 44 150 73 182 116 87 23 119 44 151 73 183 116 88 24 120 46 152 78 184 122 89 24 121 46 153 78 185 122 90 25 122 46 154 78 186 122 91 25 123 46 155 78 187 122 92 26 124 49 156 83 188 129 93 26 125 49 157 83 189 129 94 27 126 49 158 83 190 129 95 27 127 49 159 83 191 129 Table 8 – LED Driver Linear vs Logarithmic Function (I) 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 157 157 157 165 165 165 165 172 172 172 172 181 181 181 181 189 189 189 189 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 225 225 225 235 235 235 235 245 245 245 245 255 255 255 255 255 255 255 255 300 250 IOn (IOff) 200 Linear mode 150 Log mode 100 50 0 1 10 19 28 37 46 55 64 73 82 91 100 109 118 127 136 145 154 163 172 181 190 199 208 217 226 235 244 253 RegIOn (4xRegOff[2:0]) Figure 20 – LED Driver Linear vs Logarithmic Function (II) 4.9.6 Synchronization of LED Drivers across several ICs When several GPIO expanders are used in the same application it may be useful that their LEDs drivers are synchronous for coherent global operation. In this case all ICs should share their fOSC through their OSCIO pins and have their reset connected together. When RegMisc of each IC is set accordingly, NRESET signal can then be used to reset all devices’ internal counters (but not the register settings) and allow synchronous LED operation (blinking, fading) across multiple devices. 4.9.7 Tutorial Below are the steps required to use the LED driver with the typical LED connection described §6.2: - Disable input buffer (RegInputDisable) Disable pull-up (RegPullUp) th Rev 3 – 9 Sept. 2010 21 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING - Enable open drain (RegOpenDrain) Set direction to output (RegDir) – by default RegData is set high => LED OFF Enable oscillator (RegClock) Configure LED driver clock and mode if relevant (RegMisc) Enable LED driver operation (RegLEDDriverEnable) Configure LED driver parameters (RegTOn, RegIOn, RegOff, RegTRise, RegTFall) Set RegData bit low => LED driver started th Rev 3 – 9 Sept. 2010 22 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 5 5.1 CONFIGURATION REGISTERS SX1507QB 4-channel GPIO with LED Driver Address Name Description Device and IO Banks 0x00 RegInputDisable 0x01 RegLongSlew 0x02 RegLowDrive 0x03 RegPullUp 0x04 RegPullDown 0x05 RegOpenDrain 0x06 RegPolarity 0x07 RegDir 0x08 RegData 0x09 RegInterruptMask 0x0A RegSense 0x0B RegInterruptSource 0x0C RegEventStatus 0x0D RegClock 0x0E RegMisc 0x0F RegLEDDriverEnable Debounce 0x10 RegDebounceConfig 0x11 RegDebounceEnable LED Driver (PWM, blinking, breathing) 0x12 RegTOn0 0x13 RegIOn0 0x14 RegOff0 0x15 RegTOn1 0x16 RegIOn1 0x17 RegOff1 0x18 RegTRise1 0x19 RegTFall1 0x1A RegTOn2 0x1B RegIOn2 0x1C RegOff2 0x1D RegTRise2 0x1E RegTFall2 0x1F RegTOn3 0x20 RegIOn3 0x21 RegOff3 0x22 RegTRise3 0x23 RegTFall3 Software Reset 0x7D RegReset Test (not to be written) 0x7E RegTest1 0x7F RegTest2 Default Input buffer disable register Output buffer long slew register Output buffer low drive register Pull-up register Pull-down register Open drain register Polarity register Direction register Data register Interrupt mask register Sense register Interrupt source register Event status register Clock management register Miscellaneous device settings register LED driver enable register XXXX 0000 XXXX 0000 XXXX 0000 XXXX 0000 XXXX 0000 XXXX 0000 XXXX 0000 XXXX 1111 XXXX 1111* XXXX 1111 0000 0000 XXXX 0000 XXXX 0000 0000 0000 0000 0000 XXXX 0000 Debounce configuration register Debounce enable register 0000 0000 XXXX 0000 ON time register for I/O[0] ON intensity register for I/O[0] OFF time/intensity register for I/O[0] ON time register for I/O[1] ON intensity register for I/O[1] OFF time/intensity register for I/O[1] Fade in register for I/O[1] Fade out register for I/O[1] ON time register for I/O[2] ON intensity register for I/O[2] OFF time/intensity register for I/O[2] Fade in register for I/O[2] Fade out register for I/O[2] ON time register for I/O[3] ON intensity register for I/O[3] OFF time/intensity register for I/O[3] Fade in register for I/O[3] Fade out register for I/O[3] 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 Software reset register 0000 0000 Test register Test register 0000 0000 0000 0000 *Bits set as output take “1” as default value. Table 9 – SX1507QB Configuration Registers Overview th Rev 3 – 9 Sept. 2010 23 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING Addr Name Default Bits 7:4 0x00 RegInputDisable 0xX0 3:0 7:4 0x01 RegLongSlew 0xX0 0x02 RegLowDrive 0xX0 0x03 RegPullUp 0xX0 0x04 RegPullDown 0xX0 0x05 RegOpenDrain 0xX0 3:0 7:4 3:0 7:4 3:0 7:4 3:0 7:4 3:0 7:4 0x06 RegPolarity 0xX0 0x07 RegDir 0xXF 0x08 RegData 0xXF 0x09 RegInterruptMask 0xXF 0x0A RegSense 0x00 0x0B RegInterruptSource 0xX0 3:0 7:4 3:0 7:4 3:0 7:4 3:0 7:6 5:4 3:2 1:0 7:4 3:0 7:4 0x0C RegEventStatus 0xX0 3:0 7 6:5 0x0D RegClock 0x00 4 3:0 th Rev 3 – 9 Sept. 2010 Description Unused Disables the input buffer of each IO 0 : Input buffer is enabled (input actually being used) 1 : Input buffer is disabled (input actually not being used or LED connection) Unused Enables increased slew rate of the output buffer of each [output-configured] IO 0 : Increased slew rate is disabled 1 : Increased slew rate is enabled Unused Enables reduced drive of the output buffer of each [output-configured] IO 0 : Reduced drive is disabled 1 : Reduced drive is enabled. IOL specifications are divided by 2. Unused Enables the pull-up for each IO 0 : Pull-up is disabled 1 : Pull-up is enabled Unused Enables the pull-down for each IO 0 : Pull-down is disabled 1 : Pull-down is enabled Unused Enables open drain operation for each [output-configured] IO 0 : Regular push-pull operation 1 : Open drain operation Unused Enables polarity inversion for each IO 0 : Normal polarity : RegData[x] = IO[x] 1 : Inverted polarity : RegData[x] = !IO[x] (for both input and output configured IOs) Unused Configures direction for each IO. 0 : IO is configured as an output 1 : IO is configured as an input Unused Write: Data to be output to the output-configured IOs Read: Data seen at the IOs, independent of the direction configured. Unused Configures which [input-configured] IO will trigger an interrupt on NINT pin 0 : An event on this IO will trigger an interrupt 1 : An event on this IO will NOT trigger an interrupt Edge sensitivity of RegData[3] 00 : None Edge sensitivity of RegData[2] 01 : Rising 10 : Falling Edge sensitivity of RegData[1] 11 : Both Edge sensitivity of RegData[0] Unused Interrupt source (from IOs set in RegInterruptMask) 0 : No interrupt has been triggered by this IO 1 : An interrupt has been triggered by this IO (an event as configured in relevant RegSense register occured). Writing '1' clears the bit in RegInterruptSource and in RegEventStatus When all bits are cleared, NINT signal goes back high. Unused Event status of all IOs. 0 : No event has occured on this IO 1 : An event has occured on this IO (an edge as configured in relevant RegSense register occured). Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant. If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically Unused Oscillator frequency (fOSC) source 00 : OFF. LED driver and debounce features are disabled. 01 : External clock input (OSCIN) 10 : Internal 1MHz oscillator 11 : Reserved OSCIO pin function (Cf. §4.8) 0 : OSCIO is an input (OSCIN) 1 : OSCIO is an output (OSCOUT) Frequency of the signal output on OSCOUT pin: 0x0 : 0Hz, permanent "0" logical level (GPO) 0xF : 0Hz, permanent "1" logical level (GPO) Else : fOSCOUT = fOSC/(2^(RegClock[3:0]-1)) 24 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 7 6:4 3 0x0E RegMisc 0x00 2 1 0 7:4 0x0F RegLEDDriverEnable 0xX0 3:0 7:3 0x10 RegDebounceConfig 0x00 2:0 7:4 0x11 RegDebounceEnable 0xX0 3:0 7:5 0xXX RegTOnX 0x00 0xXX RegIOnX 0xFF 4:0 7:0 7:3 0xXX RegOffX 0x00 2:0 7:5 0xXX RegTRiseX 0x00 4:0 7:5 0xXX RegTFallX 0x00 0x7D RegReset 0x00 4:0 7:0 Unused Frequency of the LED Driver clock ClkX of all IOs: 0 : OFF. LED driver functionality is disabled for all IOs. Else : ClkX = fOSC/(2^(RegMisc[6:4]-1)) LED Driver mode for Bank A ‘s fading capable IOs (IO1-3) 0: Linear 1: Logarithmic NRESET pin function when externally forced low (Cf. §4.4.1 and §4.9.5). 0: Equivalent to POR 1: Reset PWM/Blink/Fade counters (not user programmed values) This bit is can only be reset manually or by POR, not by NRESET. Auto-increment register address (Cf. §4.5) 0: ON. When several consecutive data are read/written, register address is incremented. 1: OFF. When several consecutive data are read/written, register address is kept fixed. Autoclear NINT on RegData read (Cf. §4.7) 0: ON. RegInterruptSource is also automatically cleared when RegData is read. 1: OFF. RegInterruptSource must be manually cleared, either directly or via RegEventStatus. Unused Enables LED Driver for each [output-configured] IO 0 : LED Driver is disabled 1 : LED Driver is enabled Unused Debounce time (Cf. §4.6.1) 000: 0.5ms x 1MHz/fOSC 001: 1ms x 1MHz/fOSC 010: 2ms x 1MHz/fOSC 011: 4ms x 1MHz/fOSC 100: 8ms x 1MHz/fOSC 101: 16ms x 1MHz/fOSC 110: 32ms x 1MHz/fOSC 111: 64ms x 1MHz/fOSC Unused Enables debouncing for each [input-configured] IO 0 : Debouncing is disabled 1 : Debouncing is enabled Unused ON Time of IO[X]: 0 : Infinite (Static mode, TOn directly controlled by RegData, Cf §4.9.2) 1 - 15 : TOnX = 64 * RegTOnX * (255/ClkX) 16 - 31 : TOnX = 512 * RegTOnX * (255/ClkX) ON Intensity of IO[X] - Linear mode : IOnX = RegIOnX - Logarithmic mode (fading capable IOs only) : IOnX = f(RegIOnX) , Cf §4.9.5 OFF Time of IO[X]: 0 : Infinite (Single shot mode, TOff directly controlled by RegData, Cf §4.9.3) 1 - 15 : TOffX = 64 * RegOffX[7:3] * (255/ClkX) 16 - 31 : TOffX = 512 * RegOffX[7:3] * (255/ClkX) OFF Intensity of IO[X] - Linear mode : IOffX = 4 x RegOff[2:0] - Logarithmic mode (fading capable IOs only) : IOffX = f(4 x RegOffX[2:0]) , Cf §4.9.5 Unused Fade In setting of IO[X] 0 : OFF 1 - 15 : TRiseX = (RegIOnX-(4xRegOffX[2:0])) * RegTRiseX * (255/ClkX) 16 - 31 : TRiseX = 16 * (RegIOnX-(4xRegOffX[2:0])) * RegTRiseX * (255/ClkX) Unused Fade Out setting of IO[X] 0 : OFF 1 - 15 : TFallX = (RegIOnX-(4xRegOffX[2:0])) * RegTFallX * (255/ClkX) 16 - 31 : TFallX = 16 * (RegIOnX-(4xRegOffX[2:0])) * RegTFallX * (255/ClkX) Software reset register Writing consecutively 0x12 and 0x34 will reset the device (same as POR). Always reads 0. Table 10 – SX1507QB Configuration Registers Description th Rev 3 – 9 Sept. 2010 25 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 5.2 SX1508QB 8-channel GPIO with LED Driver and Keypad Engine Address Name Description Device and IO Banks 0x00 RegInputDisable 0x01 RegLongSlew 0x02 RegLowDrive 0x03 RegPullUp 0x04 RegPullDown 0x05 RegOpenDrain 0x06 RegPolarity 0x07 RegDir 0x08 RegData 0x09 RegInterruptMask 0x0A RegSenseHigh 0x0B RegSenseLow 0x0C RegInterruptSource 0x0D RegEventStatus 0x0E RegLevelShifter 0x0F RegClock 0x10 RegMisc 0x11 RegLEDDriverEnable Debounce and Keypad Engine 0x12 RegDebounceConfig 0x13 RegDebounceEnable 0x14 RegKeyConfig 0x15 RegKeyData LED Driver (PWM, blinking, breathing) 0x16 RegIOn0 0x17 RegIOn1 0x18 RegTOn2 0x19 RegIOn2 0x1A RegOff2 0x1B RegTOn3 0x1C RegIOn3 0x1D RegOff3 0x1E RegTRise3 0x1F RegTFall3 0x20 RegIOn4 0x21 RegIOn5 0x22 RegTOn6 0x23 RegIOn6 0x24 RegOff6 0x25 RegTOn7 0x26 RegIOn7 0x27 RegOff7 0x28 RegTRise7 0x29 RegTFall7 Miscellaneous 0x2A RegHighInput Software Reset 0x7D RegReset Test (not to be written) 0x7E RegTest1 0x7F RegTest2 Default Input buffer disable register Output buffer long slew register Output buffer low drive register Pull-up register Pull-down register Open drain register Polarity register Direction register Data register Interrupt mask register Sense register for I/O[7:4] Sense register for I/O[3:0] Interrupt source register Event status register Level shifter register Clock management register Miscellaneous device settings register LED driver enable register 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111* 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Debounce configuration register Debounce enable register Key scan configuration register Key value 0000 0000 0000 0000 0000 0000 1111 1111 ON intensity register for I/O[0] ON intensity register for I/O[1] ON time register for I/O[2] ON intensity register for I/O[2] OFF time/intensity register for I/O[2] ON time register for I/O[3] ON intensity register for I/O[3] OFF time/intensity register for I/O[3] Fade in register for I/O[3] Fade out register for I/O[3] ON intensity register for I/O[4] ON intensity register for I/O[5] ON time register for I/O[6] ON intensity register for I/O[6] OFF time/intensity register for I/O[6] ON time register for I/O[7] ON intensity register for I/O[7] OFF time/intensity register for I/O[7] Fade in register for I/O[7] Fade out register for I/O[7] 1111 1111 1111 1111 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 High input enable register 0000 0000 Software reset register 0000 0000 Test register Test register 0000 0000 0000 0000 *Bits set as output take “1” as default value. Table 11 – SX1508QB Configuration Registers Overview th Rev 3 – 9 Sept. 2010 26 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING Addr Name Default Bits 7:6 5:4 3:2 1:0 7:6 5:4 3:2 1:0 Disables the input buffer of each IO 0 : Input buffer is enabled (input actually being used) 1 : Input buffer is disabled (input actually not being used or LED connection) Enables increased slew rate of the output buffer of each [output-configured] IO 0 : Increased slew rate is disabled 1 : Increased slew rate is enabled Enables reduced drive of the output buffer of each [output-configured] IO 0 : Reduced drive is disabled 1 : Reduced drive is enabled. IOL specifications are divided by 2. Enables the pull-up for each IO 0 : Pull-up is disabled 1 : Pull-up is enabled Enables the pull-down for each IO 0 : Pull-down is disabled 1 : Pull-down is enabled Enables open drain operation for each [output-configured] IO 0 : Regular push-pull operation 1 : Open drain operation Enables polarity inversion for each IO 0 : Normal polarity : RegData[x] = IO[x] 1 : Inverted polarity : RegData[x] = !IO[x] (for both input and output configured IOs) Configures direction for each IO. 0 : IO is configured as an output 1 : IO is configured as an input Write: Data to be output to the output-configured IOs Read: Data seen at the IOs, independent of the direction configured. Configures which [input-configured] IO will trigger an interrupt on NINT pin 0 : An event on this IO will trigger an interrupt 1 : An event on this IO will NOT trigger an interrupt Edge sensitivity of RegData[7] 00 : None Edge sensitivity of RegData[6] 01 : Rising 10 : Falling Edge sensitivity of RegData[5] 11 : Both Edge sensitivity of RegData[4] Edge sensitivity of RegData[3] 00 : None Edge sensitivity of RegData[2] 01 : Rising 10 : Falling Edge sensitivity of RegData[1] 11 : Both Edge sensitivity of RegData[0] 7:0 Interrupt source (from IOs set in RegInterruptMask) 0 : No interrupt has been triggered by this IO 1 : An interrupt has been triggered by this IO (an event as configured in relevant RegSense register occured). 7:0 Writing '1' clears the bit in RegInterruptSource and in RegEventStatus When all bits are cleared, NINT signal goes back high. Event status of all IOs. 0 : No event has occured on this IO 1 : An event has occured on this IO (an edge as configured in relevant RegSense register occured). 0x00 RegInputDisable 0x00 7:0 0x01 RegLongSlew 0x00 7:0 0x02 RegLowDrive 0x00 7:0 0x03 RegPullUp 0x00 7:0 0x04 RegPullDown 0x00 7:0 0x05 RegOpenDrain 0x00 7:0 0x06 RegPolarity 0x00 7:0 0x07 RegDir 0xFF 7:0 0x08 RegData 0xFF 7:0 0x09 RegInterruptMask 0xFF 7:0 0x0A RegSenseHigh 0x00 0x0B RegSenseLow 0x00 0x0C 0x0D 0x0E RegInterruptSource RegEventStatus RegLevelShifter 0x00 0x00 0x00 7:6 5:4 3:2 1:0 7 6:5 0x0F RegClock 0x00 4 3:0 0x10 RegMisc th Rev 3 – 9 Sept. 2010 0x00 Description 7 Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant. If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically Level shifter mode for IO[3] (Bank A) and IO[7] (Bank B) 00 : OFF 01 : A->B Level shifter mode for IO[2] (Bank A) and IO[6] (Bank B) 10 : B->A Level shifter mode for IO[1] (Bank A) and IO[5] (Bank B) 11 : Reserved Level shifter mode for IO[0] (Bank A) and IO[4] (Bank B) Unused Oscillator frequency (fOSC) source 00 : OFF. LED driver, keypad engine and debounce features are disabled. 01 : External clock input (OSCIN) 10 : Internal 2MHz oscillator 11 : Reserved OSCIO pin function (Cf. §4.8) 0 : OSCIO is an input (OSCIN) 1 : OSCIO is an output (OSCOUT) Frequency of the signal output on OSCOUT pin: 0x0 : 0Hz, permanent "0" logical level (GPO) 0xF : 0Hz, permanent "1" logical level (GPO) Else : fOSCOUT = fOSC/(2^(RegClock[3:0]-1)) LED Driver mode for Bank B ‘s fading capable IOs (IO7) 0: Linear 1: Logarithmic 27 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 6:4 3 2 1 0 0x11 RegLEDDriverEnable 0x00 7:0 7:3 0x12 RegDebounceConfig 0x00 0x13 RegDebounceEnable 0x00 2:0 7:0 7 6:5 4:3 0x14 RegKeyConfig 0x00 2:0 0x15 RegKeyData 0xFF 7:0 7:5 0xXX RegTOnX 0x00 0xXX RegIOnX 0xFF 0xXX RegOffX 0x00 4:0 7:0 7:3 2:0 7:5 0xXX RegTRiseX th Rev 3 – 9 Sept. 2010 0x00 4:0 Frequency of the LED Driver clock ClkX of all IOs: 0 : OFF. LED driver functionality is disabled for all IOs. Else : ClkX = fOSC/(2^(RegMisc[6:4]-1)) LED Driver mode for Bank A ‘s fading capable IOs (IO3) 0: Linear 1: Logarithmic NRESET pin function when externally forced low (Cf. §4.4.1 and §4.9.5). 0: Equivalent to POR 1: Reset PWM/Blink/Fade counters (not user programmed values) This bit is can only be reset manually or by POR, not by NRESET. Auto-increment register address (Cf. §4.5) 0: ON. When several consecutive data are read/written, register address is incremented. 1: OFF. When several consecutive data are read/written, register address is kept fixed. Autoclear NINT on RegData read (Cf. §4.7) 0: ON. RegInterruptSource is also automatically cleared when RegData is read. 1: OFF. RegInterruptSource must be manually cleared, either directly or via RegEventStatus. Enables LED Driver for each [output-configured] IO 0 : LED Driver is disabled 1 : LED Driver is enabled Unused Debounce time (Cf. §4.6.1) 000: 0.5ms x 2MHz/fOSC 001: 1ms x 2MHz/fOSC 010: 2ms x 2MHz/fOSC 011: 4ms x 2MHz/fOSC 100: 8ms x 2MHz/fOSC 101: 16ms x 2MHz/fOSC 110: 32ms x 2MHz/fOSC 111: 64ms x 2MHz/fOSC Enables debouncing for each [input-configured] IO 0 : Debouncing is disabled 1 : Debouncing is enabled Unused Number of rows (outputs) + key scan enable 00 : Key scan OFF 01 : 2 rows – IO[0:1] 10 : 3 rows – IO[0:2] 11 : 4 rows – IO[0:3] Number of columns (inputs) 00 : 1 column – IO[4] 01 : 2 columns – IO[4:5] 10 : 3 columns – IO[4:6] 11 : 4 columns – IO[4:7] Scan time per row (must be set above debounce time). 000 : 1ms x 2MHz/fOSC 001 : 2ms x 2MHz/fOSC 010 : 4ms x 2MHz/fOSC 011 : 8ms x 2MHz/fOSC 100 : 16ms x 2MHz/fOSC 101 : 32ms x 2MHz/fOSC 110 : 64ms x 2MHz/fOSC 111 : 128ms x 2MHz/fOSC Key which generated NINT (active low) Ex: RegKeyData=11011110 => key [IO5;IO0] has been pressed and generated NINT When read it is automatically cleared together with NINT and key scan continues. Unused ON Time of IO[X]: 0 : Infinite (Static mode, TOn directly controlled by RegData, Cf §4.9.2) 1 - 15 : TOnX = 64 * RegTOnX * (255/ClkX) 16 - 31 : TOnX = 512 * RegTOnX * (255/ClkX) ON Intensity of IO[X] - Linear mode : IOnX = RegIOnX - Logarithmic mode (fading capable IOs only) : IOnX = f(RegIOnX) , Cf §4.9.5 OFF Time of IO[X]: 0 : Infinite (Single shot mode, TOff directly controlled by RegData, Cf §4.9.3) 1 - 15 : TOffX = 64 * RegOffX[7:3] * (255/ClkX) 16 - 31 : TOffX = 512 * RegOffX[7:3] * (255/ClkX) OFF Intensity of IO[X] - Linear mode : IOffX = 4 x RegOff[2:0] - Logarithmic mode (fading capable IOs only) : IOffX = f(4 x RegOffX[2:0]) , Cf §4.9.5 Unused Fade In setting of IO[X] 0 : OFF 1 - 15 : TRiseX = (RegIOnX-(4xRegOffX[2:0])) * RegTRiseX * (255/ClkX) 16 - 31 : TRiseX = 16 * (RegIOnX-(4xRegOffX[2:0])) * RegTRiseX * (255/ClkX) 28 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 7:5 0xXX RegTFallX 0x00 0x2A RegHighInput 0x00 7:0 0x7D RegReset 0x00 7:0 4:0 Unused Fade Out setting of IO[X] 0 : OFF 1 - 15 : TFallX = (RegIOnX-(4xRegOffX[2:0])) * RegTFallX * (255/ClkX) 16 - 31 : TFallX = 16 * (RegIOnX-(4xRegOffX[2:0])) * RegTFallX * (255/ClkX) Enables high input mode for each [input-configured] IO 0 : OFF. VIH max = 3.6V and VCCx min = 1.2V 1 : ON. VIH max = 5.5V and VCCx min = 1.65V Software reset register Writing consecutively 0x12 and 0x34 will reset the device (same as POR). Always reads 0. Table 12 – SX1508QB Configuration Registers Description th Rev 3 – 9 Sept. 2010 29 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 5.3 SX1509QB 16-channel GPIO with LED Driver and Keypad Engine Address Name Device and IO Banks 0x00 RegInputDisableB 0x01 RegInputDisableA 0x02 RegLongSlewB 0x03 RegLongSlewA 0x04 RegLowDriveB 0x05 RegLowDriveA 0x06 RegPullUpB 0x07 RegPullUpA 0x08 RegPullDownB 0x09 RegPullDownA 0x0A RegOpenDrainB 0x0B RegOpenDrainA 0x0C RegPolarityB 0x0D RegPolarityA 0x0E RegDirB 0x0F RegDirA 0x10 RegDataB 0x11 RegDataA 0x12 RegInterruptMaskB 0x13 RegInterruptMaskA 0x14 RegSenseHighB 0x15 RegSenseLowB 0x16 RegSenseHighA 0x17 RegSenseLowA 0x18 RegInterruptSourceB 0x19 RegInterruptSourceA 0x1A RegEventStatusB 0x1B RegEventStatusA 0x1C RegLevelShifter1 0x1D RegLevelShifter2 0x1E RegClock 0x1F RegMisc 0x20 RegLEDDriverEnableB 0x21 RegLEDDriverEnableA Debounce and Keypad Engine 0x22 RegDebounceConfig 0x23 RegDebounceEnableB 0x24 RegDebounceEnableA 0x25 RegKeyConfig1 0x26 RegKeyConfig2 0x27 RegKeyData1 0x28 RegKeyData2 LED Driver (PWM, blinking, breathing) 0x29 RegTOn0 0x2A RegIOn0 0x2B RegOff0 0x2C RegTOn1 0x2D RegIOn1 0x2E RegOff1 0x2F RegTOn2 0x30 RegIOn2 0x31 RegOff2 0x32 RegTOn3 0x33 RegIOn3 0x34 RegOff3 0x35 RegTOn4 0x36 RegIOn4 0x37 RegOff4 0x38 RegTRise4 th Rev 3 – 9 Sept. 2010 Description Default Input buffer disable register - I/O[15-8] (Bank B) Input buffer disable register - I/O[7-0] (Bank A) Output buffer long slew register - I/O[15-8] (Bank B) Output buffer long slew register - I/O[7-0] (Bank A) Output buffer low drive register - I/O[15-8] (Bank B) Output buffer low drive register - I/O[7-0] (Bank A) Pull-up register - I/O[15-8] (Bank B) Pull-up register - I/O[7-0] (Bank A) Pull-down register - I/O[15-8] (Bank B) Pull-down register - I/O[7-0] (Bank A) Open drain register - I/O[15-8] (Bank B) Open drain register - I/O[7-0] (Bank A) Polarity register - I/O[15-8] (Bank B) Polarity register - I/O[7-0] (Bank A) Direction register - I/O[15-8] (Bank B) Direction register - I/O[7-0] (Bank A) Data register - I/O[15-8] (Bank B) Data register - I/O[7-0] (Bank A) Interrupt mask register - I/O[15-8] (Bank B) Interrupt mask register - I/O[7-0] (Bank A) Sense register for I/O[15:12] Sense register for I/O[11:8] Sense register for I/O[7:4] Sense register for I/O[3:0] Interrupt source register - I/O[15-8] (Bank B) Interrupt source register - I/O[7-0] (Bank A) Event status register - I/O[15-8] (Bank B) Event status register - I/O[7-0] (Bank A) Level shifter register Level shifter register Clock management register Miscellaneous device settings register LED driver enable register - I/O[15-8] (Bank B) LED driver enable register - I/O[7-0] (Bank A) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111* 1111 1111* 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Debounce configuration register Debounce enable register - I/O[15-8] (Bank B) Debounce enable register - I/O[7-0] (Bank A) Key scan configuration register Key scan configuration register Key value (column) Key value (row) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 ON time register for I/O[0] ON intensity register for I/O[0] OFF time/intensity register for I/O[0] ON time register for I/O[1] ON intensity register for I/O[1] OFF time/intensity register for I/O[1] ON time register for I/O[2] ON intensity register for I/O[2] OFF time/intensity register for I/O[2] ON time register for I/O[3] ON intensity register for I/O[3] OFF time/intensity register for I/O[3] ON time register for I/O[4] ON intensity register for I/O[4] OFF time/intensity register for I/O[4] Fade in register for I/O[4] 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 30 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING Address Name 0x39 RegTFall4 0x3A RegTOn5 0x3B RegIOn5 0x3C RegOff5 0x3D RegTRise5 0x3E RegTFall5 0x3F RegTOn6 0x40 RegIOn6 0x41 RegOff6 0x42 RegTRise6 0x43 RegTFall6 0x44 RegTOn7 0x45 RegIOn7 0x46 RegOff7 0x47 RegTRise7 0x48 RegTFall7 0x49 RegTOn8 0x4A RegIOn8 0x4B RegOff8 0x4C RegTOn9 0x4D RegIOn9 0x4E RegOff9 0x4F RegTOn10 0x50 RegIOn10 0x51 RegOff10 0x52 RegTOn11 0x53 RegIOn11 0x54 RegOff11 0x55 RegTOn12 0x56 RegIOn12 0x57 RegOff12 0x58 RegTRise12 0x59 RegTFall12 0x5A RegTOn13 0x5B RegIOn13 0x5C RegOff13 0x5D RegTRise13 0x5E RegTFall13 0x5F RegTOn14 0x60 RegIOn14 0x61 RegOff14 0x62 RegTRise14 0x63 RegTFall14 0x64 RegTOn15 0x65 RegIOn15 0x66 RegOff15 0x67 RegTRise15 0x68 RegTFall15 Miscellaneous 0x69 RegHighInputB 0x6A RegHighInputA Software Reset 0x7D RegReset Test (not to be written) 0x7E RegTest1 0x7F RegTest2 Description Default Fade out register for I/O[4] ON time register for I/O[5] ON intensity register for I/O[5] OFF time/intensity register for I/O[5] Fade in register for I/O[5] Fade out register for I/O[5] ON time register for I/O[6] ON intensity register for I/O[6] OFF time/intensity register for I/O[6] Fade in register for I/O[6] Fade out register for I/O[6] ON time register for I/O[7] ON intensity register for I/O[7] OFF time/intensity register for I/O[7] Fade in register for I/O[7] Fade out register for I/O[7] ON time register for I/O[8] ON intensity register for I/O[8] OFF time/intensity register for I/O[8] ON time register for I/O[9] ON intensity register for I/O[9] OFF time/intensity register for I/O[9] ON time register for I/O[10] ON intensity register for I/O[10] OFF time/intensity register for I/O[10] ON time register for I/O[11] ON intensity register for I/O[11] OFF time/intensity register for I/O[11] ON time register for I/O[12] ON intensity register for I/O[12] OFF time/intensity register for I/O[12] Fade in register for I/O[12] Fade out register for I/O[12] ON time register for I/O[13] ON intensity register for I/O[13] OFF time/intensity register for I/O[13] Fade in register for I/O[13] Fade out register for I/O[13] ON time register for I/O[14] ON intensity register for I/O[14] OFF time/intensity register for I/O[14] Fade in register for I/O[14] Fade out register for I/O[14] ON time register for I/O[15] ON intensity register for I/O[15] OFF time/intensity register for I/O[15] Fade in register for I/O[15] Fade out register for I/O[15] 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 High input enable register - I/O[15-8] (Bank B) High input enable register - I/O[7-0] (Bank A) 0000 0000 0000 0000 Software reset register 0000 0000 Test register Test register 0000 0000 0000 0000 *Bits set as output take “1” as default value. Table 13 – SX1509QB Configuration Registers Overview th Rev 3 – 9 Sept. 2010 31 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING Addr Name Default Bits 0x00 RegInputDisableB 0x00 7:0 0x01 RegInputDisableA 0x00 7:0 0x02 RegLongSlewB 0x00 7:0 0x03 RegLongSlewA 0x00 7:0 0x04 RegLowDriveB 0x00 7:0 0x05 RegLowDriveA 0x00 7:0 0x06 RegPullUpB 0x00 7:0 0x07 RegPullUpA 0x00 7:0 0x08 RegPullDownB 0x00 7:0 0x09 RegPullDownA 0x00 7:0 0x0A RegOpenDrainB 0x00 7:0 0x0B RegOpenDrainA 0x00 7:0 0x0C RegPolarityB 0x00 7:0 0x0D RegPolarityA 0x00 7:0 0x0E RegDirB 0xFF 7:0 0x0F RegDirA 0xFF 7:0 0x10 RegDataB 0xFF 7:0 0x11 RegDataA 0xFF 7:0 0x12 RegInterruptMaskB 0xFF 7:0 0x13 RegInterruptMaskA 0xFF 7:0 0x14 0x15 RegSenseHighB RegSenseLowB 0x00 0x00 0x16 RegSenseHighA 0x00 0x17 RegSenseLowA 0x00 th Rev 3 – 9 Sept. 2010 7:6 5:4 3:2 1:0 7:6 5:4 3:2 1:0 7:6 5:4 3:2 1:0 7:6 Description Disables the input buffer of each IO 0 : Input buffer is enabled (input actually being used) 1 : Input buffer is disabled (input actually not being used or LED connection) Disables the input buffer of each IO 0 : Input buffer is enabled (input actually being used) 1 : Input buffer is disabled (input actually not being used, LED connection) Enables increased slew rate of the output buffer of each [output-configured] IO 0 : Increased slew rate is disabled 1 : Increased slew rate is enabled Enables increased slew rate of the output buffer of each [output-configured] IO 0 : Increased slew rate is disabled 1 : Increased slew rate is enabled Enables reduced drive of the output buffer of each [output-configured] IO 0 : Reduced drive is disabled 1 : Reduced drive is enabled. IOL specifications are divided by 2. Enables reduced drive of the output buffer of each [output-configured] IO 0 : Reduced drive is disabled 1 : Reduced drive is enabled. IOL specifications are divided by 2. Enables the pull-up for each IO 0 : Pull-up is disabled 1 : Pull-up is enabled Enables the pull-up for each IO 0 : Pull-up is disabled 1 : Pull-up is enabled Enables the pull-down for each IO 0 : Pull-down is disabled 1 : Pull-down is enabled Enables the pull-down for each IO 0 : Pull-down is disabled 1 : Pull-down is enabled Enables open drain operation for each [output-configured] IO 0 : Regular push-pull operation 1 : Open drain operation Enables open drain operation for each [output-configured] IO 0 : Regular push-pull operation 1 : Open drain operation Enables polarity inversion for each IO 0 : Normal polarity : RegData[x] = IO[x] 1 : Inverted polarity : RegData[x] = !IO[x] (for both input and output configured IOs) Enables polarity inversion for each IO 0 : Normal polarity : RegData[x] = IO[x] 1 : Inverted polarity : RegData[x] = !IO[x] (for both input and output configured IOs) Configures direction for each IO. 0 : IO is configured as an output 1 : IO is configured as an input Configures direction for each IO. 0 : IO is configured as an output 1 : IO is configured as an input Write: Data to be output to the output-configured IOs Read: Data seen at the IOs, independent of the direction configured. Write: Data to be output to the output-configured IOs Read: Data seen at the IOs, independent of the direction configured. Configures which [input-configured] IO will trigger an interrupt on NINT pin 0 : An event on this IO will trigger an interrupt 1 : An event on this IO will NOT trigger an interrupt Configures which [input-configured] IO will trigger an interrupt on NINT pin 0 : An event on this IO will trigger an interrupt 1 : An event on this IO will NOT trigger an interrupt Edge sensitivity of RegData[15] 00 : None Edge sensitivity of RegData[14] 01 : Rising 10 : Falling Edge sensitivity of RegData[13] 11 : Both Edge sensitivity of RegData[12] Edge sensitivity of RegData[11] Edge sensitivity of RegData[10] Edge sensitivity of RegData[9] Edge sensitivity of RegData[8] Edge sensitivity of RegData[7] Edge sensitivity of RegData[6] Edge sensitivity of RegData[5] Edge sensitivity of RegData[4] Edge sensitivity of RegData[3] 32 00 : None 01 : Rising 10 : Falling 11 : Both 00 : None 01 : Rising 10 : Falling 11 : Both 00 : None www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 5:4 3:2 1:0 0x18 0x19 0x1A 0x1B RegInterruptSourceB RegInterruptSourceA RegEventStatusB RegEventStatusA 0x00 0x00 0x00 0x00 0x1C RegLevelShifter1 0x00 0x1D RegLevelShifter2 0x00 7:0 Edge sensitivity of RegData[2] Edge sensitivity of RegData[1] Edge sensitivity of RegData[0] Interrupt source (from IOs set in RegInterruptMask) 0 : No interrupt has been triggered by this IO 1 : An interrupt has been triggered by this IO (an event as configured in relevant RegSense register occured). 7:0 Writing '1' clears the bit in RegInterruptSource and in RegEventStatus When all bits are cleared, NINT signal goes back high. Interrupt source (from IOs set in RegInterruptMask) 0 : No interrupt has been triggered by this IO 1 : An interrupt has been triggered by this IO (an event as configured in relevant RegSense register occured). 7:0 Writing '1' clears the bit in RegInterruptSource and in RegEventStatus When all bits are cleared, NINT signal goes back high. Event status of all IOs. 0 : No event has occured on this IO 1 : An event has occured on this IO (an edge as configured in relevant RegSense register occured). 7:0 Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant. If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically Event status of all IOs. 0 : No event has occured on this IO 1 : An event has occured on this IO (an edge as configured in relevant RegSense register occured). 7:6 5:4 3:2 1:0 7:6 5:4 3:2 1:0 7 6:5 0x1E RegClock 0x00 4 3:0 7 6:4 3 0x1F RegMisc 0x00 2 1 0 0x20 RegLEDDriverEnableB th Rev 3 – 9 Sept. 2010 0x00 7:0 Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant. If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically Level shifter mode for IO[7] (Bank A) and IO[15] (Bank B) 00 : OFF 01 : A->B Level shifter mode for IO[6] (Bank A) and IO[14] (Bank B) 10 : B->A Level shifter mode for IO[5] (Bank A) and IO[13] (Bank B) 11 : Reserved Level shifter mode for IO[4] (Bank A) and IO[12] (Bank B) Level shifter mode for IO[3] (Bank A) and IO[11] (Bank B) 00 : OFF 01 : A->B Level shifter mode for IO[2] (Bank A) and IO[10] (Bank B) 10 : B->A Level shifter mode for IO[1] (Bank A) and IO[9] (Bank B) 11 : Reserved Level shifter mode for IO[0] (Bank A) and IO[8] (Bank B) Unused Oscillator frequency (fOSC) source 00 : OFF. LED driver, keypad engine and debounce features are disabled. 01 : External clock input (OSCIN) 10 : Internal 2MHz oscillator 11 : Reserved OSCIO pin function (Cf. §4.8) 0 : OSCIO is an input (OSCIN) 1 : OSCIO is an output (OSCOUT) Frequency of the signal output on OSCOUT pin: 0x0 : 0Hz, permanent "0" logical level (GPO) 0xF : 0Hz, permanent "1" logical level (GPO) Else : fOSCOUT = fOSC/(2^(RegClock[3:0]-1)) LED Driver mode for Bank B ‘s fading capable IOs (IO15-12) 0: Linear 1: Logarithmic Frequency of the LED Driver clock ClkX of all IOs: 0 : OFF. LED driver functionality is disabled for all IOs. Else : ClkX = fOSC/(2^(RegMisc[6:4]-1)) LED Driver mode for Bank A ‘s fading capable IOs (IO7-4) 0: Linear 1: Logarithmic NRESET pin function when externally forced low (Cf. §4.4.1 and §4.9.5) 0: Equivalent to POR 1: Reset PWM/Blink/Fade counters (not user programmed values) This bit is can only be reset manually or by POR, not by NRESET. Auto-increment register address (Cf. §4.5) 0: ON. When several consecutive data are read/written, register address is incremented. 1: OFF. When several consecutive data are read/written, register address is kept fixed. Autoclear NINT on RegData read (Cf. §4.7) 0: ON. RegInterruptSourceA/B is also automatically cleared when RegDataA/B is read. 1: OFF. RegInterruptSourceA/B must be manually cleared, either directly or via RegEventStatusA/B. Enables LED Driver for each [output-configured] IO 0 : LED Driver is disabled 1 : LED Driver is enabled 33 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 0x21 RegLEDDriverEnableA 0x00 7:0 7:3 0x22 RegDebounceConfig 0x00 0x23 RegDebounceEnableB 0x00 7:0 0x24 RegDebounceEnableA 0x00 7:0 2:0 7 6:4 0x25 RegKeyConfig1 0x00 3 2:0 7:6 5:3 0x26 RegKeyConfig2 0x00 2:0 0x27 RegKeyData1 0xFF 7:0 0x28 RegKeyData2 0xFF 7:0 7:5 0xXX RegTOnX 0x00 0xXX RegIOnX 0xFF th Rev 3 – 9 Sept. 2010 4:0 7:0 Enables LED Driver for each [output-configured] IO 0 : LED Driver is disabled 1 : LED Driver is enabled Unused Debounce time (Cf. §4.6.1) 000: 0.5ms x 2MHz/fOSC 001: 1ms x 2MHz/fOSC 010: 2ms x 2MHz/fOSC 011: 4ms x 2MHz/fOSC 100: 8ms x 2MHz/fOSC 101: 16ms x 2MHz/fOSC 110: 32ms x 2MHz/fOSC 111: 64ms x 2MHz/fOSC Enables debouncing for each [input-configured] IO 0 : Debouncing is disabled 1 : Debouncing is enabled Enables debouncing for each [input-configured] IO 0 : Debouncing is disabled 1 : Debouncing is enabled Reserved Auto Sleep time (no key press within this time will set keypad engine to sleep) 000 : OFF 001 : 128ms x 2MHz/fOSC 010 : 256ms x 2MHz/fOSC 011 : 512ms x 2MHz/fOSC 100 : 1sec x 2MHz/fOSC 101 : 2sec x 2MHz/fOSC 110 : 4sec x 2MHz/fOSC 111 : 8sec x 2MHz/fOSC Unused Scan time per row (must be set above debounce time). 000 : 1ms x 2MHz/fOSC 001 : 2ms x 2MHz/fOSC 010 : 4ms x 2MHz/fOSC 011 : 8ms x 2MHz/fOSC 100 : 16ms x 2MHz/fOSC 101 : 32ms x 2MHz/fOSC 110 : 64ms x 2MHz/fOSC 111 : 128ms x 2MHz/fOSC Unused Number of rows (outputs) + key scan enable 000 : Key scan OFF 001 : 2 rows – IO[0:1] 010 : 3 rows – IO[0:2] 011 : 4 rows – IO[0:3] 100 : 5 rows – IO[0:4] 101 : 6 rows – IO[0:5] 110 : 7 rows – IO[0:6] 111 : 8 rows – IO[0:7] Number of columns (inputs) 000 : 1 column – IO[8] 001 : 2 columns – IO[8:9] 010 : 3 columns – IO[8:10] 011 : 4 columns – IO[8:11] 100 : 5 columns – IO[8:12] 101 : 6 columns – IO[8:13] 110 : 7 columns – IO[8:14] 111 : 8 columns – IO[8:15] Column which generated NINT (active low) Ex: RegKeyData1=11011111 => IO13 has generated NINT The register is automatically cleared when RegKeyData2 is read. Row which generated NINT (active low) Ex: RegKeyData2=11111110 => IO0 has generated NINT When the register is read both RegKeyData1 & RegKeyData2 are automatically cleared together with NINT and key scan continues. Unused ON Time of IO[X]: 0 : Infinite (Static mode, TOn directly controlled by RegData, Cf §4.9.2) 1 - 15 : TOnX = 64 * RegTOnX * (255/ClkX) 16 - 31 : TOnX = 512 * RegTOnX * (255/ClkX) ON Intensity of IO[X] - Linear mode : IOnX = RegIOnX - Logarithmic mode (fading capable IOs only) : IOnX = f(RegIOnX) , Cf §4.9.5 34 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 7:3 0xXX RegOffX 0x00 2:0 7:5 0xXX RegTRiseX 0x00 4:0 7:5 0xXX RegTFallX 0x00 0x69 RegHighInputB 0x00 7:0 0x6A RegHighInputA 0x00 7:0 0x7D RegReset 0x00 7:0 4:0 OFF Time of IO[X]: 0 : Infinite (Single shot mode, TOff directly controlled by RegData, Cf §4.9.3) 1 - 15 : TOffX = 64 * RegOffX[7:3] * (255/ClkX) 16 - 31 : TOffX = 512 * RegOffX[7:3] * (255/ClkX) OFF Intensity of IO[X] - Linear mode : IOffX = 4 x RegOff[2:0] - Logarithmic mode (fading capable IOs only) : IOffX = f(4 x RegOffX[2:0]) , Cf §4.9.5 Unused Fade In setting of IO[X] 0 : OFF 1 - 15 : TRiseX = (RegIOnX-(4xRegOffX[2:0])) * RegTRiseX * (255/ClkX) 16 - 31 : TRiseX = 16 * (RegIOnX-(4xRegOffX[2:0])) * RegTRiseX * (255/ClkX) Unused Fade Out setting of IO[X] 0 : OFF 1 - 15 : TFallX = (RegIOnX-(4xRegOffX[2:0])) * RegTFallX * (255/ClkX) 16 - 31 : TFallX = 16 * (RegIOnX-(4xRegOffX[2:0])) * RegTFallX * (255/ClkX) Enables high input mode for each [input-configured] IO 0 : OFF. VIH max = 3.6V and VCCx min = 1.2V 1 : ON. VIH max = 5.5V and VCCx min = 1.65V Enables high input mode for each [input-configured] IO 0 : OFF. VIH max = 3.6V and VCCx min = 1.2V 1 : ON. VIH max = 5.5V and VCCx min = 1.65V Software reset register Writing consecutively 0x12 and 0x34 will reset the device (same as POR). Always reads 0. Table 14 – SX1509QB Configuration Registers Description th Rev 3 – 9 Sept. 2010 35 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 6 6.1 APPLICATION INFORMATION Typical Application Circuit OSCIO 3.3V VCC1 I/O[0] I/O[1] I/O[2] I/O[3] VDDM Host controller I/O 2.5V NRESET SX1508QB SCL SCL SDA SDA I/O 5V 5V 1.2V VCC2 I/O[4] I/O[5] I/O[6] I/O[7] ADDR1 ADDR0 NINT GND Optional (depends on the application) Figure 21 - Typical Application Schematic 6.2 Typical LED Connection Typical LED Connection is described below. The LED is usually connected to a high voltage (VBAT) to take advantage of the high sink current of the I/O and to accommodate high LED threshold voltages (VLED). Please note that in this configuration the IO must be programmed as open drain output (RegOpenDrain) with no pull-up (RegPullUp) and input buffer must be disabled (RegInputBufferDisable). VCCx can take any value without compromising LED operation. VCCx VBAT VCCx * VLED SX1507/8/9QB R IOx IOL * LED colour/technology dependent Figure 22 – Typical LED Operation Serial R must be calculated for IOL not to exceed its max spec (Cf. Table 5) else VOL will increase. th Rev 3 – 9 Sept. 2010 36 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 7 PACKAGING INFORMATION 7.1 QFN-UT 14-pin Outline Drawing QFN 14-pin, 2 x 2 mm, 0.4 mm pitch Figure 23 – QFN-UT 14-pin Outline Drawing 7.2 QFN-UT 14-pin Land Pattern Figure 24 – QFN-UT 14-pin Land Pattern th Rev 3 – 9 Sept. 2010 37 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 7.3 QFN-UT 20-pin Outline Drawing QFN-UT 20-pin, 3 x 3 mm, 0.4 mm pitch Figure 25 - QFN-UT 20-pin Outline Drawing 7.4 QFN-UT 20-pin Land Pattern Figure 26 - QFN-UT 20-pin Land Pattern th Rev 3 – 9 Sept. 2010 38 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 7.5 QFN-UT 28-pin Outline Drawing QFN-UT 28-pin, 4 x 4 mm, 0.4 mm pitch Figure 27 - QFN-UT 28-pin Outline Drawing 7.6 QFN-UT 28-pin Land Pattern Figure 28 - QFN-UT 28-pin Land Pattern th Rev 3 – 9 Sept. 2010 39 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 8 SOLDERING PROFILE The soldering reflow profile for the SX1507QB, SX1508QB and SX1509QB is described in the standard IPC/JEDEC J-STD-020C. For detailed information please go to http://www.jedec.org/download/search/jstd020c.pdf Figure 29 - Classification Reflow Profile (IPC/JEDEC J-STD-020C) th Rev 3 – 9 Sept. 2010 40 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING 9 MARKING INFORMATION HAB7 yyww xxxx yyww = Date Code xxxx = Semtech Lot No. Figure 30 – SX1508QB Marking Information HCA5 yyww xxxxx xxxxx yyww = Date Code xxxxx = Semtech Lot No. xxxxx Figure 31 – SX1509QB Marking Information th Rev 3 – 9 Sept. 2010 41 www.semtech.com SX1507QB/SX1508QB/SX1509QB World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine ADVANCED COMMUNICATIONS & SENSING © Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. 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