STMICROELECTRONICS STA510A

STA510A
44-volt, 5.5-amp, quad power half bridge
Features
„
Multipower BCD technology
„
Minimum input, output pulse width distortion
„
150-mΩ RdsON complementary DMOS output
stage
„
CMOS compatible logic inputs
„
Thermal protection
„
Thermal-warning output
„
Undervoltage protection
„
Short-circuit protection
PowerSO36
with exposed pad up (EPU)
Description
STA510A is a monolithic quad half bridge stage in
Multipower BCD Technology. The device can be
used as dual bridge or reconfigured, by
connecting pin CONFIG to VDD, as a single bridge
with double current capability, or as half bridges
(Binary mode) with half current capability.
The device is intended for the output stage of a
stereo all-digital high-efficiency (DDX®) amplifier
which employs a pulse-width modulator driver.
Table 1.
The STA510A is capable of delivering an output
power of 50 W into 3 Ω x 4 channels with
THD = 10% at VCC = 37 V in single ended
configuration. It can also deliver 100 W + 100 W
into 6-Ω loads with THD = 10% at VCC = 36 V in
BTL configuration and 200W into 3 Ω with
THD = 10% at VCC = 36 V in single paralleled
BTL configuration.
The input pins have a threshold proportional to
the voltage on pin VL.
Device summary
Order code
Operating temp. range
Package
Packaging
STA510A
0 to 70 °C
PowerSO36 EPU
Tube
STA510A13TR
0 to 70 °C
PowerSO36 EPU
Tape and reel
March 2010
Doc ID 11077 Rev 2
1/17
www.st.com
17
Contents
STA510A
Contents
1
Audio applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Technical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
Logic interface and decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
Protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
Power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
Parallel output / high current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5
Output filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.6
Applications circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
Doc ID 11077 Rev 2
STA510A
1
Audio applications circuit
Audio applications circuit
Figure 1.
Audio applications circuit (dual BTL)
+VCC
VCC1A
IN1A
29
VL
23
CONFIG
24
PWRDN
PWRDN
25
R59
10K
FAULT
27
M3
IN1A
+3.3V
R57
10K
26
THWARN
16
M2
Protection
&
logic
M5
THWARN
28
IN1B
30
VDD
21
VDD
22
VSS
33
VSS
34
OUT1A
14
GND1A
12
VCC1B
OUT1B
M4
Regulators
VCCSIG
13
GND1B
7
VCC2A
C60
100nF
VCCSIG
IN2A
IN2A
GNDREG
GNDCLEAN
IN2B
IN2B
GNDSUB
9
36
M15
31
20
19
M16
1
GND2A
4
VCC2B
C31
220nF
3
OUT2B
OUT2B
M14
5
R100
6
C99
100nF
C23
470nF
C101
100nF
8Ω
C21
100nF
L113 22µH
C110
100nF
C109
330pF R103
6
OUT2A
2
32
OUT2A
6
R98
6
L19 22µH
C32
220nF
8
35
R63
20
OUT1B
M17
C53
100nF
C20
100nF
C52
330pF
C31
220nF
11
C55
1000µF
L18 22µH
OUT1A
10
IN1B
C58
100nF
C30
1µF
17
TRISTATE
C58
100nF
15
R104
20
R102
6
C107
100nF
C108
470nF
C106
100nF
8Ω
C111
100nF
L112 22µH
GND2B
D00AU1148B
Doc ID 11077 Rev 2
3/17
Pins description
2
STA510A
Pins description
Figure 2.
Pin connection (top view)
VCCSIG
36
1
GNDSUB
VCCSIG
35
2
OUT2B
VSS
34
3
OUT2B
VSS
33
4
VCC2B
IN2B
32
5
GND2B
IN2A
31
6
GND2A
IN1B
30
7
VCC2A
IN1A
29
8
OUT2A
THWARN
28
9
OUT2A
FAULT
27
10
OUT1B
TRISTATE
26
11
OUT1B
PWRDN
25
12
VCC1B
CONFIG
24
13
GND1B
14
GND1A
15
VCC1A
VL
23
VDD
22
VDD
21
16
OUT1A
GNDREG
20
17
OUT1A
GNDCLEAN
19
18
NC
EP, exposed pad up
D01AU1273
Table 2.
4/17
Pin functions
Pin
Name
Description
1
GNDSUB
2, 3
OUT2B
Output half bridge 2B
4
VCC2B
Positive supply
5
GND2B
Negative supply
6
GND2A
Negative supply
7
VCC2A
Positive supply
8, 9
OUT2A
Output half bridge 2A
10, 11
OUT1B
Output half bridge 1B
12
VCC1B
Positive supply
13
GND1B
Negative supply
14
GND1A
Negative supply
15
VCC1A
Positive supply
16, 17
OUT1A
Output half bridge 1A
Substrate ground
Doc ID 11077 Rev 2
STA510A
Pins description
Table 2.
Pin functions (continued)
Pin
Name
18
NC
19
GNDCLEAN
20
GNDREG
21, 22
VDD
23
VL
Description
No internal connection
Logical ground
Ground for regulator VDD
5-V regulator referred to ground
Logic reference voltage
24
CONFIG
Configuration pin:
0: normal operation
1: single BTL (mono) mode, join the pins OUT1A to OUT1B and
OUT2A to OUT2B (if IN1A is joined to IN1B and IN2A to IN2B)
25
PWRDN
Standby (power down):
0: low power consumption mode
1: normal operation
26
TRISTATE
High impedance control:
0: all power amplifiers in high-impedance state
1: normal operation
27
FAULT (1)
Fault advisor:
0: fault detected (short circuit or thermal)
1: normal operation
28
THWARN (1)
29
IN1A
Input of half bridge 1A
30
IN1B
Input of half bridge 1B
31
IN2A
Input of half bridge 2A
32
IN2B
Input of half bridge 2B
33, 34
VSS
5-V regulator referred to +VCC
35, 36
VCCSIG
-
EP
Thermal warning advisor:
0: junction temperature = 130 °C
1: normal operation
Signal positive supply
Exposed pad up
1. The pin is open collector. To have a high logic value it needs to be pulled up by a resistor.
Doc ID 11077 Rev 2
5/17
Electrical specifications
STA510A
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
3.2
Parameter
Min
Typ
Max
Unit
VCC
DC supply voltage (pins 4,7,12,15)
-
-
44
V
Vmax
Maximum voltage on pins 23 to 32
-
-
5.5
V
Top
Operating temperature range
-
-
90
°C
Ptot
Power dissipation (Tcase = 70 °C)
-
-
21
W
Tstg
Storage temperature
-40
-
150
°C
Tj
Junction operating temperature
-40
-
150
°C
Recommended operating conditions
Table 4.
Recommended operating conditions (*)
Symbol
Parameter
Min
Typ
Max
Unit
VCC
DC supply voltage
10
-
39.0
V
VL
Input logic reference
2.7
3.3
5.0
V
Tamb
Ambient temperature
0
-
70
°C
(*) performances not guaranteed beyond recommended operating conditions
3.3
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Min
Typ
Max
Unit
Tj-case
Thermal resistance junction to case (thermal pad)
-
1
2.5
°C/W
TjSD
Thermal shut-down junction temperature
-
150
-
°C
Twarn
Thermal warning temperature
-
130
-
°C
thSD
Thermal shut-down hysteresis
-
25
-
°C
The power dissipated within the device depends primarily on the supply voltage, load
impedance and output modulation level. The PowerSO36 package of the STA510A includes
an exposed pad or slug on the top of the device to provide a direct thermal path from the die
to the heatsink.
6/17
Doc ID 11077 Rev 2
STA510A
3.4
Electrical specifications
Electrical characteristics
The specifications given here were obtained with the conditions VL = 3.3 V, VCC = 36 V,
RL = 8 Ω, fsw = 384 kHz and Tamb = 25 °C unless otherwise specified. See also Figure 3.
Table 6.
.
Electrical characteristics
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
RdsON
Power P-channel / N-channel MOSFET
RdsON
Id = 1 A
-
150
200
mΩ
Idss
Power P-channel / N-channel leakage
-
-
-
100
µA
gN
Power P-channel RdsON matching
Id = 1 A
95
-
-
%
gP
Power N-channel RdsON matching
Id = 1 A
95
-
-
%
Dt_s
Low current dead time (static)
See test circuit in
Figure 3
-
10
20
ns
Dt_d
High current dead time (dynamic)
L = 22 µH,
C = 470 nF,
RL = 8 Ω,
Id = 3 A,
seeFigure 5
-
-
50
ns
td ON
Turn-on delay time
Resistive load,
VCC = 30 V
-
-
100
ns
td OFF
Turn-off delay time
Resistive load,
VCC = 30 V
-
-
100
ns
tr
Rise time
tf
-
-
25
ns
Fall time
Resistive load,
see Figure 3
-
-
25
ns
VINH
High-level input voltage
-
-
-
VL/2 +
300 mV
V
VINL
Low-level input voltage
-
VL/2 300 mV
-
V
IINH
High-level Input current
Pin voltage = VL
-
1
-
µA
IINL
Low-level input current
Pin voltage = 0.3 V
-
1
-
µA
IPWRDNH
High-level PWRDN pin input current
VL = 3.3 V
-
35
-
µA
VL = 2.7 V
-
-
0.70
V
VLOW
Low logical-state voltage (pins PWRDN,
TRISTATE)
VL = 3.3 V
-
-
0.80
V
VL = 5.0 V
-
-
0.85
V
VL = 2.7 V
1.50
-
-
V
VL = 3.3 V
1.70
-
-
V
VL = 5.0 V
1.85
-
-
V
VPWRDN = 0 V
-
-
3
mA
Vpin = 3.3 V
-
1
-
mA
VHIGH
High logical-state voltage (pins PWRDN,
TRISTATE)
ICCPWRDN Supply current from VCC in power down
IFAULT
Output current on pins FAULT and
THWARN with fault conditions
Doc ID 11077 Rev 2
7/17
Electrical specifications
Table 6.
STA510A
Electrical characteristics (continued)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
Supply current from VCC in 3-state
VCC = 30 V,
VTRISTATE = 0 V
-
22
-
mA
IVCC
Supply current from VCC in operation
(both channels switching)
VCC = 30 V,
Input pulse width =
50% duty,
switching frequency
= 384 kHz,
no LC filters
-
70
-
mA
ISCP
Short-circuit current limit
-
5.5
6
-
A
VUVP
Undervoltage protection threshold
-
-
7
-
V
tpw_min
Output minimum pulse width
No load
25
-
40
ns
ESD
ESD maximum withstanding voltage range,
test condition CDF-AEC-Q100-002- ”Human Body Model”
IVCCHIZ
Table 7.
+/-1500V
V
Logic truth table
TRISTATE
INxA
INxB
Q1
Q2
Q3
Q4
Output
mode
0
X
X
Off
Off
Off
Off
Hi-Z
1
0
0
Off
Off
On
On
Dump
1
0
1
Off
On
On
Off
Negative
1
1
0
On
Off
Off
On
Positive
1
1
1
On
On
Off
Off
Not used
Figure 3.
Test circuit for low current dead time for single-ended applications
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
Duty cycle = 50%
OUTxY
INxY
DTf
R 8Ω
+
-
gnd
8/17
Doc ID 11077 Rev 2
vdc = Vcc/2
D03AU1458
STA510A
Electrical specifications
Figure 4.
Block diagram for high current dead time for bridge applications
+VCC
Q1
Q2
OUTxA
INxA
OUTxB
Q3
INxB
Q4
GND
Figure 5.
D00AU1134
Test circuit for high current dead time for bridge applications
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
Q1
DTin(A)
Q2
Rload=8Ω
OUTA
INA
Iout=4.5A
Q3
DTout(B)
L67 22µ
C69
470nF
L68 22µ
C71 470nF
C70
470nF
INB
Iout=4.5A
Q4
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
Doc ID 11077 Rev 2
DTin(B)
OUTB
D03AU1517
9/17
Technical information
4
STA510A
Technical information
The STA510A is a dual channel H-bridge that is able to deliver 100 W per channel (into
RL = 6 Ω with THD = 10% and VCC = 36 V) of audio output power very efficiently. It operates
in conjunction with a pulse-width modulator driver such as the STA321 or STA309A.
The STA510A converts ternary-, phase-shift- or binary-controlled PWM signals into audio
power at the load. It includes a logic interface, integrated bridge drivers, high efficiency
MOSFET outputs and thermal and short-circuit protection circuitry.
In differential mode (ternary, phase-shift or binary differential), two logic level signals per
channel are used to control high-speed MOSFET switches to connect the speaker load to
the input supply or to ground in a bridge configuration, according to the damped ternary
modulation operation.
In binary mode, both full bridge and half bridge modes are supported. The STA510A
includes overcurrent and thermal protection as well as an undervoltage lockout with
automatic recovery. A thermal warning status is also provided.
Figure 6.
Block diagram of full-bridge DDX® or binary mode
INL[1,2]
INR[1,2]
VL
PWRDN
TRISTATE
FAULT
Logic
interface
and
decode
Protection
THWARN
OUTPL
Left
H-bridge
Right
H-bridge
OUTNL
OUTPR
OUTNR
Regulators
Figure 7.
Block diagram of binary half-bridge mode
INL[1,2]
INR[1,2]
VL
PWRDN
TRISTATE
FAULT
Logic
interface
and
decode
LeftA
½-bridge
OUTPL
LeftB
½-bridge
OUTNL
Protection
RightA
½-bridge
OUTPR
RightB
½-bridge
OUTNR
THWARN
Regulators
4.1
Logic interface and decode
The STA510A power outputs are controlled using one or two logic-level timing signals. In
order to provide a proper logic interface, the VL input must operate at the same voltage as
the DDX control logic supply.
10/17
Doc ID 11077 Rev 2
STA510A
4.2
Technical information
Protection circuitry
The STA510A includes protection circuitry for overcurrent and thermal overload conditions.
A thermal warning pin (THWARN, pin 28, open drain MOSFET) is activated low when the IC
temperature exceeds 130 °C, just in advance of thermal shutdown. When a fault condition is
detected an internal fault signal immediately disables the output power MOSFETs, placing
both H-bridges in a high-impedance state. At the same time the open-drain MOSFET of pin
FAULT (pin 27) is switched on.
There are two possible modes subsequent to activating a fault.
4.3
z
Shutdown mode: with pins FAULT (with pull-up resistor) and TRISTATE separate, an
activated fault disables the device, signalling a low at pin FAULT output.
The device may subsequently be reset to normal operation by toggling pin TRISTATE
from high to low to high using an external logic signal.
z
Automatic recovery mode: This is shown in the applications circuits below where pins
FAULT and TRISTATE are connected together to a time-constant circuit (R59 and C58).
An activated fault forces a reset on pin TRISTATE causing normal operation to resume
following a delay determined by the time constant of the circuit.
If the fault condition persists, the circuit operation repeats until the fault condition is
cleared.
An increase in the time constant of the circuit produces a longer recovery interval. Care
must be taken in the overall system design not to exceed the protection thesholds
under normal operation.
Power outputs
The STA510A power and output pins are duplicated to provide a low-impedance path for the
device bridged outputs. All duplicate power, ground and output pins must be connected for
proper operation.
The PWRDN or TRISTATE pin should be used to set all power MOSFETs to the
high-impedance state during power-up until the logic power supply, VL, has settled.
4.4
Parallel output / high current operation
When using the DDX mode output, the STA510A outputs can be connected in parallel in
order to increase the output current capability to a load. In this configuration the STA510A
can provide up to 200 W into a 3-Ω load.
This mode of operation is enabled with the pin CONFIG (pin 24) connected to pin VDD. The
inputs are joined so that IN1A = IN1B, IN2A = IN2B and similarly the outputs
OUT1A = OUT1B, OUT2A = OUT2B as shown in Figure 9 on page 12
4.5
Output filtering
A passive 2nd-order filter is used on the STA510A power outputs to reconstruct the analog
audio signal. System performance can be significantly affected by the output filter design
and choice of passive components. A filter design for 6- or 8-Ω loads is shown in the
application circuit of Figure 8, and for 4-Ω loads in Figure 9 and Figure 10.
Doc ID 11077 Rev 2
11/17
Technical information
4.6
STA510A
Applications circuits
Figure 8.
Typical stereo full bridge configuration for up to 2x 100 W
+VCC
VCC1A
IN1A
29
VL
23
CONFIG
24
PWRDN
PWRDN
25
R59
10K
FAULT
27
M3
IN1A
+3.3V
R57
10K
16
M2
Protection
&
logic
26
THWARN
M5
THWARN
28
IN1B
30
VDD
21
VDD
22
VSS
33
VSS
34
OUT1A
14
GND1A
12
VCC1B
OUT1B
M4
Regulators
13
GND1B
7
VCC2A
VCCSIG
C60
100nF
VCCSIG
IN2A
IN2A
GNDREG
GNDCLEAN
IN2B
IN2B
GNDSUB
9
36
M15
31
20
19
M16
GND2A
4
VCC2B
C31
220nF
3
OUT2B
OUT2B
M14
1
5
8Ω
C21
100nF
L113 22µH
C110
100nF
C109
330pF R103
6
OUT2A
2
32
OUT2A
6
R100
6
L19 22µH
C32
220nF
8
35
C99
100nF
C23
470nF
C101
100nF
R98
6
R63
20
OUT1B
M17
C53
100nF
C20
100nF
C52
330pF
C31
220nF
11
C55
1000µF
L18 22µH
OUT1A
10
IN1B
C58
100nF
C30
1µF
17
TRISTATE
C58
100nF
15
R104
20
C107
100nF
C108
470nF
C106
100nF
R102
6
8Ω
C111
100nF
L112 22µH
GND2B
D00AU1148B
Figure 9.
Typical single BTL configuration for up to 180 W
VL
+3.3V
GNDCLEAN
GNDREG
10K
23
18
NC
12µH
100nF
100nF
X7R
19
20
VDD
VDD
CONFIG
THWARN
THWARN
PWRDN
nPWRDN
10K
FAULT
IN1A
IN1B
IN1A
IN2A
IN2B
IN1B
16
11
10
9
24
Add.
GNDSUB
330pF
12µH
VCC1A
+36V
1µF
X7R
2200µF
63V
12
VCC2A
31
220nF
+36V
7
32
VCC2B
33
1µF
X7R
4
GND1A
14
GND1B
220nF
13
GND2A
36
6
1
5
GND2B
D04AU1545
12/17
6.2
1/2W
100nF
X7R
680nF
FILM
100nF
X7R
100nF
FILM
OUT2B
VCC1B
35
VCCSIG
OUT2A
15
VCCSIG
100nF
X7R
6.2
1/2W
22Ω
1/2W
30
34
100nF
X7R
OUT1B
2
VSS
VSS
OUT1B
OUT2B
3
25
29
100nF
FILM
OUT1A
8
28
26
OUT1A
OUT2A
22
27
TRISTATE
100nF
21
17
Doc ID 11077 Rev 2
4Ω
STA510A
Technical information
Figure 10. Typical quad half bridge configuration for up to 4x 50 W
+VCC
VCC1A
IN1A
29
M3
IN1A
15
1µF
17
C31 820µF
L11 22µH
+3.3V
PWRDN
R57
10K
VL
23
CONFIG
24
PWRDN
25
FAULT
R59
10K
27
26
16
M2
Protection
&
logic
TRISTATE
C58
100nF
THWARN
M5
THWARN
28
IN1B
30
VDD
21
VDD
22
VSS
33
VSS
34
OUT1A
14
GND1A
12
VCC1B
11
10
C51
1µF
M4
Regulators
13
7
GND1B
VCC2A
VCCSIG
C60
100nF
VCCSIG
IN2A
IN2A
GNDREG
GNDCLEAN
IN2B
IN2B
GNDSUB
9
M15
31
20
19
M16
1
OUT2A
6
GND2A
4
VCC2B
3
C52
1µF
5
GND2B
D03AU1474
Note:
R42
20
C42
330pF
R62
5K
R63
5K
L12 22µH
R43
20
C43
330pF
C72
100nF
R52
6
C82
100nF
R64
5K
R65
5K
C73
100nF
R53
6
C83
100nF
C62
100nF
OUT2B
OUT2B
M14
C81
100nF
C91
1µF
4Ω
C32 820µF
C92
1µF
4Ω
C33 820µF
L13 22µH
OUT2A
2
32
R51
6
C61
100nF
8
35
36
C41
330pF
C71
100nF
1µF
M17
C53
100nF
R41
20
OUT1B
OUT1B
IN1B
C58
100nF
OUT1A
C21
2200µF
R61
5K
R67
5K
L14 22µH
R44
20
C44
330pF
R66
5K
C74
100nF
R54
6
C84
100nF
R68
5K
C93
1µF
4Ω
C34 820µF
C94
1µF
4Ω
1
In the above three circuits a PWM modulator as driver is needed.
2
The power estimations were made using the STA321+STA510A demo board. The peak
power duration is for t ≤ 1 s.
Doc ID 11077 Rev 2
13/17
Package mechanical data
5
STA510A
Package mechanical data
Figure 11. PowerSO36 EPU outline drawing package dimension
14/17
Doc ID 11077 Rev 2
STA510A
Package mechanical data
Table 8.
PowerSO36 EPU package dimension
mm
inch
Symbol
Min
Typ
Max
Min
Typ
Max
A
3.25
-
3.43
0.128
-
0.135
A2
3.10
-
3.20
0.122
-
0.126
A4
0.80
-
1.00
0.031
-
0.039
A5
-
0.20
-
-
0.008
-
a1
0.03
-
-0.04
0.001
-
-0.002
b
0.22
-
0.38
0.009
-
0.015
c
0.23
-
0.32
0.009
-
0.013
D
15.80
-
16.00
0.622
-
0.630
D1
9.40
-
9.80
0.370
-
0.386
D2
-
1.00
-
-
0.039
-
E
13.90
-
14.50
0.547
-
0.571
E1
10.90
-
11.10
0.429
-
0.437
E2
-
-
2.90
-
-
0.114
E3
5.80
-
6.20
0.228
-
0.244
E4
2.90
-
3.20
0.114
-
0.126
e
-
0.65
-
-
0.026
-
e3
-
11.05
-
-
0.435
-
G
0
-
0.08
0
-
0.003
H
15.50
-
15.90
0.610
-
0.626
h
-
-
1.10
-
-
0.043
L
0.80
-
1.10
0.031
-
0.043
M
2.25
-
2.60
0.089
-
0.102
N
-
-
10 degrees
-
-
10 degrees
R
-
0.6
-
-
0.024
-
s
-
-
8 degrees
-
-
8 degrees
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 11077 Rev 2
15/17
Revision history
6
STA510A
Revision history
Table 9.
16/17
Document revision history
Date
Revision
Changes
October 2004
1
Initial release.
11-Mar-2010
2
Updated description and applications circuits
Doc ID 11077 Rev 2
STA510A
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