STA335ML 2-channel microless high-efficiency digital audio system Sound Terminal® Features PowerSSO-36 ■ Wide supply voltage range (5.0 V to 26 V) ■ PowerSSO-36 exposed pad down package ■ 2 channels of 24-bit DDX® ■ 100-dB SNR and dynamic range ■ Selectable 32 kHz to 48 kHz input sample rates ■ Automatic zero-detect mute ■ Automatic invalid input detect mute ■ 2-channel I2S input data interface ■ Selectable clock input ratio (256 or 364 * fs) ■ Max power correction for lower full power ■ 96-kHz internal processing sample rate, 24-bit precision with exposed pad down (EPD) Description The STA335ML is a single die embedding digital audio processing and high-efficiency power amplification, capable of operating without the aid of an external microcontroller. ■ Thermal overload and short-circuit protection embedded ■ Filterless configuration capability Applications ■ LCDs ■ DVDs ■ Cradles ■ Digital speakers ■ Wireless speaker cradles The STA335ML is part of the Sound Terminal® family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment. The STA335ML combines a unique 24-bit DDX® digital class-D ternary modulator together with an extremely low RdsON stereo power DMOS stage. The latter is capable of a total output power of 2 x 20 W with outstanding performance in terms of efficiency (>90 %), THD, SNR and EMI. The microless feature allows its use in low-cost applications (cradle, digital speakers, audio terminals) where no microcontroller is needed. The serial audio data interface accepts the universally used I2S format. Basic features, such as oversampling clock, gain, I2S format can be set using a minimal number of selection pins. The STA335ML is self-protected against thermal overload, overcurrent, short-circuit and overvoltage conditions. The fault condition is also signalled on an external pin (INT_LINE) for specific requirements. Table 1. Device summary Order code Package Packaging STA335MLJ PowerSSO-36 EPD Tube STA335MLJ13TR PowerSSO-36 EPD Tape and reel July 2011 Doc ID 17638 Rev 4 1/20 www.st.com 20 STA335ML Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 5 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.5 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.6 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.7 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 Fade-in/out feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 Oversampling selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.6 Gain selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.7 Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 PLL filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 Doc ID 17638 Rev 4 STA335ML 1 Block diagram Block diagram Figure 1. Block diagram Protection current/thermal 2 I S interface Volume control Channel 1A Power control Logic Channel 1B DDX Channel 2A Regulators Channel 2B PLL Bias Doc ID 17638 Rev 4 3/20 Pin description 2 STA335ML Pin description Figure 2. Table 2. Pin connections (top view) GND_SUB 1 36 VDD_DIG FMT 2 35 GND_DIG TEST_MODE 3 34 GAIN VSS_REG 4 33 ONSEL VCC_REG 5 32 INT_LINE OUT2B 6 31 RESET GND2 7 30 SDI VCC2 8 29 LRCKI OUT2A 9 28 BICKI OUT1B 10 27 XTI VCC1 11 26 GND_PLL GND1 12 25 FILTER_PLL OUT1A 13 24 VDD_PLL GND_REG 14 23 PWRDN 22 GND_DIG VDD_REG 15 CONFIG 16 21 VDD_DIG N.C. 17 20 N.C. N.C. 18 19 N.C. Pin description Pin 4/20 EP, exposed pad (device ground) Name Type Description 1 GND_SUB Gnd Substrate ground 2 FMT In Serial format: 0: I2S format 1: left justified 3 TEST_MODE In This pin must be connected to GROUND 4 VSS_REG Analog Internal reference at VCC - 3.3 V 5 VCC_REG Analog Internal VCC reference 6 OUT2B Out Output half-bridge 2B 7 GND2 Gnd Power negative supply 8 VCC2 Power Power positive supply 9 OUT2A Out Output half-bridge 2A 10 OUT1B Out Output half-bridge 1B Doc ID 17638 Rev 4 STA335ML Pin description Table 2. Pin description (continued) Pin Name Type Description 11 VCC1 Power Power positive supply 12 GND1 Gnd Power negative supply 13 OUT1A Out Output half-bridge 1A 14 GND_REG Analog Internal ground reference 15 VDD_REG Analog Internal 3.3-V reference voltage 16 CONFIG In Configuration mode, must be connected to ground 17 N.C. - No internal connection 18 N.C. - No internal connection 19 N.C. - No internal connection 20 N.C. - No internal connection 21 VDD_DIG Power Positive supply digital 22 GND_DIG Gnd Digital ground 23 PWRDN In Power down: 0: low-power mode 1: normal operation 24 VDD_PLL Power Positive supply for PLL 25 FILTER_PLL In Connection to PLL filter 26 GND_PLL Gnd Negative supply for PLL 27 XTI In PLL input clock, 256 * fs or 384 * fs 28 BICKI In I2S serial clock 29 LRCKI In I2S left/right clock 30 SDI In I2S serial data channel 31 RESET In Reset 32 INT_LINE Out Fault interrupt 33 ONSEL In Oversampling selector: 0: 256 * fs 1: 384 * fs 34 GAIN In Gain selector: 0: 0 dBFs 1: 24 dBFs 35 GND_DIG Gnd Digital ground 36 VDD_DIG Power Digital supply - EP - Exposed pad for PCB heatsink, to be connected to ground plane Doc ID 17638 Rev 4 5/20 Electrical specifications STA335ML 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol 3.2 Parameter Min Unit Power supply voltage (pins VCC1, VCC2) - - 30 V VL Logic input interface -0.3 - 4 V VDD Digital supply (pin VDD_DIG) - - 4 V Top Operating junction temperature -20 - 150 °C Tstg Storage temperature -40 - 150 °C Thermal data Symbol Thermal data Parameter Min RTh(j-case) Thermal resistance junction to case (thermal pad) - Typ Max Unit 1.5 2 °C/W Tsd Thermal shutdown junction temperature 140 - 150 °C Thsd Thermal shutdown hysteresis 18 20 22 °C Tw Thermal warning temperature 120 130 140 °C Recommended operating conditions Table 5. Symbol 6/20 Max VCC Table 4. 3.3 Typ Recommended operating conditions Parameter Min Typ Max Unit VCC Power supply voltage (pins VCC1, VCC2) 5 - 26 V VL Logic input interface 2.7 3.3 3.6 V VDD Digital supply (pin VDD_DIG) 2.7 3.3 3.6 V Tamb Ambient temperature -20 - 70 °C Doc ID 17638 Rev 4 STA335ML 3.4 Electrical specifications Electrical specifications - digital section Table 6. Symbol Iil Iih 3.5 Electrical specifications for digital section Parameter Conditions Input current without bias device Min Typ Max Unit Vi = 0 V -10 - 10 µA Vi = VDD = 3.6 V -10 - 10 µA Vil Low-level input voltage - - - 0.2 * VDD V Vih High-level input voltage - 0.8 * VDD - - V Vol Low-level output voltage Iol = 2 mA - - 0.4 * VDD V Voh High-level output voltage Ioh = 2 mA 0.8 * VDD - - V Ipu Pull-up/down current - 25 66 125 µA Rpu Equivalent pull-up/down resistance - - 50 - kΩ Electrical specifications - power section The specifications given here are with the operating conditions: VCC = 18 V, VDD = 3.3 V, fsw = 384 kHz, Tamb = 25 °C, RL = 8 Ω unless otherwise specified. Table 7. Symbol Po Electrical specifications for power section Parameter Conditions Min Typ Max THD = 1% - 16 - THD = 10% - 20 - Output power BTL Unit W RdsON On resistance of power P-channel/N-channel ld = 1 A MOSFET (Total bridge) - 180 250 mΩ ldss Power P-channel/N-channel leakage current VCC = 20 V - - 10 μA gP Power P-channel RdsON matching ld = 1.5 A 95 - - % gN Power N-channel RdsON matching ld = 1.5 A 95 - - % ILDT Low current deadtime (static) Resistive load Figure 4 - 8 15 ns IHDT High current deadtime (dynamic) Load = 1.5 A (Figure 5) - 15 30 ns tr Rise time Resistive load Figure 4 - 10 18 ns tf Fall time Resistive load Figure 4 - 10 18 ns Doc ID 17638 Rev 4 7/20 Electrical specifications Table 7. Symbol Electrical specifications for power section (continued) Parameter Conditions Min Typ Max Unit Supply current from VCC in power-down PWRDN = 0 - 0.1 1.0 mA Supply current from VCC in operation PCM Input signal = -60 dBFs. Switching frequency = 384 kHz No LC filters - 52 60 mA Ivdd_dig Supply current DDX processing (reference only) Internal clock = 49.152 MHz - 55 70 mA ISCP Short-circuit protection Hi-Z output 4.0 4.2 - A UVL Undervoltage protection threshold - 3.5 4.3 V tmin Output minimum pulse No load width 20 30 60 ns DR Dynamic range - - 100 - dB SNR Signal-to-noise ratio A-weighted - 100 - dB THD+N Total harmonic distortion + noise DDX stereo mode, Po = 1 W, f = 1 kHz - 0.2 - % PSRR DDX stereo, <5 kHz Power supply rejection Vripple = 1 V RMS ratio Audio input = dither only - 80 - dB XTALK Crosstalk DDX stereo, <5 kHz One chan. driven at 1 W other channel measured - 80 - dB η Peak efficiency, DDX mode Po = 2 x 20 W into 8 Ω - 90 - % Ivcc 8/20 STA335ML - Doc ID 17638 Rev 4 STA335ML 3.6 Electrical specifications Power-on sequence Figure 3. Power-on sequence VCC Don’t care VDD_DIG XTI Don’t care RESET TR PWRDN TR = minimum time between XTI master clock stable and reset removal: 1 ms Note 1: clock stable means: fmax - fmin < 1 MHz Note 2: No specific VCC and VDD turn-on sequence is required. 3.7 Test circuits Figure 4. Resistive load OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 + - gnd Figure 5. V67 = vdc = Vcc/2 D03AU1458 Test circuit High current dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) Q1 DTin(A) Q2 INA Iout Q3 DTout(B) Rload=8Ω OUTA L67 22μ C69 470nF L68 22μ C71 470nF C70 470nF OUTB Iout Q4 Duty cycle A and B: Fixed to have DC output current of Iout in the direction shown in figure Doc ID 17638 Rev 4 DTin(B) INB D03AU1517_00 9/20 Functional description STA335ML 4 Functional description 4.1 Serial audio interface protocols The STA335ML serial audio input interfaces with standard digital audio components and accepts serial data formats. The STA335ML always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 29), serial clock BICKI (pin 28), and serial data SDI (pin 30). The available formats are given in Figure 6 and Figure 7. Pin FMT (pin 2) selects the format such that FMT = logical 0 gives the I2S format and FMT = logical 1 gives the left-justified. Figure 6. I2S LRCKI BICKI SDI Figure 7. 1 22 33 n-1 n 1 2 3 n-1 n Left-justified LRCKI BICKI SDATAI 10/20 1 2 3 n-1 n 1 2 3 Doc ID 17638 Rev 4 n-1 n STA335ML 4.2 Functional description Fault-detect recovery bypass The on-chip STA335ML power output block provides feedback to the digital controller using inputs to the power control block. The fault input is used to indicate a fault condition (either overcurrent or thermal). When fault is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for 1 ms and then toggles it back to 1. This sequence is repeated for as long as the fault exists. 4.3 Zero-detect mute enable If this function is enabled, the zero-detect circuit examines each processing channel to see if 2048 consecutive zero value samples (regardless of fs) are received. If so, the channel is muted. 4.4 Fade-in/out feature The STA335ML has an internal fade-in / fade-out feature when powered on or off, or after a fault condition. 4.5 Oversampling selector Pin ONSEL (33) is used to configure the PLL to accept 256 * fs or 384 * fs master clock. Where fs is the I2S LRCKI frequency: ONSEL = logical 0 gives 256 * fs ONSEL = logical 1 gives 384 * fs. 4.6 Gain selector Pin GAIN (34) is used to configure the STA335ML gain: GAIN = logical 0 gives 0 dBFs GAIN = logical 1 gives 24 dBFs. 4.7 Power-down function Pin PWRDN (23) is used to power down the STA335ML: PWRDN = logical 0 sets the power-down mode PWRDN = logical 1 gives normal operation. If the power stage is switched off, then the PLL is also switched off. It is possible to use the PWRDN function as a mute function. Doc ID 17638 Rev 4 11/20 Applications STA335ML 5 Applications 5.1 Applications schematic Figure 10 on the next page shows the schematic of a typical application for the STA335ML. Concerning the power supplies, take care when designing the PCB layout. In particular, the 3.3-Ω resistors on the digital supplies (VDD_DIG) must be placed as close as possible to the device. This helps to prevent parasitic oscillation in the digital part of the device due to the inductive tracks of the PCB. The same rule applies for all the decoupling capacitors in order to limit any spikes on the supply pins. 5.2 Internal voltage reference An embedded voltage regulator produces the reference voltages for the DMOS bridge driver. It requires two 100 nF capacitors to keep the regulator stable. The capacitors should be place close to the pins. Figure 8. Reference voltage block diagram VCC VCC_REG 100 nF VSS_REG Regulator VDD_REG 100 nF GND_REG Input level shifter Driver P Driver N I2 S interface GND 5.3 PLL filter schematic It is recommended to use the circuit in Figure 9 below for the PLL loop filter to achieve the best performance from the device in general application. Note that the ground of this filter scheme has to be connected to the ground of the PLL without any resistive path. Concerning the component values, please take into account that the greater is the filter bandwidth, the less is the lock time but the higher is the PLL output jitter. Figure 9. PLL applications schematic FILTER_PLL 2k2 680 pF Ferrite bead 4.7 nF GND_DIG 12/20 100 pF GND_PLL Doc ID 17638 Rev 4 STA335ML Figure 10. Applications schematic Doc ID 17638 Rev 4 Applications 13/20 Applications 5.4 STA335ML Typical output configuration Figure 11, Figure 12 and Figure 13 show the typical output circuits used for the BTL stereo mode. Please refer to the application note for all the other recommended output configurations. Figure 11. Output configuration for stereo BTL mode (8 ohm) 22 µH OUT1A 100 nF 100 nF 22R 6R2 470 nF Left 100 nF 330 pF 6R2 100 nF 22 µH OUT1B 22 µH OUT2A 100 nF 100 nF 22R 6R2 470 nF Right 100 nF 330 pF 6R2 100 nF 22 µH OUT2B 14/20 Doc ID 17638 Rev 4 STA335ML Applications Figure 12. Filterless output configuration OUT1A Left OUT1B OUT2A Right OUT2B The filterless application is more critical in terms of EMI. It is quite important to follow the suggestions below: ● Tracks from amplifier to speaker should be as short as possible. ● Ferrite beads can be used (instead of coils) to improve EMI performance. – Ferrite beads must have a low impedance in the audio band and high impedance at high frequencies. – Place ferrite beads as close as possible to the IC. – Ferrite filters must reduce EMI above 1 MHz. – FCC and CE authorities test radiated emission above 30 MHz. Figure 13. Filterless output configuration with snubber network OUT1A 22 R 330 pF Left OUT1B OUT2A 22 R 330 pF Right OUT2B The presence of snubber networks reduce the EMI. The snubber networks should be placed as close as possible to the IC. Doc ID 17638 Rev 4 15/20 Package thermal characteristics 6 STA335ML Package thermal characteristics Using a double layer PCB the thermal resistance junction to ambient with 2 copper ground areas of 3 x 3 cm2 and with 16 via holes (see Figure 14) is 24 °C/W in natural air convection. The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. The max estimated dissipated power for the STA335ML is: 2 x 20 W into 8 Ω, at 18 V Pd max is approximately 4 W Figure 14. Double layer PCB with 2 copper ground areas and 16 via holes Figure 15 shows the power derating curve for the PowerSSO-36 package on a board with two copper areas of 2 x 2 cm2 and 3 x 3 cm2. Figure 15. PowerSSO-36 power derating curve Pd (W) 8 7 Copper Area 3x3 cm and via holes 6 5 STA335ML STA333BW STA333ML PowerSSO-36 PSSO36 4 3 Copper Area 2x2 cm and via holes 2 1 0 0 20 40 60 80 100 Tamb ( °C) 16/20 Doc ID 17638 Rev 4 120 140 160 STA335ML 7 Package mechanical data Package mechanical data Figure 16 on page 18 shows the package outline and the table below gives the dimensions. Table 8. PowerSSO-36 EPD dimensions Dimensions in mm Dimensions in inches Symbol Min Typ Max Min Typ Max A 2.15 - 2.47 0.085 - 0.097 A2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.00 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 4.90 - 7.10 0.193 - 0.280 In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 17638 Rev 4 17/20 h x 45° Package mechanical data 18/20 Figure 16. PowerSSO-36 EPD outline drawing Doc ID 17638 Rev 4 STA335ML STA335ML 8 Revision history Revision history Table 9. Document revision history Date Revision 09-May-2007 1 20-Feb-2008 2.0 Application note added 29-Sep-2008 2.1 Package information updated 18-Dec-2008 2.2 Overcurrent Limit removed 24-Jun-2010 18-Jul-2011 Changes Initial release. 3 Updated junction temperature range in Table 3: Absolute maximum ratings on page 6 Updated Table 7: Electrical specifications for power section on page 7 Removed max estimated dissipated power example on page 16 4 Updated Table 1: Device summary Removed Lrclko, Biclko, Sdatao from Figure 7 on page 10 Updated Figure 10: Applications schematic on page 13 Minor textual updates Doc ID 17638 Rev 4 19/20 STA335ML Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 20/20 Doc ID 17638 Rev 4