DDX-2100 All-Digital High Efficiency Power Amplifier GENERAL DESCRIPTION FEATURES • • • • • • HIGH OUTPUT CAPABILITY 2 x 50W into 8Ω or 1 x 100W into 4Ω SINGLE SUPPLY (+9V to +36V) SMALL PACKAGE HIGH EFFICIENCY, >88% THERMAL OVERLOAD AND SHORT CIRCUIT PROTECTION BENEFITS • • COMPLETE SURFACE MOUNT DESIGN POWER SUPPLY SAVINGS APPLICATIONS • • • • • DIGITAL POWERED SPEAKERS PC SOUND CARDS CAR AUDIO SURROUND SOUND SYSTEMS DIGITAL AUDIO COMPONENTS The DDX-2100 power device is a monolithic dual channel H-Bridge that can provide up to 50 watts per channel of audio power at very high efficiency. The DDX-2100 power device contains a logic interface, integrated bridge drivers, high efficiency MOSFET output transistors and protection circuitry. The device may be used as a dual bridge or reconfigured as a single bridge with double the output current capability. The benefits of the DDX amplification system are an all-digital design that eliminates the need for a digital to analog converter (DAC) and the high efficiency operation derived from the use of Apogee's patented damped ternary pulse width modulation (PWM). This approach provides an efficiency advantage over conventional Class-D designs and up to three times the efficiency of typical Class A/B amplifiers with music input signals. VCC1P INLA FET DRIVER IBIAS CONFIG PWRDN FAULT PROTECTION AND DRIVER LOGIC OUTPL OUTPL PGND1P VCC1N TRISTATE FET DRIVER TWARN OUTNL OUTNL GNDREF PGND1N INLB INRA VCC2P VSIG FET DRIVER VREG2 VREG2 OUTPR PGND2P VCC2N REGULATORS VREG1 VREG1 OUTPR FET DRIVER GNDR1 OUTNR OUTNR PGND2N INRB Figure 1. Block Diagram 1 Document #11010001-01 PRELIMINARY – subject to change without notice November 2001 DDX-2100 Absolute Maximum Ratings [Note 1] SYMBOL PARAMETER VCC VL Tj Tstg Power supply voltage Input logic reference Operating junction temperature range Storage temperature range VALUE UNIT 40V 5.5V -40 to +150 -40 to +150 V V °C °C Recommended Operating Conditions [Note 2] SYMBOL PARAMETER MIN TYP MAX UNIT VCC VL TA Power supply voltage Input logic reference Ambient Temperature 10.0 2.7 0 3.3 36.0 5.0 70 V V °C SYMBOL PARAMETER MIN TYP MAX UNIT θJC TjSD Twarn ThSD Thermal resistance junction-case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis 2.5 °C/W °C °C °C Thermal Data 150 130 25 Electrical Characteristics Refer to circuit Figure 2. VCC = 36V, VL = 3.3V, fsw = 384kHz, TA = 25C, RL = 8Ω unless otherwise specified. SYMBOL PARAMETER CONDITION Po Po UVL IPD Icctri Output power [Note 3] Output power [Note 3] Undervoltage Lockout Threshold Vcc supply current in Powerdown Supply current from Vcc in Tristate THD+N <1% THD+N <10% Icc Vcc supply current Isc Output Short-circuit Protection limit THD+N Total Harmonic Distortion+Noise [Note 3] SNR η RdsON RdsON matching ton toff tr tf Signal to Noise Ratio [Note 3] Efficiency Power MOSFET output resistance MIN TRISTATE = 0 2-Chan. switching at 384 KHz. Speaker outputs. Po=1 Wrms Po=50 Wrms A-Weighted Po=2 x 50 W Id=1A Id=1A Turn-on delay time Turn-off delay time Rise time Fall Time Resistive load Resistive load Resistive load Resistive load VIL Low logic input voltage on PWRDN, TRISTATE pins VL = 2.7V VL = 3.3V VL = 5.0V VIH High logic input voltage on PWRDN, TRISTATE pins VL = 2.7V VL = 3.3V VL = 5.0V VIL, PWM Inputs Low logic input voltage on INLA, INLB, INRA, INRB pins VL = 2.7V VL = 3.3V VL = 5.0V VIH, PWM Inputs High logic input voltage on INLA, INLB, INRA, INRB pins VL = 2.7V VL = 3.3V VL = 5.0V Ifault Pwmin Output Sink Current, FAULT, TWARN pins Minimum output pulse width Fault Active No load TYP 50 75 7 1 25 MAX 9 3 75 3.5 5.0 .07 .50 90 88 200 UNIT Wrms Wrms V mA mA mA 6.5 270 95 A % % dB % mΩ % 100 100 25 25 0.7 0.8 0.85 ns ns ns ns V 1.5 1.7 1.85 1.05 1.35 2.2 V V 1.65 1.95 2.8 1 70 150 V mA ns 2 Document #11010001-01 PRELIMINARY – subject to change without notice November 2001 DDX-2100 Electrical Characteristics (continued) Note 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: Performance not guaranteed beyond recommended operating conditions. Note 3: Characteristics are for the DDX-2100 power device driven by DDX-2000 processor. Logic Truth Table TRISTATE INxA INxB OUTPx OUTNx OUTPUT MODE 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 OFF GND GND VCC VCC OFF GND VCC GND VCC Hi-Z DAMPED NEGATIVE POSITIVE Not Used DDX-2100 Pin Function Description PWM Inputs Pin Name Pin No. INLA Description 29 Left A logic input signal INLB 30 Left B logic input signal INRA 31 Right A logic input signal INRB 32 Right B logic input signal Control/Miscellaneous Pin Name Pin No. Description PWRDN 25 Power Down (0=Shutdown, 1= Normal). TRI-STATE 26 FAULT [Note 4] 27 TWARN [Note 4] 28 CONFIG [Note 5] 24 Tri-State (0=All MOSFETS Hi-Z, 1=Normal). Fault output indicator; Overcurrent Overtemperature 1=Normal). Thermal warning output (0=Warning TJ >= 130°C, 1=Normal). Configuration (0=Normal, 1=Parallel operation for mono). NC 18 Do not connect. (0=Fault, Power Outputs [Note 6] Pin Name Pin No. Description OUTPL 16, 17 Left output, positive reference OUTNL 10, 11 Left output, negative reference OUTPR 8, 9 Right output, positive reference OUTNR 2, 3 Right output, negative reference Note 4: FAULT and TWARN outputs are open-drain Note 5: Connect CONFIG Pin 24 to VREG1 Pins 21,22 to implement single bridge operation for high current. Note 6: DDX outputs are bridged. The outputs OUTPx produce signals in phase with the input. 3 Document #11010001-01 PRELIMINARY – subject to change without notice November 2001 DDX-2100 Power Supplies Pin Name Pin No. Description VCC [1P, 1N, 2P, 2N] 4, 7, 12, 15 Power PGND [1P, 1N, 2P, 2N] 5, 6, 13, 14 Power grounds VREG1 21, 22 Internal regulator voltage requires bypass capacitor. VREG2 33, 34 Internal regulator voltage requires bypass capacitor. VSIG 35, 36 Signal Positive supply. VL 23 Logic reference voltage. GNDREF 19 Logic reference ground. GNDS 1 Substrate ground. GNDR1 20 Internal regulator ground. 4 Document #11010001-01 PRELIMINARY – subject to change without notice November 2001 DDX-2100 22uH LEFT+ 100nF 21 100nF 22 23 +3.3V 24 CT 100nF 10k RT 25 EAPD 26 27 28 TWARN 10k LEFTA LEFTB RIGHTA +3.3V RIGHTB 29 30 31 32 33 100nF 34 35 36 NC GNDR1 OUTPL VREG1 OUTPL VREG1 VCC1P VL PGND1P CONFIG PGND1N PWRDN VCC1N TRI-STATE OUTNL FAULT OUTNL TWARN OUTPR INLA OUTPR VCC2P INLB INRA PGND2P INRB PGND2N VCC2N VREG2 VREG2 OUTNR VSIG OUTNR VSIG GNDS 18 2200uF 17 VB+ 20 6.2 100nF + GNDREF C43 470nF FILM 16 1uF 15 330pF + 20 14 100nF 8ohm SPEAKER 6.2 100nF 13 LS1 12 100nF 11 22uH 10 LEFT- 9 22uH 8 7 RIGHT+ 1uF + 19 100nF 6 100nF VB+ 5 100nF 4 3 20 6.2 100nF 2 LS2 470nF 1 330pF DDX2100 100nF 100nF 6.2 8ohm SPEAKER 100nF 22uH RIGHT- Figure 2. Stereo Audio Application Circuit 10uH 21 100nF CT 22 23 +3.3V 10k RT 100nF EAPD2 24 25 26 27 28 TWARN2 29 10k 30 LFEA 31 +3.3V 32 LFEB 33 100nF 34 35 100nF 36 GNDR1 OUTPL VREG1 OUTPL VREG1 VCC1P VL PGND1P CONFIG PGND1N PWRDN VCC1N TRI-STATE OUTNL FAULT OUTNL TWARN OUTPR INLA OUTPR INLB VCC2P INRA PGND2P INRB PGND2N VREG2 VCC2N VREG2 OUTNR VSIG OUTNR VSIG GNDS 17 2200uF VB+ 16 SUB+ 220nF + NC 1uF 15 + 20 100nF GNDREF 18 14 3.0 100nF 13 12 220nF 10 11 10 3.0 9 220nF 680pF 8 7 LS1 1uF 4ohm SPEAKER 220nF 100nF 6 5 4 3 2 VB+ 1uF + 19 10uH SUB- 1 DDX2100 Figure 3. Mono Audio Application Circuit 5 Document #11010001-01 PRELIMINARY – subject to change without notice November 2001 DDX-2100 DDX-2100 POWER DEVICE The DDX-2100 Power Device is a dual channel H-Bridge that can deliver over 50 watts per channel of audio output power at very high efficiency. It converts DDX controlled PWM signals to power at the load. The DDX-2100 includes a logic interface, integrated bridge drivers, high efficiency MOSFET outputs, thermal and short circuit protection circuitry. Two logic level signals per channel are used to control highspeed MOSFET switches to connect the speaker load to the input supply or to ground in a bridge configuration, according to Apogee's patented damped ternary PWM. The DDX-2100 includes over-current, thermal and under-voltage lockout with automatic recovery. A thermal warning status is also provided. INL[1:2] INR[1:2] VL PWRDN OUTPL Logic I/F and Decode Left H-Bridge OUTNL TRI-STATE FAULT TWARN Protection Circuitry OUTPR Right H-Bridge Regulators OUTNR Figure 4. DDX-2100 Block Diagram Logic Interface and Decode The DDX-2100 power outputs are controlled using two logic level timing signals. In order to provide a proper logic interface, the VL input must operate at the same voltage as the DDX controller logic supply. Protection Circuitry The DDX-2100 includes protection circuitry for over-current and thermal overload conditions. A thermal warning pin TWARN is activated low (open-drain MOSFET) when the IC temperature exceeds 130°C, in advance of the thermal shutdown protection. When a fault condition is detected (logical OR of over-current and thermal), an internal fault signal acts to immediately disable the output power MOSFETs, placing both Hbridges in a high impedance state. At the same time an open-drain MOSFET connected to the FAULT pin is switched on. There are two possible modes subsequent to activating a fault. The first is a SHUTDOWN mode. With FAULT (pull-up resistor) and TRI-STATE pins independent, an activated fault will disable the device, signaling low at the FAULT output. The device may subsequently be reset to normal operation by toggling the TRI-STATE pin from High to Low to High using an external logic signal. The second is an AUTOMATIC recovery mode. This is depicted in the application circuit, Figure 2. The FAULT and TRI-STATE pins are shorted together and connected to a time constant circuit comprising RT and CT. An activated FAULT will force a reset on the TRI-STATE pin causing normal operation to resume following a delay determined by the time constant of the circuit. If the fault condition is still presented, the circuit operation will continue repeating until such time as the fault condition is removed. An increase in the time constant of the circuit will produce a longer recovery interval. Care must be taken in the overall system design so as not to exceed the protection thresholds under normal operation. Power Outputs The DDX-2100 power and output pins are duplicated to provide a low impedance path for the devices bridged outputs. All duplicate power, ground and output pins must be connected for proper operation. The PWRDN or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state during power-up until the logic power supply, VL, is settled. Parallel Output/High Current Operation The DDX-2100 outputs can be connected in parallel to increase the output current to a load. In this configuration the device can provide over 100W into 4Ω (see Figure 3). This mode is enabled with the CONFIG pin connected to VREG1 and the inputs combined INLA = INLB, INRA = INRB and outputs combined OUTLA = OUTLB, OUTRA = OUTRB. ADDITIONAL INFORMATION Output Filter A passive two-pole low pass filter is used on the DDX-2100 power outputs to reconstruct an analog signal. System performance can be significantly affected by the output filter design and choice of components. A filter design for 8Ω loads is shown in Figure 2, and for 4Ω loads in Figure 3. 6 Document #11010001-01 PRELIMINARY – subject to change without notice November 2001 DDX-2100 Power Dissipation/Heat Sink Requirements The power dissipation of the device will depend primarily on the supply voltage, load impedance, and output modulation level. The DDX-2100 surface mount package includes an exposed thermal pad on the top of the device to provide a direct thermal path from the integrated circuit to the heatsink. This pad should be fastened to a low thermal impedance path at circuit ground potential for proper operation.. For continuous duty rated applications, careful consideration must be made to the overall thermal design. For additional thermal design considerations, see http://www.apogeeddx.com/DDX_Themal_Consid erations.PDF Typical Performance Characteristics at Vcc=36V Figure 5: Efficiency Figure 6: Frequency Response 100 +3 90 80 Efficiency (%) +1.5 70 60 d B r 50 -0 A 40 30 -1.5 20 10 -3 20 0 0 10 20 30 40 50 60 70 80 90 100 110 50 100 200 500 120 1k 2k 5k 10k 20k Hz Total Output Power (Watts) 7 Document #11010001-01 PRELIMINARY – subject to change without notice November 2001 DDX-2100 Typical Performance Characteristics at Vcc=36V, 8Ω Load, Stereo Mode Figure 7: THD+N vs. Frequency Figure 8: THD+N vs. Output Power @ 1kHz 1 20 10 0.5 5 2 0.2 1 % 1W 0.1 % 0.5 0.2 0.05 0.1 10W 0.05 0.02 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 0.01 100m 20k 200m 500m 1 2 5 10 20 50 80 W Hz Typical Performance Characteristics at Vcc=36V, 4Ω Load, Mono Mode Figure 9: THD+N vs. Frequency Figure 10: THD+N vs. Output Power @ 1kHz 20 1 10 0.5 5 1W 2 0.2 1 % 0.1 % 10W 0.5 0.2 0.05 0.1 0.05 0.02 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 0.01 100m 200m 500m 1 2 Hz 5 10 20 50 100 W rm s 8 Document #11010001-01 PRELIMINARY – subject to change without notice November 2001 DDX-2100 PHYSICAL DIMENSIONS (Dimensions shown in mm) Information furnished in this publication is believed to be accurate and reliable. However, Apogee Technology, Inc. assumes no responsibility for its use, or for any infringements of patents or other rights of third parties that may result form its use. Specifications in this publication are subject to change without notice. This publication supersedes and replaces all information previous supplied. Apogee Technology, Inc. All Rights Reserved 9 Document #11010001-01 PRELIMINARY – subject to change without notice November 2001