STMICROELECTRONICS STM6822

STM6321/6322
STM6821/6822/6823/6824/6825
5-pin supervisor with watchdog timer and push-button reset
Features
■
Precision VCC monitoring of 5, 3.3, 3, or 2.5 V
power supplies
■
RST outputs (active-low, push-pull or open
drain)
■
RST outputs (active-high, push-pull)
■
Reset pulse width of 1.4 ms, 200 ms and
240 ms (typ)(a)
■
Watchdog timeout period of 1.6 s (typ)(a)
■
Manual reset input (MR)
■
Low supply current - 3 µA (typ)
■
Guaranteed RST (RST) assertion down to
VCC = 1.0 V
■
Operating temperature: –40 to +85°C
(industrial grade)
■
RoHS compliance
Lead-free components are compliant with the
RoHS directive
a.
Other trec and watchdog timings are
offered. Minimum order quantities may
apply. Contact local sales office for
availability.
Table 1.
SOT23-5 (WY)
Device summary
Reset output
Part number
Watchdog input
STM6321
✔
STM6322
Manual reset
input
Active-high
(push-pull)
Active-low
(open drain)
✔
✔
✔
✔
✔
✔
STM6821
✔
✔
STM6822
✔
✔
STM6823
✔
✔
STM6824
✔
STM6825
April 2009
Active-low
(push-pull)
✔
✔
✔
Rev 9
✔
✔
✔
✔
1/29
www.st.com
1
Contents
STM6321/6322STM6821/6822/6823/6824/6825
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1
Active-low, push-pull reset output (RST) - 6823/6824/6825 . . . . . . . . . . 7
1.1.2
Active-low, open drain reset output (RST) - STM6321/6322/6822 . . . . . 7
1.1.3
Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.4
Watchdog input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.5
Active-high reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Open drain RST output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Push-button reset input (STM6322/6821/6822/6823/6825) . . . . . . . . . . . 11
2.4
Watchdog input (STM6321/6821/6822/6823/6824) . . . . . . . . . . . . . . . . . 11
2.5
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6
2.5.1
Watchdog input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.2
Ensuring a valid reset output down to VCC = 0 V . . . . . . . . . . . . . . . . . . 11
Interfacing to microprocessors with bidirectional reset pins . . . . . . . . . . . 12
3
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
STM6321/6322STM6821/6822/6823/6824/6825
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC and AC characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SOT23-5 – 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 24
Carrier tape dimensions for SOT23-5 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
List of figures
STM6321/6322STM6821/6822/6823/6824/6825
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
4/29
Logic diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic diagram (STM6321/6322/6824/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
STM6822/6823 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM6821 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM6322/6825 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM6321/6824 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram (STM6321/6824) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram (STM6322/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STM6321/6322/6822 open drain RST output with multiple supplies . . . . . . . . . . . . . . . . . 10
Ensuring RST valid to VCC = 0, (active-low push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 12
Ensuring RST valid to VCC = 0, (active-high, push-pull outputs) . . . . . . . . . . . . . . . . . . . . 12
Interfacing to microprocessors with bidirectional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCC-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Supply current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MR-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Normalized power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Normalized reset threshold voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Normalized power-up watchdog timeout period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Voltage output low vs. ISINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Voltage output high vs. ISOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 24
Carrier tape for SOT23-5 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM6321/6322STM6821/6822/6823/6824/6825
1
Description
Description
The STM6xxx supervisors are self-contained devices which provide microprocessor
supervisory functions. A precision voltage reference and comparator monitors the VCC input
for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output
(RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer
(except for STM6322/6825) and/or a push-button (MR) reset input.
These devices are available in a standard 5-pin SOT23 package.
Figure 1.
Logic diagram (STM6821/6822/6823)
VCC
WDI
RST (RST)(1)
STM6XXX
MR
VSS
AI09128
1. For STM6821 only.
Figure 2.
Logic diagram (STM6321/6322/6824/6825)
VCC
RST
(WDI)(1) MR
STM6XXX
RST
VSS
AI09129
1. For STM6321/6824.
Table 2.
Signal names
MR
Push-button reset input
WDI
Watchdog input
RST
Active-low reset output
RST
Active-high reset output
VCC
Supply voltage
VSS
Ground
5/29
Description
STM6321/6322STM6821/6822/6823/6824/6825
Figure 3.
STM6822/6823 SOT23-5 connections
SOT23-5
(1)
RST
VSS
MR
1
2
3
5
VCC
4
WDI
AI09130a
1. Open drain for STM6822.
Figure 4.
STM6821 SOT23-5 connections
SOT23-5
RST(1)
VSS
MR
1
2
3
VCC
5
WDI
4
AI12285
1. Push-pull only.
Figure 5.
STM6322/6825 SOT23-5 connections
SOT23-5
RST(1)
VSS
RST(2)
1
2
3
5
VCC
4
MR
AI09131a
1. Open drain for STM6322.
2. Push-pull only.
Figure 6.
STM6321/6824 SOT23-5 connections
SOT23-5
RST(1)
VSS
RST(2)
1
2
3
5
4
VCC
WDI
AI12286
1. Open drain for STM6321.
2. Push-pull only.
6/29
STM6321/6322STM6821/6822/6823/6824/6825
Description
1.1
Pin descriptions
1.1.1
Active-low, push-pull reset output (RST) - 6823/6824/6825
Pulses low when triggered, and stays low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after either VCC rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high.
1.1.2
Active-low, open drain reset output (RST) - STM6321/6322/6822
Pulses low when triggered, and stays low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after either VCC rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high. Connect a pull-up
resistor to supply voltage.
1.1.3
Push-button reset input (MR)
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for trec after MR returns high. This active-low input has an internal 52 kΩ pull-up. It can
be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
1.1.4
Watchdog input (WDI)
If WDI remains high or low for at least 1.6s, the internal watchdog timer expires and reset is
asserted. The internal watchdog timer clears while reset is asserted or when WDI sees a
rising or falling edge. The watchdog function CAN be disabled if WDI is left unconnected or
is connected to a tri-state buffer output.
1.1.5
Active-high reset output (RST)
Active-high, push-pull reset output; inverse of RST.
Table 3.
Pin functions
Pin
STM6822
STM6823
STM6821
STM6321
STM6322
STM6824
STM6825
Name
Function
1
—
1
1
RST
Active-low reset output
3
3
—
4
MR
Push-button reset input
4
4
4
—
WDI
Watchdog Input
—
1
3
3
RST
Active-high reset output
5
5
5
5
VCC
Supply voltage
2
2
2
2
VSS
Ground
7/29
Description
STM6321/6322STM6821/6822/6823/6824/6825
Figure 7.
Block diagram (STM6821/6822/6823)
WDI
Transitional
Detector
WDI
WATCHDOG
TIMER
VCC
VRST
VCC
COMPARE
trec
Generator
(1,2)
RST (RST)
MR
AI09132a
1. Push-pull for STM6823, open drain for STM6822.
2. Active-high (push-pull) for STM6821.
Figure 8.
Block diagram (STM6321/6824)
WDI
Transitional
Detector
WDI
WATCHDOG
TIMER
VCC
VRST
COMPARE
trec
Generator
RST(1)
RST(2)
A12287
3. Active-low (open drain) for STM6321, active-low (push-pull) for STM6824.
4. Push-pull only.
Figure 9.
Block diagram (STM6322/6825)
VCC
VCC
VRST
COMPARE
trec
Generator
RST(1)
RST(2)
MR
AI12288
1. Active-low (open drain) for STM6322, active-low (push-pull) for STM6825.
2. Push-pull only.
8/29
STM6321/6322STM6821/6822/6823/6824/6825
Description
Figure 10. Hardware hookup
VCC
VCC
0.1μF
From Microprocessor
Push-button
STM6XXX
(1)
WDI
MR
(2)
(3)
To Microprocessor Reset
RST(4)
To Microprocessor Reset
RST (RST)
AI09133
1. For STM6321/6821/6822/6823/6824
2. For STM6322/6821/6822/6823/6825
3. For STM6821/ (RST output only)
4. For STM6321/6322/6824/6825 (both RST and RST outputs)
9/29
Operation
STM6321/6322STM6821/6822/6823/6824/6825
2
Operation
2.1
Reset output
The STM6xxx supervisor asserts a reset signal to the MCU whenever VCC goes below the
reset threshold (VRST), a watchdog timeout occurs, or when the push-button reset input
(MR) is taken low. Reset is guaranteed valid for VCC < VRST down to VCC =1 V for TA = 0°C
to 85°C.
During power-up, once VCC exceeds the reset threshold an internal timer keeps reset low
for the reset timeout period, trec. After this interval reset is de-asserted.
Each time RST is asserted, it stays low for at least the reset timeout period (trec). Any time
VCC goes below the reset threshold the internal timer clears. The reset timer starts when
VCC returns above the reset threshold.
2.2
Open drain RST output
The STM6321/6322/6822 have an active-low, open drain reset output. This output structure
will sink current when RST is asserted. Connect a pull-up resistor from RST to any supply
voltage up to 6 V (see Figure 11). Select a resistor value large enough to register a logic
low, and small enough to register a logic high while supplying all input current and leakage
paths connected to the reset output line. A 10 kΩ pull-up resistor is sufficient in most
applications.
Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies
3.3V
5.0V
VCC
STM6XXX
10k
5V System
(1)
MR
(2)
WDI
RST(3)
RST
GND
AI09137
1. STM6322/6822
2. STM6321/6822
3. STM6321/6322
10/29
STM6321/6322STM6821/6822/6823/6824/6825
2.3
Operation
Push-button reset input (STM6322/6821/6822/6823/6825)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see
Figure 25 on page 19) after it returns high. The MR input has an internal 52 kΩ pull-up
resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic
levels or with open-drain/collector outputs. Connect a normally open momentary switch from
MR to GND to create a manual reset function; external debounce circuitry is not required. If
MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF
capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to
VCC when not used.
2.4
Watchdog input (STM6321/6821/6822/6823/6824)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within tWD (1.6 sec), the reset is asserted. The internal
watchdog timer is cleared by either:
1.
a reset pulse, or
2.
by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
Note:
The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
2.5
Applications information
2.5.1
Watchdog input current
The WDI input is internally driven through a buffer and series resistor from the watchdog
counter. For minimum watchdog input current (minimum overall power consumption), leave
WDI low for the majority of the watchdog timeout period. When high, WDI can draw as much
as 160 µA. Pulsing WDI high at a low duty cycle will reduce the effect of the large input
current. When WDI is left unconnected, the watchdog timer is serviced within the watchdog
timeout period by a low-high-low pulse from the counter chain.
2.5.2
Ensuring a valid reset output down to VCC = 0 V
The STM6xxx supervisors are guaranteed to operate properly down to VCC = 1 V. In
applications that require valid reset levels down to VCC = 0, a pull-down resistor to activelow outputs (push/pull only, see Figure 12 on page 12) and a pull-up resistor to active-high
outputs (push/pull only, see Figure 13 on page 12) will ensure that the reset line is valid
while the reset output can no longer sink or source current. This scheme does not work with
the open drain outputs of the STM6321/6322/6822.
The resistor value used is not critical, but it must be large enough not to load the reset
output when VCC is above the reset threshold. For most applications, 100 kΩ is adequate.
11/29
Operation
STM6321/6322STM6821/6822/6823/6824/6825
Figure 12. Ensuring RST valid to VCC = 0, (active-low push-pull outputs)
STM6XXX
VCC
VCC
GND
RST
R1
AI09138
Figure 13. Ensuring RST valid to VCC = 0, (active-high, push-pull outputs)
VCC
STM6XXX
R1
VCC
GND
RST
AI09139
1. This configuration does not work on open drain outputs of the STM6321/6322/6822.
2.6
Interfacing to microprocessors with bidirectional reset pins
Microprocessors with bidirectional reset pins can contend with the STM6321 / 6322 / 6821 /
6822 / 6823 / 6824 / 6825 reset output. For example, if the reset output is driven high and the
microprocessor wants to pull it low, signal contention will result. To prevent this from
occurring, connect a 4.7 kΩ resistor between the reset output and the microprocessor’s
reset I/O as in Figure 14.
Figure 14. Interfacing to microprocessors with bidirectional reset I/O
Buffered Reset to other
System Components
VCC
VCC
STM6XXX
Microprocessor
4.7k
RST
GND
RST
GND
AI09135
12/29
STM6321/6322STM6821/6822/6823/6824/6825
Typical operating characteristics
Figure 15. VCC-to-reset output delay vs. temperature
35
Reset Output Delay (µs)
30
25
20
15
10
5
0
–40
–20
0
20
40
60
80
Temperature (˚C)
AI09627a
Figure 16. Supply current vs. temperature
7
6
Supply Current (µA)
3
Typical operating characteristics
5
4
VCC = 3V
VCC = 5V
3
2
1
0
–40
–20
0
20
Temperature (˚C)
40
60
80
AI09628a
13/29
Typical operating characteristics
STM6321/6322STM6821/6822/6823/6824/6825
Figure 17. MR-to-reset output delay vs. temperature
Reset Output Delay (ns)
600
500
400
300
200
100
0
–40
–20
0
20
40
60
80
Temperature (˚C)
AI09669
Figure 18. Normalized power-up trec vs. temperature
Normalized Power-up trec
1.05
1.04
1.03
1.02
1.01
1.00
0.99
–40
–20
0
20
Temperature (˚C)
14/29
40
60
80
AI09670
STM6321/6322STM6821/6822/6823/6824/6825
Typical operating characteristics
Figure 19. Normalized reset threshold voltage vs. temperature
1.05
Normalized Reset Threshold Voltage
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
–40
–20
0
20
40
60
80
Temperature (˚C)
AI09631a
Normalized Watchdog Time-out Period
Figure 20. Normalized power-up watchdog timeout period
1.05
1.04
1.03
1.02
1.01
1.00
0.99
–40
–20
0
20
Temperature (˚C)
40
60
80
AI09671
15/29
Typical operating characteristics
STM6321/6322STM6821/6822/6823/6824/6825
Figure 21. Voltage output low vs. ISINK
0.35
0.30
VOUT (V)
0.25
0.20
VCC = 2.9V
0.15
0.10
0.05
0.00
0
1
2
3
4
5
6
ISINK (mA)
AI09634a
Figure 22. Voltage output high vs. ISOURCE
2.92
2.90
2.88
VOUT (V)
2.86
2.84
VCC = 2.9V
2.82
2.80
2.78
2.76
2.74
0.0
0.1
0.2
0.3
0.4
0.5
0.6
ISOURCE (mA)
16/29
0.7
0.8
0.9
1.0
AI09635a
STM6321/6322STM6821/6822/6823/6824/6825
Typical operating characteristics
Figure 23. Maximum transient duration vs. reset threshold overdrive
35
Transient Duration (µs)
30
25
S
20
Z
15
L
10
5
0
0
20
40
60
80
100
120
140
Reset Threshold Overdrive (mV)
160
180
200
AI09637a
17/29
Maximum ratings
4
STM6321/6322STM6821/6822/6823/6824/6825
Maximum ratings
Stressing the device above the rating listed in Table 4 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
documents.
Table 4.
Absolute maximum ratings
Symbol
TSTG
(1)
Parameter
Storage temperature (VCC off)
Unit
–55 to 150
°C
260
°C
–0.3 to VCC + 0.3
V
Supply voltage
–0.3 to 7.0
V
IO
Output current
20
mA
PD
Power dissipation
320
mW
TSLD
Lead solder temperature for 10 seconds
Value
VIO
Input or output voltage
VCC
1. Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seconds).
18/29
STM6321/6322STM6821/6822/6823/6824/6825
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 5. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 5.
Operating and AC measurement conditions
Parameter
STM6xxx
Unit
VCC supply voltage
1.0 to 5.5
V
Ambient operating temperature (TA)
–40 to 85
°C
≤5
ns
Input pulse voltages
0.2 to 0.8VCC
V
Input and output timing ref. voltages
0.3 to 0.7VCC
V
Input rise and fall times
Figure 24. AC testing input/output waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Figure 25. MR timing waveform
MR
tMLRL
RST
(1)
tMLMH
trec
AI07837a
1. RST for STM6322/6821/6825.
Figure 26. Watchdog timing
VCC
RST
WDI
trec
tWD
AI09136
19/29
DC and AC parameters
Table 6.
Sym
VCC
ICC
ILI
STM6321/6322STM6821/6822/6823/6824/6825
DC and AC characteristic
Alternative
Test condition (1)
Description
Typ
1.2 (2)
Operating voltage
Max
Unit
5.5
V
VCC supply current
(MR and WDI unconnected)
T/S/R/Z/Y (VCC < 3.6 V)
4
12
µA
L/M (VCC < 5.5 V)
6
17
µA
VCC supply current
(MR unconnected;
STM6322/6825)
T/S/R/Z/Y (VCC < 3.6 V)
3
8
µA
L/M (VCC < 5.5 V)
3
12
µA
+1
µA
160
µA
Input leakage current
0V = VIN = VCC
Input leakage current
(WDI)(3)
WDI = VCC, time average
ILO
Open drain reset output
leakage current
VIH
Input high voltage (MR)
(4)
VIH
Input high voltage (WDI)
VIL
Input low voltage (MR)
VIL
Input low voltage (WDI) (4)
Output low voltage (RST;
push-pull or open drain)
VOL
Output low voltage (RST;
push-pull only)
20/29
Min
–1
120
WDI = GND, time average
–20
–15
µA
VCC > VRST,
Reset not asserted
–1
VRST > 4.0 V
2.0
V
VRST < 4.0 V
0.7VCC
V
VRST (max) < VCC < 5.5 V
0.7VCC
V
+1
µA
VRST > 4.0 V
0.8
V
VRST < 4.0 V
0.3VCC
V
VRST (max) < VCC < 5.5 V
0.3VCC
V
VCC ≥ 1.0 V, ISINK = 50 µA,
Reset asserted
0.3
V
VCC ≥ 1.2 V, ISINK = 100 µA,
Reset asserted
0.3
V
VCC ≥ 2.7 V, ISINK = 1.2 mA,
Reset asserted
0.3
V
VCC ≥ 4.5 V, ISINK = 3.2 mA,
Reset asserted
0.4
V
VCC ≥ 2.7 V, ISINK = 1.2 mA,
Reset not asserted
0.3
V
VCC ≥ 4.5 V, ISINK = 3.2 mA,
Reset not asserted
0.4
V
STM6321/6322STM6821/6822/6823/6824/6825
Table 6.
Sym
DC and AC parameters
DC and AC characteristic (continued)
Alternative
Description
Output high voltage (RST)
VOH
Output high voltage (RST)
Test condition (1)
Min
VCC ≥ 2.7 V, ISOURCE = 500 µA,
Reset not asserted
0.8VCC
V
VCC ≥ 4.5 V, ISOURCE = 800 µA
, Reset not asserted
0.8VCC
V
VCC ≥ 1.0 V, ISOURCE = 1 µA,
Reset asserted (0°C to 85°C)
0.8VCC
V
VCC ≥ 1.5 V, ISOURCE = 100 µA,
Reset asserted
0.8VCC
V
VCC ≥ 2.55 V, ISOURCE = 500 µA,
0.8VCC
Reset asserted
V
VCC ≥ 4.25 V, ISOURCE = 800 µA,
0.8VCC
Reset asserted
V
Typ
Max
Unit
Reset thresholds
25°C
4.561
–40 to 85°C
4.514
25°C
4.314
–40 to 85°C
4.270
25°C
3.040
–40 to 85°C
3.000
25°C
2.890
–40 to 85°C
2.857
25°C
2.590
–40 to 85°C
2.564
25°C
2.266
–40 to 85°C
2.243
25°C
1.970
–40 to 85°C
1.950
4.630
4.699
V
4.746
V
4.446
V
4.490
V
3.110
V
3.150
V
2.960
V
3.000
V
2.660
V
2.696
V
2.335
V
2.358
V
2.030
V
2.050
V
STM6xxxL
4.390
STM6xxxM
3.080
STM6xxxT
VRST(5)
Reset threshold
2.930
STM6xxxS
2.630
STM6xxxR
2.300
STM6xxxZ
2.000
STM6xxxY
L/M versions
10
mV
T/S/R/Z/Y versions
5
mV
20
µs
Reset threshold hysteresis
VCC to RST delay
(VRST – VCC = 100 mV, VCC
falling at 1 mV/µs)
trec
(6)
Reset pulse width
A
1
1.4
2
ms
Blank
140
200
280
ms
J
240
360
480
ms
21/29
DC and AC parameters
Table 6.
Sym
STM6321/6322STM6821/6822/6823/6824/6825
DC and AC characteristic (continued)
Alternative
Test condition (1)
Description
Min
Reset threshold
temperature coefficient
Typ
Max
40
Unit
ppm/C
Push-button reset input
tMLMH
tMR
MR pulse width
1
µs
tMLRL
tMRD
MR to RST output delay
500
ns
MR glitch immunity
100
ns
MR pull-up resistor
35
52
75
kΩ
Watchdog timeout period
1.12
1.60
2.24
s
Watchdog timer
tWD (6)
(7)
WDI pulse width
VCC ≥ 3.0 V
50
ns
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5 V for “L/M” versions; VCC = 2.7 to 3.6 V for
“T/S/R” versions; and VCC = 1.2 to 2.75 V for “Z/Y” version (except where noted).
2. VCC (min) = 1.0 V for TA = 0 to +85°C.
3. WDI input is designed to be driven by a three-state output device. To float WDI, the “high-impedance mode” of the output
device must have a maximum leakage current of 10 µA and a maximum output capacitance of 200 pF. The output device
must also be able to source and sink at least 200 µA when active.
4. WDI is internally serviced within the watchdog period if WDI is left unconnected.
5. The leakage current measured on the RST pin is tested with the reset asserted (output high impedance).
6. Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact local sales office for availability.
7.
For VCC < 3.0 V, tWD(min) = 100 ns.
22/29
STM6321/6322STM6821/6822/6823/6824/6825
6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
23/29
Package mechanical data
STM6321/6322STM6821/6822/6823/6824/6825
Figure 27. SOT23-5 – 5-lead small outline transistor package mechanical drawing
1. Drawing is not to scale.
Table 7.
SOT23-5 – 5-lead small outline transistor package mechanical data
mm
inches
Symb
A
Typ
Min
Max
Typ
Min
Max
1.20
0.90
1.45
0.047
0.035
0.057
A1
0.15
A2
1.05
0.90
1.30
0.041
0.035
0.051
B
0.40
0.35
0.50
0.016
0.014
0.020
C
0.15
0.09
0.20
0.006
0.004
0.008
2.80
3.00
0.114
0.110
0.118
0.102
0.118
0.059
0.069
0°
10°
0.004
0.024
D
2.90
D1
1.90
E
2.80
e
0.95
F
1.60
K
L
24/29
0.006
0.35
0.075
2.60
3.00
0.110
0.037
1.50
1.75
0°
10°
0.10
0.60
0.063
0.014
STM6321/6322STM6821/6822/6823/6824/6825
Package mechanical data
Figure 28. Carrier tape for SOT23-5 package
P0
E
P2
D
T
A0
F
TOP COVER
TAPE
W
B0
P1
CENTER LINES
OF CAVITY
K0
USER DIRECTION OF FEED
AM03073v1
Table 8.
Carrier tape dimensions for SOT23-5 package
Package
W
D
SOT23-5
8.00
+0.30
–0.10
1.50
+0.10/
–0.00
E
P0
P2
F
4.00
2.00
3.50
1.75
±0.10 ±0.10 ±0.10 ±0.05
A0
B0
K0
P1
3.23
±0.10
3.17
±0.10
1.37
±0.10
4.00
±0.10
T
Unit
Bulk
Qty
0.254
mm 3000
±0.013
25/29
Part numbering
7
STM6321/6322STM6821/6822/6823/6824/6825
Part numbering
Table 9.
Ordering information scheme
Example:
STM6xxx
L
WY
6
E
Device type
STM6xxx
Reset threshold voltage
L: VRST = 4.514 to 4.746 V
M: VRST = 4.270 to 4.490 V
T: VRST = 3.000 to 3.150 V
S: VRST = 2.850 to 3.000 V
R: VRST = 2.564 to 2.696 V
Z: VRST = 2.243 to 2.358 V
Y: VRST = 1.950 to 2.050 V
Reset pulse width (1)
A: trec = 1 to 2 ms
Blank: trec = 140 to 280 ms
J: trec = 240 to 480 ms
Package
WY = SOT23-5
Temperature range
6 = –40 to 85°C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape & reel
1. Contact local sales office for availability. Other trec and watchdog timings are offered. Minimum order
quantities may apply. Contact local sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
26/29
STM6321/6322STM6821/6822/6823/6824/6825
Table 10.
Note:
Part numbering
Marking description
Part number
Reset threshold (V)
Reset pulse width (ms)
Topside marking
STM6321LWY6F
STM6321MAWY6F
STM6321MWY6F
STM6321TWY6F
STM6321SWY6F
STM6321RWY6F
STM6322LWY6F
STM6322MWY6F
STM6322TWY6F
STM6322SWY6F
STM6322RWY6F
STM6821LWY6F
STM6821MWY6F
STM6821TWY6F
STM6821SWY6F
STM6821RWY6F
STM6822LWY6F
STM6822MWY6F
STM6822TWY6F
STM6822SWY6F
STM6822RWY6F
STM6822ZWY6F
STM6822YWY6F
STM6823LWY6F
STM6823MWY6F
STM6823TJWY6F
STM6823TWY6F
STM6823SJWY6F
STM6823SWY6F
STM6823RJWY6F
STM6823RWY6F
STM6824LWY6F
STM6824MWY6F
STM6824TWY6F
STM6824SWY6F
STM6824RWY6F
STM6825LWY6F
STM6825MWY6F
STM6825TWY6F
STM6825SWY6F
STM6825RWY6F
4.630
4.390
4.390
3.080
2.930
2.630
4.630
4.390
3.080
2.930
2.630
4.630
4.390
3.080
2.930
2.630
4.630
4.390
3.080
2.930
2.630
2.300
2.000
4.630
4.390
3.080
3.080
2.930
2.930
2.630
2.630
4.630
4.390
3.080
2.930
2.630
4.630
4.390
3.080
2.930
2.630
200
1.4
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
280
200
280
200
280
200
200
200
200
200
200
200
200
200
200
200
5AUx
5CRx
5AVx
5AWx
5AXx
5AYx
5BAx
5BBx
5BCx
5BDx
5BEx
5BGx
5BHx
5BJx
5BKx
5BLx
5BNx
5BPx
5BQx
5BRx
5BSx
5BTx
5CTx
5BUx
5BVx
5CMx
5BWx
5CNx
5BXx
5CPx
5BYx
5CAx
5CBx
5CCx
5CDx
5CEx
5CGx
5CHx
5CJx
5CKx
5CLx
Where “x” = assembly work week (A to Z), such that “A” = WW01-02, “B” = WW03-04, and
so forth.
27/29
Revision history
8
STM6321/6322STM6821/6822/6823/6824/6825
Revision history
Table 11.
28/29
Document revision history
Date
Revision
Changes
25-Aug-2004
1
First draft
15-Dec-2004
2
Update characteristics (Figure 15, 16, 17; Table 6, and 9)
10-Mar-2005
3
Document promoted to Datasheet status
17-Jun-2005
4
Package marking update (Table 10)
11-Apr-2006
5
Update characteristics, Lead-free text, availability (Figure 3, 4, 5, 6,
7, 8, and 9; Table 1, 6, 9, and 10)
11-Aug-2006
6
Update Description, Table 9, and 10.
25-May-2007
7
Formatting changes, updated Table 10.
03-Jun-2008
8
Updated cover page; updated reset threshold values in Table 6, 9,
and 10; addition of text to Section 6; updated Figure 27 and Table 6
and 7; minor text changes.
09-Apr-2009
9
Updated Section 1.1.1, Section 6; added tape and reel specifications
Figure 28, Table 8.
STM6321/6322STM6821/6822/6823/6824/6825
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29/29