STM6717/6718/6719/6720 STM6777/6778/6779*/6780* Dual/Triple Ultra-Low Voltage Supervisors with Push-Button Reset (with Delay Option) FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ PRIMARY SUPPLY (VCC1) MONITOR. FIXED (FACTORY-PROGRAMMED) RESET THRESHOLDS: 4.63V TO 1.58V SECONDARY SUPPLY (VCC2) MONITOR (STM6717/18/19/20/77/78). FIXED (FACTORY-PROGRAMMED) RESET THRESHOLDS: 3.08V TO 0.79V TERTIARY SUPPLY MONITOR (USING EXTERNALLY ADJUSTABLE RSTIN): 0.626V INTERNAL REFERENCE RST OUTPUTS (PUSH-PULL OR OPEN DRAIN); STATE GUARANTEED IF VCC1 OR VCC2 ≥ 0.8V RESET DELAY TIME (trec) ON POWER-UP: – 210ms (typ) MANUAL RESET INPUT (MR) OPTIONAL DELAYED MANUAL RESET INPUT (MRC) WITH EXTERNAL CAPACITOR (STM6777/78/79/80) LOW SUPPLY CURRENT - 11µA (TYP), VCC1 = VCC2 = 3.6V OPERATING TEMPERATURE: –40°C to 85°C (Industrial Grade) Figure 1. Packages SOT23-5 (WY) SOT23-6 (WB) Table 1. Device Options Monitored Voltages Reset Output (RST) VCC1 VCC2 STM6717 ✔ ✔ ✔ STM6718 ✔ ✔ ✔ STM6719 ✔ ✔ ✔ ✔ STM6720 ✔ ✔ ✔ ✔ STM6777 ✔ ✔ ✔ ✔ STM6778 ✔ ✔ ✔ ✔ STM6779* ✔ ✔ ✔ ✔ STM6780* ✔ ✔ ✔ ✔ RSTIN Manual Reset Input (MR) Delayed MR Pin (MRC) Part Number Active-Low (Push-Pull) Active-Low (Open Drain) Package ✔ WY ✔ WY ✔ ✔ WB ✔ ✔ WB WB ✔ ✔ WB WB WB * Contact local ST sales office for availability. Rev 3.0 October 2005 1/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. Logic Diagram (STM6719/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. Logic Diagram (STM6777/78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5. Logic Diagram (STM6779/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. STM6717/18 SOT23-5 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7. STM6719/20 SOT23-6 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 8. STM6777/78 SOT23-6 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9. STM6779/80 SOT23-6 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3. Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10.Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....4 .....4 .....5 .....5 .....5 .....5 .....5 .....6 .....6 .....7 .....7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 12.STM67xx Interface to Processor with Bi-directional Reset Pins . . . . . . . . . . . . . . . . . . . . 8 Figure 13.Ensuring RST Valid to VCC = 0 (Active-Low, Push-Pull Outputs) . . . . . . . . . . . . . . . . . . . 8 TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 14.Supply Current vs. Temperature (VCC1 = 5.5V; VCC2 = 3.6V). . . . . . . . . . . . . . . . . . . . . . 9 Figure 15.Supply Current vs. Temperature (VCC1 = 3.6V; VCC2 = 2.75V). . . . . . . . . . . . . . . . . . . . . 9 Figure 16.Supply Current vs. Temperature (VCC1 = 3.0V; VCC2 = 2.0V). . . . . . . . . . . . . . . . . . . . . 10 Figure 17.Supply Current vs. Temperature (VCC1 = 2.0V; VCC2 = 1.0V). . . . . . . . . . . . . . . . . . . . . 10 Figure 18.Normalized VCC Reset Time-out Period vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 19.Maximum VCC Transient Duration vs. Reset Threshold Overdrive . . . . . . . . . . . . . . . . . 11 Figure 20.Normalized VRST1 Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 21.Normalized VRST2 Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 22.Reset Input Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 23.VCC1-to-Reset Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 24.Reset Input-to-Reset Output Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 25.MR-to-Reset Output Delay vs. Temperature (VCC1 = 3.6V) . . . . . . . . . . . . . . . . . . . . . . 14 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* Figure 26.AC Testing Input/Output Waveforms. . . . . . . . . . . Figure 27.MR Timing Waveform (STM6717/18/19/20) . . . . . Figure 28.MR Timing Waveform (STM6777/78/79/80) . . . . . Table 6. DC and AC Characteristics . . . . . . . . . . . . . . . . . . Table 7. tMLMH Minimum Pulse Width . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 16 . . . . 16 . . . . 16 . . . . 17 . . . . 19 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 29.SOT23-5 – 5-lead Small Outline Transistor Package Mechanical Drawing Table 8. SOT23-5 – 5-lead Small Outline Transistor Package Mechanical Data . . . Figure 30.SOT23-6 – 6-lead Small Outline Transistor Package Mechanical Drawing Table 9. SOT23-6 – 6-lead Small Outline Transistor Package Mechanical Data . . . ...... ...... ...... ...... . . . . 21 . . . . 21 . . . . 22 . . . . 22 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* SUMMARY DESCRIPTION The STM6717/18/19/20 and STM6777/78/79/80 Supervisors are a family of low voltage/low supply current processor (Micro or DSP) Supervisors, designed to monitor two (or three) system power supply voltages. They are targeted at applications such as Set-Top Boxes (STBs), portable, batterypowered systems, networking, and communication systems. All device options have a push-button-type manual reset input (MR). The STM6777/78/79/80 also includes an option which enables the user to delay the start of the Manual Reset process from 6µs (MRC pin left open) or more with external capacitor. The delay is implemented by connecting the appropriately sized capacitor between the MRC pin and VSS (typical 4s delay with a 3.3µF capacitor, see Table 7., page 19). Two of the three supplies monitored (VCC1 and VCC2) have fixed (customer-selectable, factorytrimmed) thresholds (VRST1 and VRST2). The third voltage is monitored using an externally adjustable RSTIN threshold (0.626V internal reference). If any of the three monitored voltages drop below its factory-trimmed or adjustable thresholds, or if MR is asserted to logic low, a RST is asserted (driven low). Once asserted, RST is maintained at Low for a minimum delay period (trec) after ALL supplies rise above their respective thresholds and MR returns to High. These devices are guaranteed to be in the correct reset output logic state when VCC1 and/or VCC2 is greater than 0.8V. These devices are available in a standard 5-pin or 6-pin SOT23 packages (see Table 1., page 1). Figure 2. Logic Diagram (STM6717/18) Figure 4. Logic Diagram (STM6777/78) VCC2 VCC1 MR STM6717 STM6718 VCC2 VCC1 MRC RST MR VSS VSS AI10413 Figure 3. Logic Diagram (STM6719/20) STM6777 STM6778 RST AI10415 Figure 5. Logic Diagram (STM6779/80) VCC2 VCC1 VCC RSTIN RSTIN MR STM6719 STM6720 RST MRC STM6779 STM6780 RST MR VSS 4/25 AI10414 VSS AI10416 STM6717/6718/6719/6720/6777/6778/6779*/6780* Table 2. Signal Names MR Push-button Reset Input MRC Manual Reset Delay Input RST Active-low Reset Output VCC1 Primary Supply Voltage Input VCC2 Secondary Supply Voltage Input RSTIN VSS Adjustable Reset Comparator Input Ground Figure 6. STM6717/18 SOT23-5 Connections RST 1 VSS 2 MR 3 5 4 VCC1 VCC2 Figure 8. STM6777/78 SOT23-6 Connections RST 1 6 VCC1 VSS 2 5 MRC MR 3 4 VCC2 AI10417 Figure 7. STM6719/20 SOT23-6 Connections AI10418 Figure 9. STM6779/80 SOT23-6 Connections RST 1 6 VCC1 RST 1 6 VCC1 VSS 2 5 RSTIN VSS 2 5 RSTIN MR 3 4 VCC2 MR 3 4 MRC AI10419 AI10420 5/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* Pin Descriptions Active-Low, Push-pull Reset Output (RST) STM6718/20/78/80. The RST pin is driven low and stays low whenever VCC1 or VCC2 or RSTIN falls below its factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low for trec after ALL supply voltages being monitored rise above their reset thresholds and MR goes from low to high. (Push-pull outputs are referenced to VCC1.) Active-Low, Open Drain Reset Output (RST) STM6717/19/77/79. The RST pin is driven low and stays low whenever VCC1 or VCC2 or RSTIN falls below its factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low for trec after ALL supply voltages being monitored rise above their reset thresholds and MR goes from low to high. Connect an external pull-up resistor to VCC1. A 10kΩ pull-up resistor should be sufficient for most applications. Push-Button Reset Input (MR). When MR goes low the RST output is driven low. RST remains low as long as MR is low and for trec after MR returns to high. This active-low input has an internal 50kΩ pull-up resistor to VCC1. It can be driven from a TTL or CMOS logic line, or with open drain/collector outputs, or connected to VSS through a switch. If unused, leave this pin open or connect it to VCC1. Connect a normally open momentary switch from MR to VSS; external debounce circuitry is not required. (If MR is driven from long cables or if the device is used in noisy environments, connecting a 0.1µF capacitor from MR to VSS provides additional noise immunity. Manual Reset Delay Input (MRC) - STM6777/78/ 79/80). This pin is either left open or connected to VSS via a capacitor. By selecting the appropriate capacitor, the manual reset process, initiated by pressing the push-button Manual Reset Input, can be delayed by any value from 6µs or more (see Table 7., page 19). Primary Supply Voltage Monitoring Input (VCC1). It also is the input for the primary reset threshold monitor. Available fixed (customer-selectable, factory-programmed) reset thresholds include 4.63V to 1.58V. Secondary Supply Voltage Monitoring Input (VCC2). This function is available on the STM6717/18/19/20/77/78. Fixed (customer-selectable, factory-programmed) reset thresholds include 3.08V to 0.79V. Adjustable Reset Comparator Input (RSTIN; STM6719/20/79/80). This is a high impedance input. RST is driven low when the voltage at the RSTIN pin falls below 0.626V (internal reference voltage at this comparator). The monitored voltage reset threshold is set with an external resistor-divider network. Table 3. Pin Functions Pin Name Function STM6717 STM6718 STM6719 STM6720 STM6777 STM6778 STM6779 STM6780 1 1 1 1 RST Active-low Reset Output 3 3 3 3 MR Push-button Reset Input – – 5 4 MRC Manual Reset Delay Input 5 6 6 6 VCC1 Primary Supply Voltage Input 4 4 4 – VCC2 Secondary Supply Voltage Input – 5 – 5 2 2 2 2 6/25 RSTIN Adjustable Reset Comparator Input VSS Ground STM6717/6718/6719/6720/6777/6778/6779*/6780* Figure 10. Block Diagram VCC1 VRST1 COMPARE VRST2 COMPARE VREF/2 = 0.626 COMPARE (1) VCC2 RSTIN(2) VCC1 trec Generator RST Logic MR MRC(3) AI10421 Note: 1. VCC2 Input is available on STM6717/18/19/20/77/78. 2. RSTIN available only on STM6719/20/79/80. 3. MRC available only on STM6777/78/79/80. Figure 11. Hardware Hookup From DC/DC Converter VCC2(1) VCC1 VCC1 VCC3 = (626.5mV) R1 + R2 R2 ( ) 0.1µF STM67xx VCC2 VCC3 0.1µF R1 RSTIN(2) RST RST (To Processor Reset) R2 MR (3) MRC Push-button Switch C VSS AI10422 Note: 1. VCC2 is available only on STM6717/18/19/20/77/78. 2. RSTIN available only on STM6719/20/79/80. 3. MRC available only on STM6777/78/79/80. 7/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* OPERATION Applications Information 1. Interfacing to Processors with Bi-directional Reset Pins Most processors with bi-directional reset pins can interface directly to the open drain RST outputs (STM6717/19/77/79). Systems simultaneously requiring a push-pull RST output and a bi-directional reset interface can be in logic contention. To prevent this contention, connect a 4.7kΩ resistor between RST and the processor’s Reset I/O as shown in Figure 12. 2. Ensuring a Valid RST Output Down to VCC = 0V The STM67xx Supervisors are guaranteed to be in the correct RST output logic state when VCC1 and/or VCC2 is greater than 0.8V. In applications which require valid reset levels down to VCC = 0, a pull-down resistor to active-low outputs (push-pull only, see Figure 13.) will ensure that the reset line is valid while the reset output can no longer sink or source current. This scheme does NOT work with the open drain outputs of the STM6717/19/77/79. The resistor value used is not critical, but it must be large enough not to load the reset output when VCC is above the reset threshold. For most applications, 100kΩ is adequate. Figure 12. STM67xx Interface to Processor with Bi-directional Reset Pins VCC2 VCC1 STM67xx Processor To other system components VCC1 VCC2 RESET RST 4.7kΩ VSS VSS AI10425 Figure 13. Ensuring RST Valid to VCC = 0 (Active-Low, Push-Pull Outputs) STM67xx VCC1 VCC1 RST VSS R1 AI10426 8/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* TYPICAL OPERATING CHARACTERISTICS Note: Typical values are at TA = 25°C unless otherwise noted. Figure 14. Supply Current vs. Temperature (VCC1 = 5.5V; VCC2 = 3.6V) 18 Supply Current (µA) 16 14 12 10 ITOTAL ICC1 8 6 4 ICC2 2 0 –40 –20 0 20 40 60 80 Temperature (°C) AI11843 Figure 15. Supply Current vs. Temperature (VCC1 = 3.6V; VCC2 = 2.75V) 18 16 Supply Current (µA) 14 12 10 ITOTAL 8 ICC1 6 4 ICC2 2 0 –40 –20 0 20 40 Temperature (°C) 60 80 AI11844 9/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* Figure 16. Supply Current vs. Temperature (VCC1 = 3.0V; VCC2 = 2.0V) 18 Supply Current (µA) 16 14 12 10 8 ITOTAL 6 ICC1 4 2 ICC2 0 –40 –20 0 20 40 60 80 Temperature (°C) AI11845 Figure 17. Supply Current vs. Temperature (VCC1 = 2.0V; VCC2 = 1.0V) 18 Supply Current (µA) 16 14 12 10 8 ITOTAL 6 ICC1 4 2 0 –40 ICC2 –20 0 20 Temperature (°C) 10/25 40 60 80 AI11846 STM6717/6718/6719/6720/6777/6778/6779*/6780* Figure 18. Normalized VCC Reset Time-out Period vs. Temperature 1.07 Reset Period 1.05 1.03 1.01 0.99 0.97 –40 –20 0 20 40 60 Temperature (°C) 80 AI11847 Maximum VCC Transient Duration (µs) Figure 19. Maximum VCC Transient Duration vs. Reset Threshold Overdrive 1000 100 10 1 1 10 100 Reset Threshold Overdrive (mV) 1000 AI11848 11/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* Figure 20. Normalized VRST1 Threshold vs. Temperature VRST1 Reset Threshold 1.004 1.002 1.000 0.998 0.996 –40 –20 0 20 40 60 Temperature (°C) 80 AI11849 Figure 21. Normalized VRST2 Threshold vs. Temperature VRST2 Reset Threshold 1.004 1.002 1.000 0.998 0.996 –40 –20 0 20 40 60 80 Temperature (°C) AI11850 12/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* Figure 22. Reset Input Threshold vs. Temperature Reset Input Threshold (mV) 630 629 628 627 626 625 624 –40 –20 0 20 40 60 Temperature (°C) 80 AI11851 Figure 23. VCC1-to-Reset Delay vs. Temperature VCC1-to-Reset Delay (µs) 48 44 40 36 32 28 –40 –20 0 20 Temperature (°C) 40 60 80 AI11852 13/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* Figure 24. Reset Input-to-Reset Output Delay vs. Temperature RSTIN-to-Reset Output Delay (µs) 29.0 28.5 28.0 27.5 27.0 26.5 26.0 25.5 25.0 –40 –20 0 20 40 60 80 Temperature (°C) AI11853 Figure 25. MR-to-Reset Output Delay vs. Temperature (VCC1 = 3.6V) MR-to-Reset Output Delay (ns) 500 480 460 440 420 400 –40 –20 0 20 40 60 80 Temperature (°C) AI11854 14/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute Maximum Ratings Symbol TSTG TSLD(1) VIO VCC1, VCC2 Parameter Value Unit –55 to 150 °C 260 °C –0.3 to VCC1 + 0.3 V –0.3 to VCC2 + 0.3 V –0.3 to 7.0 V 20 mA SOT23-5 654 mW SOT23-6 675 mW Storage Temperature (VCC Off) Lead Solder Temperature for 10 seconds Input or Output Voltage Supply Voltage IIO Input or Output Current (all pins) PD Power Dissipation Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 to 150 seconds). 15/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 5., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC Measurement Conditions Parameter STM67xx Unit VCC Supply Voltage 0.8 to 5.5 V Ambient Operating Temperature (TA) –40 to 85 °C ≤5 ns Input Pulse Voltages 0.2 to 0.8VCC V Input and Output Timing Ref. Voltages 0.3 to 0.7VCC V Input Rise and Fall Times Figure 26. AC Testing Input/Output Waveforms 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI02568 Figure 27. MR Timing Waveform (STM6717/18/19/20) tMLMH MR tMLRL RST trec AI10423a Figure 28. MR Timing Waveform (STM6777/78/79/80) tMLMH (1) MR tMLRL RST trec AI10424c Note: 1. By connecting a certain capacitor between the MRC pin and VSS, the RST can be delayed from 6µs or more (tMLMH, see Table 7., page 19). 16/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* Table 6. DC and AC Characteristics Sym Alternative Description VCC Operating Voltage ICC1 VCC1 Supply Current VCC2 Supply Current ICC2 ILI(2) Input Leakage Current Open Drain RST Output Leakage Current ILO Output Low Voltage (RST; Push-pull or Open Drain) VOL Output High Voltage (RST; Push-pull only) VOH Push-pull RST Rise Time (STM6718/20/78/80) tR(3) Test Condition(1) Min Typ 0.8 Max Unit 5.5 V VCC1 < 5.5V, all I/O pins open 12 35 µA VCC1 < 3.6V, all I/O pins open 8 23 µA VCC2 < 3.6V, all I/O pins open 3 9 µA VCC2 < 2.75V, all I/O pins open 2.5 7 µA +1 µA VCC1 > VRST1, VCC2 > VRST2; RST not asserted 0.5 µA VCC1 or VCC2 ≥ 0.8V, ISINK = 1µA, RST asserted 0.3 V VCC1 or VCC2 ≥ 1.0V, ISINK = 50µA, RST asserted 0.3 V VCC1 or VCC2 ≥ 1.2V, ISINK = 100µA, RST asserted 0.3 V VCC1 or VCC2 ≥ 2.7V, ISINK = 1.2mA, RST asserted 0.3 V VCC1 or VCC2 ≥ 4.5V, ISINK = 3.2mA, RST asserted 0.4 V 0V = VIN = VCC –1 VCC1 ≥ 1.8V, ISOURCE = 200µA, RST not asserted 0.8VCC1 V VCC1 ≥ 2.7V, ISOURCE = 500µA, RST not asserted 0.8VCC1 V VCC1 ≥ 4.5V, ISOURCE = 800µA, RST not asserted 0.8VCC1 V Rise time measured from 10% to 90% of VCC; CL = 5pF, VCC = 3.3V 5 25 ns Reset Thresholds VRST1(4) VTH1 VCC1 Reset Threshold L (falling) 4.500 4.625 4.750 V M (falling) 4.250 4.375 4.500 V T (falling) 3.000 3.075 3.150 V S (falling) 2.850 2.925 3.000 V R (falling) 2.550 2.625 2.700 V Z (falling) 2.250 2.313 2.375 V Y (falling) 2.125 2.188 2.250 V W (falling) 1.620 1.665 1.710 V V (falling) 1.530 1.575 1.620 V 17/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* Sym VRST2(4) Alternative VTH2 VCC to RST Delay tRD tRP Test Condition(1) Min Typ Max Unit T (falling) 3.000 3.075 3.150 V S (falling) 2.850 2.925 3.000 V R (falling) 2.550 2.625 2.700 V Z (falling) 2.250 2.313 2.375 V Y (falling) 2.125 2.188 2.250 V W (falling) 1.620 1.665 1.710 V V (falling) 1.530 1.575 1.620 V I (falling) 1.350 1.388 1.425 V H (falling) 1.275 1.313 1.350 V G (falling) 1.080 1.110 1.140 V F (falling) 1.020 1.050 1.080 V K (falling) 0.895 0.925 0.955 V J (falling) 0.845 0.875 0.905 V E (falling) 0.810 0.833 0.855 V D (falling) 0.765 0.788 0.810 V VCC2 Reset Threshold Reset Threshold Hysteresis VHYST trec Description Referenced to VRST typical 0.5 % VCC1 = (VRST1 + 100mV) to (VRST – 100mV) 20 µs VCC2 = (VRST2 + 75mV) to (VRST2 – 75mV) 20 µs RST Time-out Period 140 210 280 ms 626.5 642 mV +25 nA Adjustable Reset Comparator Input (STM6719/20/79/80) VRSTIN RSTIN Input Threshold 611 IRSTIN RSTIN Input Current –25 RSTIN Hysteresis tRSTIND 18/25 RSTIN to RST Output Delay VRSTIN to (VRSTIN – 30mV) 3 mV 22 µs STM6717/6718/6719/6720/6777/6778/6779*/6780* Alternative Sym Description Test Condition(1) Min Typ Max Unit 0.3VCC1 V Manual (Push-button) Reset Input VIL MR Input Voltage VIH MR Minimum Pulse Width (STM6717/18/19/20) tMR tMLMH tMLRL tMRD MR Minimum Pulse Width (STM6777/78/79/80) V 1 µs MRC connected via capacitor to VSS(5) 6 µs MR to RST Output Delay 200 ns MR Glitch Immunity (STM6717/18/19/20) 100 ns MR Pull-up Resistance Note: 1. 2. 3. 4. 5. 0.7VCC1 25 50 80 kΩ Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC1 = 0.8 to 5.5V and VCC2 = 0.8 to 3.6V (except where noted). Input leakage for the MRC pin is not tested. Guaranteed by design. The leakage current measured on the RST pin is tested with the reset de-asserted (output high impedance). Selecting the appropriate external capacitor (preferably less than 100pF) allows systems designers to vary the minimum delay from 6µs (MRC pin left open) or more (see Table 7.). Table 7. tMLMH Minimum Pulse Width Capacitor Value(1) VCC1 100pF 0.1µF 2.2µF 3.3µF 4.7µF 6.8µF 1.6V 120µs 120ms 2.6s 4.0s 5.6s 8.2s 2.0V 122µs 122ms 2.7s 4.0s 5.8s 8.3s 3.0V 125µs 125ms 2.7s 4.1s 5.9s 8.5s 4.0V 128µs 129ms 2.8s 4.2s 6.0s 8.7s 5.0V 130µs 130ms 2.8s 4.3s 6.1s 8.8s Note: 1. At 25°C (typical) 19/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* PACKAGE MECHANICAL In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 20/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* Figure 29. SOT23-5 – 5-lead Small Outline Transistor Package Mechanical Drawing E A1 1 e e1 D 5x b 5x 0.20 M CAB A2 C 0.10 A C A Datum A 0.20 θ C L B E1 SOT23-5b Note: Drawing is not to scale. Table 8. SOT23-5 – 5-lead Small Outline Transistor Package Mechanical Data mm inches Symb Typ Min Max Typ Min Max A – – 1.45 – – 0.057 A1 – – 0.15 – – 0.006 A2 1.15 0.90 1.30 0.045 0.035 0.051 b – 0.30 0.50 – 0.012 0.020 C – 0.08 0.22 – 0.003 0.009 D 2.90 – – 0.114 – – E 2.80 – – 0.110 – – E1 1.60 – – 0.063 – – e 0.95 – – 0.037 – – e1 1.90 – – 0.075 – – L 0.45 0.30 0.60 0.018 0.012 0.024 Θ 4° 0° 8° 4° 0° 8° N 5 5 Note: Dimensions per JEDEC SOT/SOP Product Outline MO-178C, variation AA 21/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* Figure 30. SOT23-6 – 6-lead Small Outline Transistor Package Mechanical Drawing E A1 1 e e1 D 6x b 0.10 6x M CAB A2 C 0.10 A C A Datum A 0.20 θ C L B E1 SOT23-6 Note: Drawing is not to scale. Table 9. SOT23-6 – 6-lead Small Outline Transistor Package Mechanical Data mm inches Symb Typ Min Max Typ Min Max A – – 1.45 – – 0.057 A1 – – 0.15 – – 0.006 A2 1.15 0.90 1.30 0.045 0.035 0.051 b – 0.30 0.50 – 0.012 0.020 C – 0.08 0.22 – 0.003 0.009 D 2.90 – – 0.114 – – E 2.80 – – 0.110 – – E1 1.60 – – 0.063 – – e 0.95 – – 0.037 – – e1 1.90 – – 0.075 – – L 0.45 0.30 0.60 0.018 0.012 0.024 Θ 4° 0° 8° 4° 0° 8° N 6 Note: Dimensions per JEDEC SOT/SOP Product Outline MO-178C, variation AA 22/25 6 STM6717/6718/6719/6720/6777/6778/6779*/6780* PART NUMBERING Table 10. Ordering Information Scheme Example: STM67xx LT WY 6 E Device Type STM67xx Reset Thresholds (VRST1 and VRST2) for VCC1 and VCC2 STM6717/18/19/20/77/78 (VRST1 and VRST2) VRST1 VRST2 Suffix LT 4.625 3.075 MS 4.375 2.925 MR 4.375 2.625 (1) 3.075 2.313 TZ (1) 3.075 TW 1.665 TI 3.075 1.388 (1) 3.075 TG 1.110 TK 3.075 0.925 TE 3.075 0.833 2.925 SY(1) 2.188 2.925 SV(1) 1.575 SH 2.925 1.313 2.925 SF(1) 1.050 SJ 2.925 0.875 SD 2.925 0.788 YV 2.188 1.575 YH 2.188 1.313 YF 2.188 1.050 YJ 2.188 0.875 YD 2.188 0.788 VH 1.575 1.313 VF 1.575 1.050 VJ 1.575 0.875 VD 1.575 0.788 STM6779/80 (VRST1 only)(2) L– 4.625 – T– 3.075 – S– 2.925 – Y– 2.188 – V– 1.575 – R– 2.625 – Z– 2.313 – Package WY = SOT23-5 WB = SOT23-6 Temperature Range 6 = –40 to 85°C Shipping Method E = ECOPACK Package, Tubes F = ECOPACK Package, Tape & Reel Note: 1. These are standard versions and are typically held in stock. A non-standard version may require a higher minimum volumes, and/ or longer delivery times. For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. 2. Contact local ST sales office for availability. 23/25 STM6717/6718/6719/6720/6777/6778/6779*/6780* REVISION HISTORY Table 11. Document Revision History Date Version 18-October-04 1.0 First Draft 25-Oct-04 1.1 Descriptive text, sales types (Table 10) 14-Jan-05 1.2 Update characteristics, pin functions (Table 3) 09-Feb-05 1.3 Update characteristics (Figure 10; Table 3) 08-Apr-05 1.4 Update characteristics and mechanical dimensions; add table (Figure 10, 11, 28, 29, 30; Table 4, 6, 10, 8, 9) 28-Jul-05 1.5 Updated characteristics, reset delay (Figure 11, 28; Table 4, 6, 7, 10) 13-Sep-05 2.0 Add operating characteristics; update timings, document status, Lead-free text (Figure 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 28; Table 10) 07-Oct-05 3.0 Marked STM6779/6780 as availability request parts (Table 1, 10) 24/25 Revision Details STM6717/6718/6719/6720/6777/6778/6779*/6780* Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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