UNISONIC TECHNOLOGIES CO., LTD PA3212 CMOS IC 2.6W STEREO AUDIO AMPLIFIER WITH FOUR SELECTABLE GAIN SETTINGS AND MUX CONTROL DESCRIPTION As operating on a single 5V supply, the UTC PA3212 is capable of delivering 2.6W of output power per channel into 3Ω loads. In Bridge-Tied Load (BTL) mode the UTC PA3212 has less than 1% THD+N, and it also has less than 0.65% THD+N across its specified frequency range when driving 1 W into 8-Ω speakers. Way of two terminals (GAIN0 and GAIN1) can configure and control the amplifier gain. It also provides BTL gain settings of 2, 6, 12 and 24 V/V. Other features included that the SHDN mode is provided to disable UTC PA3212 for the low current consumption applications and the current consumption can be reduced to typically 150µA. Lead-free: PA3212L Halogen-free: PA3212G FEATURES * Output power at 0.65% THD+N, VDD=5V(TYP) –2.6W/CH (typical) into a 3Ω load –1.0W/CH (typical) into a 8Ω load * Bridge-tied load (BTL) supported * Gain control internally * Differential Input fully * Depop circuitry Inside * Shutdown protection * Stereo input ORDERING INFORMATION Normal PA3212-N24-R PA3212-N24-T Ordering Number Lead Free PA3212L-N24-R PA3212L-N24-T www.unisonic.com.tw Copyright © 2009 Unisonic Technologies Co., Ltd Halogen Free PA3212G-N24-R PA3212G-N24-T Package Packing HTSSOP-24 HTSSOP-24 Tape Reel Tube 1 of 9 QW-R502-310.A PA3212 CMOS IC PIN CONFIGURATION PIN DESCRIPTION PIN NO. 1,12,13,24 11 2 3 5 6 7,18 PIN NAME GND BYPASS GAIN0 GAIN1 LLINEIN LHPIN PVDD I/O 8 RIN I 10 LIN I 14 PC-BEEP I 17 HP/ LINE I 15 19 20 23 SE/ BTL VDD RHPIN RLINEIN I I I I 22 SHUTDOWN I In shutdown mode when held low, expect PC-BEEP remains active. 4 9 16 21 LOUT+ LOUTROUTROUT+ O O O O In BTL mode: left channel + output; In SE mode: left channel + output In BTL mode: left channel - output; In SE mode: high impedance In BTL mode: right channel + output; In SE mode: right channel + output In BTL mode: right channel - output; In SE mode: high impedance I I I I I DESCRIPTION Ground. Connected to voltage divider For gain control: Bit 0 For gain control: Bit 1 Line input for Left channel, available when pin15 is held low. Headphone input Left channel, available when pin15 is held high. Power supply voltage. Differential input for right channel. And for single-ended inputs is also AC ground. Differential input for Left channel. And for single-ended inputs is also AC ground. PC-BEEP mode input. When at least eight continuous >1-VPP square waves is input to this pin, PC-BEEP is enabled. Input of MUX control. Being high to select the inputs of Pin6, 20, and low to select inputs of PIN 5, 23. Low for BTL mode, high for SE mode. Analog VDD supply voltage Right channel headphone input, selected when pin17 is held high. Headphone input right channel, available when pin17 is held low. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 9 QW-R502-310.A PA3212 CMOS IC BLOCK DIAGRAM RHPIN RLINEIN R MUX Volume Control ROUT+ GAIN0 GAIN1 RIN Volume Control ROUT– Depop Circuitry Power Management LHPIN LLINEIN L MUX Volume Control PVDD VDD BYPASS SHUTDOWN GND LOUT+ LIN PC-BEEP SE/BEL HP/LINE PC Beep Volume Control MUX Control UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw LOUT– 3 of 9 QW-R502-310.A PA3212 CMOS IC ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL RATINGS Supply Voltage VDD 6 Input Voltage VIN -0.3 ~ VDD ~ +0.3 Junction Temperature TJ +150 Operating Temperature TOPR -40 ~ +85 Storage Temperature TSTG -65 ~ +85 Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. UNIT V V °С °С °С ELECTRICAL CHARACTERISTICS (Ta= 25°С, unless otherwise specified.) PARAMETER SYMBOL DC ELECTRICAL CHARACTERISTICS Supply Voltage VDD High-Level Input voltage Low-Level Input voltage DC Differential Output Voltage Supply Current in Mute Mode VIH VIL VOUT(DIFF) IDD TEST CONDITIONS SHUTDOWN SE/BTL, HP/LINE, GAIN0, GAIN1 MIN TYP MAX UNIT 4.5 5 5.5 V 2 V 0.8×VDD SHUTDOWN GAIN0, GAIN1 SE/ BTL , HP/ LINE VIN=0V,Gain=2V/V BTL Mode SE Mode VDD=5V VDD=5.5V, VIN=VDD VDD=5.5V, VIN=0V Supply Current, Shutdown Mode IDD(SD) High-Level Input Current |IIH| Low-Level Input Current |IIL| Operating Free-Air Temperature Ta -40 AC ELECTRICAL CHARACTERISTICS (VDD = 5.0V, RL = 8Ω, unless otherwise noted ) THD=1%, BTL, RL=3Ω, G=2V/V Output Power POUT THD=10%, BTL, RL=3Ω, G=2V/V Total Harmonic Distortion Plus Noise THD+N POUT=1W, BTL, RL= 8Ω, G=2V/V THD= 5% Max Output Power Bandwidth BOM Power Supply Ripple Rejection PSRR f=1kHz, BTL, G=2V/V, CBYP=0.47µF CBYP=0.47µF,BTL, G=2V/V Output Noise Voltage eN CBYP=0.47µF, SE, G=2V/V Signal-to-Noise Ratio SNR Note: Output power is measured at the output terminals of the IC at 1kHz. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw V 6 3 150 2.05 2.6 0.65 15 72 20 18 105 0.8 V 0.4×VDD V 0.6×VDD V mV mA mA µA nA nA °С 25 8 4 300 900 900 85 W % kHz dB µVRMS µVRMS dB 4 of 9 QW-R502-310.A PA3212 CMOS IC TYPICAL APPLICATION CIRCUITS UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 5 of 9 QW-R502-310.A PA3212 CMOS IC TYPICAL APPLICATION CIRCUITS(Cont.) UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 9 QW-R502-310.A PA3212 CMOS IC APPLICATION INFORMATION Shutdown Mode Operating INPUT HP/ LINE X L L H H X: Don’t care L: Low H: High SE/ BTL X L H L H AMPLIFIER SHUTDOWN L H H H H INPUT X LINE LINE HEADPHONE HEADPHONE OUTPUT MUTE BTL SE BTL SE CI (Input Capacitor) The value of CI is important to consider as it directly affects the bass performance of the application circuit. When CI is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation, it’s value can be calculate by this equation: CI=1/(2πRIFC) RI: Input Impedance FC: High-pass Filter’s Frequency The low leakage tantalum or ceramic capacitors are suggested to be used as the input coupling capacitors, because of the small leakage current of the input capacitors will cause the dc offset voltage at the input to the amplifier that reduces the operation headroom, especially at the high gain applications. It is important to let the positive side connecting to the higher dc level of the application when using the polarized capacitors. Gain setting (VS Gain0, Gain1 and RI) Gain setting is determined by GAIN0 and GAIN1. The gains listed in the next table are realized by changing the taps on the input resistors inside the amplifier which will cause the internal input impedance(R I) to be dependent on the gain setting as we can see listed in the next table. GAIN0 0 0 1 1 X GAIN1 0 1 0 1 X R I(kΩ) 91 45.5 26 14 UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw AV(V/V) 2 6 12 24 1 SE/ BTL 0 0 0 0 1 7 of 9 QW-R502-310.A Right Channel Output Voltage(V) Right Channel Output Voltage(V) Right Channel Output Voltage(V) Left Channel Output Voltage(V) Left Channel Output Voltage(V) Negative Output Voltage(mV) Right Channel Output Voltage(V) Positive Output Voltage(mV) Left Channel Output Voltage(V) PC-Beep Input Voltage(mV) UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw Phase(°) Gain(dB) Left Channel Output Voltage(V) PA3212 CMOS IC TYPICAL CHARACTERISTICS QW-R502-310.A 8 of 9 PA3212 CMOS IC UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 9 of 9 QW-R502-310.A