TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER www.ti.com FEATURES • • • • • • • • • Fully Integrated Signal Conditioning Transceiver 1.0–1.3 Gbps Operation Low Power CMOS Design (<300 mW) High Differential Output Voltage Swing (1600 mVp-p typical) 400 mVp-p Differential Input Sensitivity High Input Jitter Tolerance 0.606 UI Single 1.8 V Power Supply 2.5 V Tolerant Control Inputs Differential VML Transmit Outputs With No External Components Necessary SLLS661 – JUNE 2005 • • • • No External Filter Components Required for PLLs Supports Loop-Back Modes Temperature Rating 0°C to 70°C Small Footprint 4 mm × 4 mm 24-Lead QFN Package APPLICATIONS • • Resynchronization in Both Directions for 1.25 Gbps Links Repeater for 1.0625 Gbps Applications DESCRIPTION TLK1002A is a single-chip dual signal conditioning transceiver. This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip clock generation phase-locked loop (PLL) generates the required half-rate clock from an externally applied reference clock. This reference clock equals approximately one tenth of the data rate. It may be off frequency from both received data streams by up to ±200 ppm. Both data paths are implemented identical. The implemented input buffers provide an input sensitivity of 400 mVp-p differential. The data paths tolerate up to 0.606 UI total input jitter. Signal retiming is performed by means of phase-locked loop (PLL) circuits. The retimed output signals are fed to VML output buffers, which provide output amplitudes of typical 1600mVp-p differential across the external 2x50 Ω load. TLK1002A only requires a single 1.8 V supply voltage. Robust design avoids the necessity of special off-chip supply filtering. Advanced low power CMOS design leads to low power consumption. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER www.ti.com SLLS661 – JUNE 2005 BLOCK DIAGRAM A simplified block diagram of the TLK1002A circuit is shown in Figure 1. The main circuit parts are described in detail below. RXA+ RXA− input buffer stage + 2 DIN signal conditioning PLL − ICLK DOUT VML output buffer MUX 2 I1 Q Q 2 Q I2 QCLK TXB+ TXB− SEL amplifier stage 2 RCLK RCLK ICLK low−noise half−rate clock synthesizer PLL TXA+ TXA− VML output buffer Q Q QCLK Q I1 I2 2 ICLK MUX 2 2 2 DOUT QCLK signal conditioning PLL DIN 2 SEL input buffer stage + RXB+ RXB− reference voltage and bias current generation ENA LBA VDD GND VDD GND LBB ENB Figure 1. Simplified Block Diagram of the TLK1002A Transceiver DATA PATHS The serial input data streams are connected to the input ports RXA+/RXA– or RXB+/RXB– respectively. The input stages provide on-chip differential 100-Ω termination. The outputs of the input buffer stages are connected to the signal conditioning PLL circuits. The PLL output signals are fed to multiplexer (MUX) stages, which are used to redirect the data signals if loop back mode is selected. The multiplexer stages are connected to the output ports TXB+/TXB– or TXA+/TXA– , respectively, by means of VML output buffer stages. To enable the output buffer stages, ENA and ENB, which are internally pulled up, must be at high level (VDD). The loop back modes are enabled by means of the control-inputs LBA and LBB, which are implemented as active low inputs with integrated pull-up resistors. If LBA is set to low level, the input data applied to the input port RXA+/RXA– is retimed and fed to both output ports TXB+/TXB– and TXA+/TXA–. If LBB is pulled low, the retimed input data signal applied to RXB+/RXB– is available at TXA+/TXA– and TXB+/TXB–. If a logic low signal is applied to both loop back control inputs the retimed signal connected to RXA+/RXA– appears at TXA+/TXA–, while the retimed signal applied to RXB+/RXB– is fed to TXB+/TXB–. 2 TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER www.ti.com SLLS661 – JUNE 2005 DATA PATHS (continued) LOW-NOISE HALF-RATE CLOCK GENERATION PLL In order to achieve the low power requirements, an on-chip half-rate clock synthesizer PLL is implemented. It generates the internally used inphase and quadrature clock signals with 5 times the reference clock frequency. The required reference clock frequency equals approximately one tenth of the data rate. It may be off frequency from both transmit and receive data streams by up to ±200 ppm. A valid reference clock must be connected to the RCLK pin to ensure proper operation. In case of a clock absence of up to 4 cycles during clock switch over the CDR will independently re-acquire lock (i.e., without the need of any reset signal), however during re-locking erroneous bits will be transmitted for a limited period of time. The reference clock may contain jitter, in the order of about 80 psp-p. However, the jitter components below 10 MHz, which is the bandwidth of the clock generation PLL, must not exceed 40 psp-p. Increased reference clock jitter leads to increased output jitter as well as to reduced jitter tolerance. CONTROL INPUTS TLK1002A provides a total of four control inputs, which activate the VML output buffer stages and enable the loop-back modes. These control inputs may be driven from circuits using a different supply voltage. Thus, 2.5 V tolerance is mandatory at these pins. All control inputs provide on-chip pull-up resistors to VDD. REFERENCE VOLTAGE AND BIAS CURRENT GENERATION The TLK1002A transceiver is supplied by a 1.8 V ±5% supply voltage connected to VDD. The voltage is referred to ground (GND). From this voltage all required reference voltages and bias currents are derived by means of the reference voltage and bias current generation block. PACKAGE For the TLK1002A a small footprint 4 mm × 4 mm 24-lead QFN package is used, with a lead pitch of 0.5 mm. The pin out is shown below. The thermal resistance of the package is about 47°C/W. At a total power consumption of 0.3 W assuming an ambient temperature of 70°C, the maximum junction temperature is below 85°C. PIN OUT GND VDD LBA LBB VDD GND RGE PACKAGE (TOP VIEW) 24 2322 21 20 19 1 2 3 4 5 6 18 17 TLK1002A 16 15 14 13 7 8 9 10 11 12 RXB− RXB+ GND GND TXB+ TXB− GND RCLK ENA ENB VDD GND RXA− RXA+ GND GND TXA+ TXA− 3 TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER www.ti.com SLLS661 – JUNE 2005 TERMINAL FUNCTIONS TERMINAL NO. TYPE NAME DESCRIPTION 1 RXA– In Inverted data input A. On board AC coupled. On-chip 100-Ω differential terminated to RXA+. 2 RXA+ In Non-inverted data input A. On board AC coupled. On-chip 100-Ω differential terminated to RXA–. 3, 4, 7, 12, 15, 16,19, 24, EP GND Supply Circuit ground. The exposed die pad (EP) must be grounded. 5 TXA+ VML-out Retimed non-inverted data output A. On board AC coupled. 6 TXA– VML-out Retimed inverted data output A. On board AC coupled. 8 RCLK CMOS-in Reference clock input. Self biased for AC coupling. This input is 2.5 V tolerant. 9 ENA CMOS-in Enable A, on-chip pulled up to VDD. When set to high level, the VML output buffer driving the TXA+/TXA– port is enabled. This input is 2.5 V tolerant. 10 ENB CMOS-in Enable B, on-chip pulled up to VDD. When set to high level, the VML output buffer driving the TXB+/TXB– port is enabled. This input is 2.5 V tolerant 11, 20, 23 VDD Supply 1.8 V ±5% supply voltage 13 TXB– VML-out Retimed inverted data output B. On board AC coupled. 14 TXB+ VML-out Retimed non-inverted data output B. On board AC coupled. 17 RXB+ In Non-inverted data input B. On board AC coupled. On-chip 100-Ω differential terminated to RXB–. 18 RXB– In Inverted data input B. On board AC coupled. On-chip 100-Ω differential terminated to RXB+. 21 LBB CMOS-in 22 LBA CMOS-in Loop back B, on-chip pulled up to VDD. When pulled to low level, loop back mode B is enabled The input data applied to the input port RXB+/RXB– is retimed and fed to both output ports TXA+/TXA– and TXB+/TXB–. This input is 2.5 V tolerant. Loop back A, on-chip pulled up to VDD. When pulled to low level, loop back mode A is enabled 4 The input data applied to the input port RXA+/RXA– is retimed and fed to both output ports TXB+/TXB– and TXA+/TXA–. This input is 2.5 V tolerant. www.ti.com TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER SLLS661 – JUNE 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE VDD Supply voltage (2) –0.3 V to 2.5 V VCMOS Voltage range at CMOS input terminals (ENA, ENB, LBA, LBB, RCLK) (2) –0.3 V to 3.0 V Electrical discharge 2k V (HBM) TA Characterized free-air temperature range (no airflow) 0°C to 70°C TSTG Storage temperature range (1) (2) –65°C to 85°C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VDD Supply voltage TA Ambient temperature (no airflow, no heatsink) MIN NOM MAX 1.7 1.8 1.9 V 70 °C 0 UNIT 5 TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER www.ti.com SLLS661 – JUNE 2005 DC ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VDD Supply voltage 1.7 IVCC2 Current from 1.8 V supply ENA = high, ENB = high, VDD = VDD,max PRBS 1.25 Gbps data on both inputs VIL,CMOS Low level CMOS input voltage VDD= 1.8 V VIH,CMOS High level CMOS input voltage VDD = 1.8 V IL,CMOS Low level CMOS input current IH,CMOS High level CMOS input current RPU Integrated pull-up resistor to VDD TYP MAX 1.8 UNIT 1.9 V 158 mA –0.2 0.6 V VDD–0.6 2.7 V VDD = VDD,max, VIL = 0.0 V –120 µA VDD = VDD,min, VIH = 2.7 V 165 20 µA kΩ AC ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DATA PATHS Ω ZD,IN Differential input impedance TJIN Total input jitter BER ≤ 10–12, 1.25 Gbps data 0.606 UI DJIN Deterministic input jitter BER ≤ 10–12, 1.25 Gbps data 0.373 UIpp VCM,IN Common-mode input voltage vS,IN Single-ended input voltage swing 1200 mVp-p vD,IN Differential input voltage swing 2400 mVp-p 0.303 UI X1IN Y1IN Input eye mask 100 1200 BER ≤ 10–12, 1.25 Gbps data, See Figure 2 200 800 400 1600 mV 200 mV Y2IN 1200 mV tR,OUT, tF,OUT Output signal rise/fall time 20% to 80% 150 260 ps TJOUT Total output jitter 1.25 Gbps input from 3.3G pattern generator at 0 ppm 0.20 0.28 UI DJOUT Deterministic output jitter 1.25 Gbps input from 3.3G pattern generator at 0 ppm 0.1 UIpp VCM,OUT Common-mode output voltage 800 1000 1200 mV vS,OUT Single-ended output voltage swing 440 800 1000 mVp-p vD,OUT Differential output voltage 880 1600 2000 mVp-p 0.12 UI 0.32 UI X1OUT X2OUT Y1OUT Output eye mask 1.25 Gbps input from 3.3G pattern generator at 0 ppm See Figure 3 440 mV Y2OUT tD RX to TX latency tINI Lock acquisition from link down tLCK (1) (2) 6 Lock recovery on link discontinuity See (1) See (2) and (2) 1000 mV 25 ns 4 µs 1.6 µs Assuming maximum initial CDR phase offset and maximum frequency difference between reference clock and input data. The output data may contain bit errors during lock-in time, dependent on the input-data sequence and the input-data jitter. However it is assured, that the output-data does not contain bits with widths deviating significantly from the nominal bit width. TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER www.ti.com SLLS661 – JUNE 2005 AC ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE CLOCK AC SPECIFICATIONS VIL,RCLK Reference clock low level voltage DC coupled –0.3 0.3 VIH,RCLK Reference clock high level voltage DC coupled 1.5 2.1 V vRCLK Reference clock swing AC coupled 1.2 2.4 Vp-p VIH,RCLK Reference clock input threshold (self biasing) AC coupled 0.9 Clock duty cycle tR,RCLK, tF,RCLK Rise / fall time f0,RCLK Reference clock frequency (3) TJRCLK200 TJRCLK ∆fRCLK (3) (4) 20% to 80% V V 40% 60% 300 1500 ps Baud/10 Up to 10 MHz Reference clock total jitter (4) 40 80 Frequency difference between reference clock and incoming data signal Reference clock and incoming data are off the nominal data rate but in opposite direction psp-p psp-p –200 200 ppm Reference clock is not locked to the data frequency and may deviate by ∆ fRCLK. The reference clock may contain jitter, in the order of about 80 psp-p. However, the jitter components below 10 MHz, which is the bandwidth of the clock generation PLL, must not exceed 40 psp-p. Increased reference clock jitter leads to increased output jitter as well as to reduced jitter tolerance. Y2 Y2 Y1 Y1 0 −Y1 0 −Y1 −Y2 −Y2 0 X1 1−X1 1 Figure 2. Input Eye Mask 0 X1 X2 1−X2 1−X1 1 Figure 3. Output Eye Mask OPERATIONAL MODES NORMAL OPERATION MODE In normal operation, the data signal at the RXA+/RXA– pins is applied to an input buffer stage, which drives a signal conditioning PLL. The retimed output signal is connected to the output pins TXB+/TXB– by means of a multiplexer stage and a VML output buffer. On the other side, the input signal applied to the RXB+/RXB– pins is connected to a signal conditioning PLL by means of an input buffer stage. The retimed output signal of the PLL is connected to the output pins TXA+/TXA– using a multiplexer stage as well as a VML output driver. 7 TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER www.ti.com SLLS661 – JUNE 2005 OPERATIONAL MODES (continued) RXA+ RXA− input buffer stage + 2 DIN signal conditioning PLL − ICLK DOUT VML output buffer MUX 2 QCLK I1 Q 2 Q I2 Q TXB+ TXB− SEL amplifier stage 2 RCLK TXA+ RCLK ICLK low−noise half−rate clock synthesizer PLL QCLK VML output buffer 2 ICLK MUX Q 2 Q Q TXA− 2 I1 I2 2 QCLK signal conditioning PLL DOUT 2 DIN input buffer stage + RXB+ RXB− SEL reference voltage and bias current generation VDD ENA LBA VDD GND GND LBB ENB Figure 4. Data Path in Normal Operation Mode INTERNAL LOOP-BACK MODE A In internal loop-back mode A operation, which is activated by pulling the LBA pin to logic low level, the input data signal at the RXA+/RXA– pins is applied to the input buffer driving a signal conditioning PLL. The retimed output signal is connected to the output pins TXB+/TXB– by means of a multiplexer stage and a VML output buffer. Furthermore, by means of a second multiplexer the same signal is fed to the second VML output buffer, which drives the TXA+/TXA– output. The signal applied to the RXB+/RXB– input is not fed to any output in this mode. input buffer stage RXA+ + RXA− − 2 DIN signal conditioning PLL ICLK DOUT VML output buffer MUX 2 QCLK I1 Q 2 Q I2 Q TXB+ TXB− SEL amplifier stage 2 RCLK TXA+ TXA− RCLK ICLK low−noise half−rate clock synthesizer PLL QCLK VML output buffer Q Q Q I1 I2 2 ICLK MUX 2 2 2 DOUT QCLK signal conditioning PLL DIN 2 SEL input buffer stage + RXB+ RXB− reference voltage and bias current generation VDD ENA LBA VDD GND GND LBB ENB Figure 5. Data Path in Internal Loop-Back Mode A INTERNAL LOOP-BACK MODE B In internal loop-back mode B operation, which is activated by pulling the LBB pin low, the input data signal at the RXB+/RXB– pins is applied to an input buffer driving a signal conditioning PLL. The retimed output signal is connected to the output pins TXA+/TXA– by means of a multiplexer stage and a VML output buffer. Additionally, by means of a second multiplexer, the same signal is fed to the second VML output buffer, which drives the TXB+/TXB– output 8 TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER www.ti.com SLLS661 – JUNE 2005 OPERATIONAL MODES (continued) The signals applied to the RXA+/RXA– input is not fed to any output in this mode. input buffer stage RXA+ + RXA− − 2 DIN signal conditioning PLL ICLK DOUT VML output buffer MUX 2 QCLK I1 Q 2 Q I2 Q TXB+ TXB− SEL amplifier stage 2 RCLK TXA+ RCLK ICLK low−noise half−rate clock synthesizer PLL QCLK VML output buffer 2 ICLK MUX Q 2 Q Q TXA− 2 I1 I2 2 QCLK signal conditioning PLL DOUT 2 DIN input buffer stage + RXB+ RXB− SEL reference voltage and bias current generation VDD ENA LBA VDD GND GND LBB ENB Figure 6. Data Path in Internal Loop-Back Mode B INTERNAL LOOP-BACK MODES A AND B If both internal loop-back modes A and B are activated simultaneously, by pulling the LBA and the LBB pins low, the input data signal at RXA+/RXA– is applied to an input buffer driving a signal conditioning PLL. The retimed output signal is fed to the output TXA+/TXA– by means of a multiplexer stage and a VML output buffer. The signals applied to the RXB+/RXB– input drives an input buffer connected to a signal conditioning PLL. The retimed output signal is connected to the output pins TXB+/TXB– by means of a multiplexer stage and a VML output buffer. input buffer stage RXA+ + RXA− − 2 DIN signal conditioning PLL ICLK DOUT VML output buffer MUX 2 QCLK I1 Q 2 Q I2 Q TXB+ TXB− SEL amplifier stage 2 RCLK TXA+ TXA− RCLK ICLK low−noise half−rate clock synthesizer PLL QCLK VML output buffer Q Q Q I1 I2 2 ICLK MUX 2 2 2 DOUT QCLK signal conditioning PLL DIN 2 SEL input buffer stage + RXB+ RXB− reference voltage and bias current generation VDD ENA LBA VDD GND GND LBB ENB Figure 7. Data Path in Internal Loop-Back Modes A and B 9 PACKAGE OPTION ADDENDUM www.ti.com 27-Feb-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLK1002ARGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLK1002ARGERG4 ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLK1002ARGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLK1002ARGETG4 ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLK1002ARGER VQFN RGE 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TLK1002ARGET VQFN RGE 24 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLK1002ARGER VQFN RGE 24 3000 340.5 333.0 20.6 TLK1002ARGET VQFN RGE 24 250 340.5 333.0 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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