TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 10-BIT DIGITAL-TO-ANALOG CONVERTERS FEATURES • • • • • • • • • • • 10-Bit CMOS Voltage Output DAC in an 8-Terminal Package 5V Single Supply Operation 3-Wire Serial Interface High-Impedance Reference Inputs Voltage Output Range: 2 Times the Reference Input Voltage Internal Power-On Reset Low Power Consumption: 1.75mW Max Update Rate of 1.21MHz Settling Time to 0.5LSB: 12.5µs Typ Monotonic Over Temperature Pin-Compatible With the Maxim MAX515 APPLICATIONS • • • • • Battery-Powered Test Instruments Digital Offset and Gain Adjustment Battery Operated/Remote Industrial Controls Machine and Motion Control Devices Cellular Telephones DESCRIPTION The TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is monotonic. The device is simple to use, running from a single supply of 5V. A power-on-reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to produce the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication protocols include the SPI™, QSPI™, and Microwire™ standards. The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications. The TLC5615C is characterized for operation from 0°C to +70°C. The TLC5615I is characterized for operation from –40°C to +85°C. D, P, OR DGK PACKAGE (TOP VIEW) DIN SCLK CS DOUT 1 8 2 7 3 6 4 5 VDD OUT REFIN AGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996–2007, Texas Instruments Incorporated TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM _ + _ 2 DAC + REFIN OUT (Voltage Output) AGND R Power-ON Reset R 10-Bit DAC Register Control Logic CS 2 0s SCLK (LSB) (MSB) 10 Data Bits DIN 4 Dummy Bits DOUT 16-Bit Shift Register Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION DIN 1 I Serial data input SCLK 2 I Serial clock input CS 3 I Chip select, active low DOUT 4 O Serial data output for daisy chaining AGND 5 REFIN 6 I Reference input OUT 7 O DAC analog voltage output VDD 8 Analog ground Positive power supply PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 Submit Documentation Feedback TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage (VDD to AGND) 7V Digital input voltage range to AGND –0.3V to VDD + 0.3V Reference input voltage range to AGND –0.3V to VDD + 0.3V Output voltage at OUT from external source VDD + 0.3V ±20mA Continuous current at any terminal Operating free-air temperature range, TA TLC5615C 0°C to +70°C TLC5615I –40°C to +85°C Storage temperature range, Tstg –65°C to +150°C Lead temperature 1,6mm (1/16 inch) from case for 10 seconds (1) +260°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX Supply voltage, VDD 4.5 5 5.5 High-level digital input voltage, VIH 2.4 0.8 2 Load resistance, RL 2 Operating free-air temperature, TA V V Low-level digital input voltage, VIL Reference voltage, Vref to REFIN terminal UNIT 2.048 VDD–2 V V kΩ TLC5615C 0 70 °C TLC5615I 40 85 °C ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, VDD = 5V ± 5%, Vref = 2.048V (unless otherwise noted) STATIC DAC SPECIFICATIONS PARAMETER TEST CONDITIONS MIN Resolution EZS EG Integral nonlinearity, end point adjusted (INL) Vref = 2.048V, See (1) Differential nonlinearity (DNL) Vref = 2.048V, See (2) Zero-scale error (offset error at zero scale) Vref = 2.048V, See (3) Zero-scale-error temperature coefficient Vref = 2.048V, See (4) Gain error Vref = 2.048V, See (5) Gain-error temperature coefficient Vref = 2.048V, See (6) PSRR Power-supply rejection ratio Analog full scale output (1) (2) (3) (4) (5) (6) (7) (8) TYP MAX 10 Zero scale Gain See (7) (8) RL = 100kΩ UNIT bits ±0.1 ±1 LSB ±0.5 LSB ±3 LSB 3 ppm/°C ±3 1 80 LSB ppm/°C dB 80 2Vref(1023/1024) V The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). Tested from code 3 to code 1024. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Tested from code 3 to code 1024. Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text). Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax– Tmin). Gain error is the deviation from the ideal output (Vref – 1LSB) with an output load of 10kΩ excluding the effects of the zero-scale error. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax– Tmin). Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5V to 5.5V dc and measuring the proportion of this signal imposed on the zero-code output voltage. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5V to 5.5V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero-scale change. Submit Documentation Feedback 3 TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 VOLTAGE OUTPUT (OUT) PARAMETER VO TEST CONDITIONS Voltage output range RL= 10kΩ Output load regulation accuracy VO(OUT) = 2V, IOSC Output short circuit current OUT to VDD or AGND VOL(low) Output voltage, low-level IO(OUT)≤ 5mA VOH(high) Output voltage, high-level IO(OUT)≤– 5mA MIN TYP 0 MAX VDD–0.4 RL = 2kΩ 0.5 20 UNIT V LSB mA 0.25 4.75 V V REFERENCE INPUT (REFIN) VI Input voltage ri Input resistance Ci Input capacitance 0 VDD–2 V 10 MΩ 5 pF DIGITAL INPUTS (DIN, SCLK, CS) VIH High-level digital input voltage VIL Low-level digital input voltage 2.4 IIH High-level digital input current VI = VDD IIL Low-level digital input current VI = 0 Ci Input capacitance V 0.8 V ±1 µA ±1 µA 8 pF DIGITAL OUTPUT (DOUT) VOH Output voltage, high-level IO = –2mA VOL Output voltage, low-level IO = 2mA VDD–1 V 0.4 V 5 5.5 V POWER SUPPLY VDD Supply voltage IDD 4.5 Power supply current VDD = 5.5V, No load, All inputs = 0V or VDD Vref = 0 150 250 µA VDD= 5.5V, No load, All inputs = 0V or VDD Vref = 2.048V 230 350 µA ANALOG OUTPUT DYNAMIC PERFORMANCE Vref = 1VPP at 1kHz + 2.048Vdc, code = 11 1111 1111 (1) Signal-to-noise + distortion, S/(N+D) (1) 60 dB The limiting frequency value at 1VPP is determined by the output-amplifier slew rate. DIGITAL INPUT TIMING REQUIREMENTS (See Figure 1) PARAMETER MIN NOM MAX UNIT tsu(DS) Setup time, DIN before SCLK high 45 ns th(DH) Hold time, DIN valid after SCLK high 0 ns tsu(CSS) Setup time, CS low to SCLK high 1 ns tsu(CS1) Setup time, CS high to SCLK high 50 ns th(CSH0) Hold time, SCLK low to CS low 1 ns th(CSH1) Hold time, SCLK low to CS high 0 ns tw(CS) Pulse duration, minimum chip select pulse width high 20 ns tw(CL) Pulse duration, SCLK low 25 ns tw(CH) Pulse duration, SCLK high 25 ns OUTPUT SWITCHING CHARACTERISTICS PARAMETER tpd(DOUT) 4 Propagation delay time, DOUT TEST CONDITIONS CL = 50pF Submit Documentation Feedback MIN NOM MAX 50 UNIT ns TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 OPERATING CHARACTERISTICS over recommended operating free-air temperature range, VDD = 5V ±5%, Vref = 2.048V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.3 0.5 V/µs 12.5 µs ANALOG OUTPUT DYNAMIC PERFORMANCE SR Output slew rate CL = 100pF, TA= +25°C RL = 10kΩ, ts Output settling time To 0.5LSB, RL = 10kΩ, CL = 100pF, Glitch energy DIN = All 0s to all 1s (1) 5 nV-s REFERENCE INPUT (REFIN) (1) (2) Reference feedthrough REFIN = 1VPP at 1kHz + 2.048Vdc Reference input bandwidth (f–3dB) REFIN = 0.2VPP + 2.048Vdc (2) –80 dB 30 kHz Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change of 000 hex to 3FF hex or 3FF hex to 000 hex. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048Vdc + 1Vpp at 1kHz. PARAMETER MEASUREMENT INFORMATION CS ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ th(CSH0) tsu(CSS) tw(CS) tw(CH) tw(CL) SCLK See Note A tsu(DS) th(CSH1) See Note C th(DH) DIN tpd(DOUT) DOUT ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Previous LSB MSB tsu(CS1) See Note A LSB See Note B NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough. B. Data input from preceeding conversion cycle. C. Sixteenth SCLK falling edge Figure 1. Timing Diagram Submit Documentation Feedback 5 TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS OUTPUT SINK CURRENT vs OUTPUT PULLDOWN VOLTAGE OUTPUT SOURCE CURRENT vs OUTPUT PULLUP VOLTAGE 30 20 IO - Output Sink Current - mA 16 VDD = 5 V VREFIN = 2.048 V TA = 25°C IO - Output Source Current - mA 18 14 12 10 8 6 4 VDD = 5 V VREFIN = 2.048 V TA = 25°C 25 20 15 10 5 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 1 4.8 4.6 5 1.1 1.2 4 3.8 3.6 3.4 Figure 2. Figure 3. SUPPLY CURRENT vs TEMPERATURE VREFIN TO V(OUT) RELATIVE GAIN vs INPUT FREQUENCY 280 3.2 3 4 VDD = 5 V VREFIN = 0.2 VPP + 2.048 V dc TA = 25°C 2 240 0 200 G - Relative Gain - dB I DD - Supply Current - µ A 4.4 4.2 VO - Output Pullup Voltage - V VO - Output Pulldown Voltage - V 160 120 80 -2 -4 -6 -8 - 10 40 VDD = 5 V VREFIN = 2.048 V TA = 25°C 0 - 60 - 40 - 20 - 12 0 20 40 60 80 t - Temperature - °C 100 120 140 - 14 1 1k 10 k fI - Input Frequency - Hz Figure 4. 6 100 Figure 5. Submit Documentation Feedback 100 k TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY AT REFIN 70 VDD = 5 V TA = 25°C VREFIN = 4 VPP Signal-To-Noise + Distortion - dB 60 50 40 30 20 10 0 1k 10 k 100 k 300 k Frequency - Hz Figure 6. Differential Nonlinearity – LSB 0.2 0.15 0.1 0.05 0 –0.05 –0.1 –0.15 –0.2 0 255 511 767 1023 Integral Nonlinearity – LSB Input Code Figure 7. Differential Nonlinearity With Input Code 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 255 511 767 1023 Input Code Figure 8. Integral Nonlinearity With Input Code Submit Documentation Feedback 7 TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 APPLICATION INFORMATION GENERAL FUNCTION The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digital data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the same polarity as the reference input (see Table 1). An internal circuit resets the DAC register to all zeros on power up. DIN REFIN + _ SCLK CS Resistor String DAC DOUT + _ OUT R R AGND VDD 5V 0.1 µF Figure 9. TLC5615 Typical Operating Circuit Table 1. Binary Code Table (0V to 2VREFINOutput), Gain = 2 INPUT (1) 1111 1111 OUTPUT 1023 2 VREFIN 1024 ǒ 11(00) Ǔ : : 1000 0000 01(00) 513 2 VREFIN 1024 1000 0000 00(00) 512 2 VREFIN + V REFIN 1024 0111 1111 11(00) ǒ ǒ Ǔ 8 Ǔ 511 ǒ 2 VREFIN 1024 : (1) Ǔ : 0000 0000 01(00) 1 2 VREFIN 1024 0000 0000 00(00) 0V ǒ Ǔ A 10-bit data word with two bits below the LSB bit (sub-LSB) with 0 values must be written since the DAC input latch is 12 bits wide. Submit Documentation Feedback TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 BUFFER AMPLIFIER The output buffer has a rail-to-rail output with short circuit protection and can drive a 2kΩ load with a 100pF load capacitance. Settling time is 12.5µs typical to within 0.5LSB of final value. EXTERNAL REFERENCE The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore, the REFIN input resistance is 10MΩ and the REFIN input capacitance is typically 5pF independent of input code. The reference voltage determines the DAC full-scale output. LOGIC INTERFACE The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic levels. SERIAL CLOCK AND UPDATE RATE Figure 1 shows the TLC5615 timing. The maximum serial clock rate is: f(SCLK)max + t wǒCHǓ 1 )t wǒCLǓ or approximately 14MHz. The digital update rate is limited by the chip-select period, which is: tp(CS) + 16 ǒ t wǒCHǓ )t Ǔ wǒCLǓ )t wǒCSǓ and is equal to 820ns which is a 1.21MHz update rate. However, the DAC settling time to 10 bits of 12.5µs limits the update rate to 80kHz for full-scale input step transitions. SERIAL INTERFACE When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most significant bit first. The rising edge of the SLCK input shifts the data into the input register. The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clocked into the input register. All CS transitions should occur when the SCLK input is low. If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data sequence with the MSB first can be used as shown in Figure 10: 12 Bits 10 Data Bits x MSB LSB x 2 Extra (Sub-LSB) Bits x = don’t care Figure 10. 12-Bit Input Data Sequence or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first. 16 Bits 4 Upper Dummy Bits 10 Data Bits MSB x LSB x 2 Extra (Sub-LSB) Bits x = don’t care Figure 11. 16-Bit Input Data Sequence Submit Documentation Feedback 9 TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width. When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data transfer requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUT terminal (see Figure 1). The two extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit data converter transfers. The TLC5615 three-wire interface is compatible with the SPI, QSPI, and Microwire serial standards. The hardware connections are shown in Figure 12 and Figure 13. The SPI and Microwire interfaces transfer data in 8-bit bytes; therefore, two write cycles are required to input data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC input register in one write cycle. SCLK DIN TLC5615 CS DOUT SK SO Microwire Port I/O SI NOTE A: The DOUT-SI connection is not required for writing to the TLC5615 but may be used for verifying data transfer if desired. Figure 12. Microwire Connection SCLK DIN TLC5615 CS DOUT SCK MOSI I/O SPI/QSPI Port MISO CPOL = 0, CPHA = 0 NOTE A: The DOUT-MISO connection is not required for writing to the TLC5615 but may be used for verifying data transfer. Figure 13. SPI/QSPI Connection DAISY-CHAINING DEVICES DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in the chain, providing that the setup time, tsu(CSS) (CS low to SCLK high), is greater than the sum of the setup time, tsu(DS), plus the propagation delay time, tpd(DOUT), for proper timing (see digital input timing requirements section). The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is a totem-poled output for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high, DOUT remains at the value of the last data bit and does not go into a high-impedance state. LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE-ENDED SUPPLIES When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. 10 Submit Documentation Feedback TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14. Output Voltage 0V DAC Code Negative Offset Figure 14. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs '0') and full-scale code (all inputs '1') after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. For the TLC5615, the zero-scale (offset) error is ±3LSB maximum. The code is calculated from the maximum specification for the negative offset. POWER-SUPPLY BYPASSING AND GROUND MANAGEMENT Printed circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 15 shows the ground plane layout and bypassing technique. Analog Ground Plane 1 8 2 7 3 6 4 5 0.1 µF Figure 15. Power-Supply Bypassing SAVING POWER Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output load when the system is not using the DAC. Submit Documentation Feedback 11 TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 AC CONSIDERATIONS Digital Feedthrough Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through the DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digital feedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT. Analog Feedthrough Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to REFIN, and monitoring the DAC output. 12 Submit Documentation Feedback TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from D Revision (August 2003) to E Revision ............................................................................................... Page • • Added ESD statement. ......................................................................................................................................................... 2 Changed —moved package option table from front page. ................................................................................................... 2 Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 30-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC5615CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615CDGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615CDGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615CDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615CDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC5615CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC5615ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615IDGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615IDGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615IDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615IDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5615IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC5615IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 30-May-2007 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC5615CDGKR DGK 8 SITE 60 330 12 5.3 3.4 1.4 8 12 Q1 TLC5615CDR D 8 SITE 60 330 12 6.4 5.2 2.1 8 12 Q1 TLC5615CDR D 8 SITE 27 330 0 6.4 5.2 2.1 8 12 Q1 TLC5615IDGKR DGK 8 SITE 60 330 12 5.3 3.4 1.4 8 12 Q1 TLC5615IDR D 8 SITE 60 330 12 6.4 5.2 2.1 8 12 Q1 TLC5615IDR D 8 SITE 27 330 0 6.4 5.2 2.1 8 12 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) TLC5615CDGKR DGK 8 SITE 60 346.0 346.0 29.0 TLC5615CDR D 8 SITE 60 346.0 346.0 29.0 TLC5615CDR D 8 SITE 27 342.9 336.6 20.64 TLC5615IDGKR DGK 8 SITE 60 346.0 346.0 29.0 TLC5615IDR D 8 SITE 60 346.0 346.0 29.0 TLC5615IDR D 8 SITE 27 342.9 336.6 20.64 Pack Materials-Page 2 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. 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