SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004
D
D
D
† For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI
application report, CBT-C, CB3T, and CB3Q
Signal-Switch Families, literature number SCDA008.
D
D
D
D
D
D
D
RGY PACKAGE
(TOP VIEW)
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1OE
1A1
2B4
1A2
2B3
1A3
2B2
1A4
2B1
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1B1
2A4
1B2
2A3
1B3
2A2
1B4
2A1
1A1
2B4
1A2
2B3
1A3
2B2
1A4
2B1
VCC
D
D
Undershoot Clamp Diodes
Low Power Consumption
(ICC = 0.7 mA Typical)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0- to 5-V Signaling
Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V,
5 V)
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
Supports Both Digital and Analog
Applications: Differential Signal Interface,
Memory Interleaving, Bus Isolation,
Low-Distortion Signal Gating
1
20
19 2OE
18 1B1
2
3
17 2A4
16 1B2
4
5
15 2A3
14 1B3
6
7
13 2A2
12 1B4
8
9
10
11
2A1
D
D Data and Control Inputs Provide
1OE
D
(Up To 500 MHz†)
5-V-Tolerant I/Os with Device Powered Up
or Powered Down
Low and Flat ON-State Resistance (ron)
Characteristics Over Operating Range
(ron = 4 Ω Typical)
Rail-to-Rail Switching on Data I/O Ports
− 0- to 5-V Switching With 3.3-V VCC
− 0- to 3.3-V Switching With 2.5-V VCC
Bidirectional Data Flow, With Near-Zero
Propagation Delay
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 3.5 pF Typical)
Fast Switching Frequency
(fOE = 20 MHz Max)
GND
D High-Bandwidth Data Path
description/ordering information
The SN74CB3Q3244 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage
of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance
allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The
device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data
bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3244 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &/* &*#$' "! *0%' '&#)$*&'
'&%.%#. 1%##%&2 #".)(&" +#"(*''3 ."*' "& *(*''%#-2 (-).*
&*'&3 "! %-- +%#%$*&*#'
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1
SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004
description/ordering information (continued)
The SN74CB3Q3244 is organized as two 4-bit bus switches with separate output-enable (1OE, 2OE) inputs.
It can be used as two 4-bit bus switches or as one 8-bit bus switch. When OE is low, the associated 4-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 4-bit bus switch is OFF, and the high-impedance state exists between the A and B
ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
QFN − RGY
Tape and reel
SN74CB3Q3244RGYR
Tube
SN74CB3Q3244DW
Tape and reel
SN74CB3Q3244DWR
SSOP − DB
Tape and reel
SN74CB3Q3244DBR
BU244
SSOP (QSOP) − DBQ
Tape and reel
SN74CB3Q3244DBQR
CB3Q3244
Tube
SN74CB3Q3244PW
Tape and reel
SN74CB3Q3244PWR
Tape and reel
SN74CB3Q3244DGVR
SOIC − DW
−40°C
−40
C to 85
85°C
C
TOP-SIDE
MARKING
TSSOP − PW
TVSOP − DGV
BU244
CB3Q3244
BU244
BU244
VFBGA − GQN
Tape and reel
SN74CB3Q3244GQNR
BU244
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
GQN PACKAGE
(TOP VIEW)
1
2
3
terminal assignments
4
1
2
3
4
A
A
1A1
1OE
B
1A2
2A4
VCC
2B4
2OE
B
C
C
1A3
2B3
2A3
1B2
D
D
1A4
2A2
2B2
1B3
E
E
GND
2B1
2A1
1B4
FUNCTION TABLE
(each 4-bit bus switch)
2
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
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1B1
SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004
logic diagram (positive logic)
18
2
1A1
1B1
SW
12
8
1A4
1B4
SW
1
1OE
11
9
2A1
2B1
SW
17
3
2A4
SW
2B4
19
2OE
simplified schematic, each FET switch (SW)
A
B
VCC
Charge
Pump
EN†
† EN is the internal enable signal applied to the switch.
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3
SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±64 mA
Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 5): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 5): GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
VCC
Supply voltage
VIH
High-level control input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low-level control input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI/O
TA
Data input/output voltage
Operating free-air temperature
MIN
MAX
UNIT
2.3
3.6
1.7
5.5
V
2
5.5
0
0.7
0
0.8
0
5.5
V
−40
85
°C
V
V
NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
IIN
TEST CONDITIONS
MIN
VCC = 3.6 V,
VCC = 3.6 V,
II = −18 mA
VIN = 0 to 5.5 V
IOZ‡
VCC = 3.6 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
Ioff
VCC = 0,
VI = 0
ICC
VCC = 3.6 V,
VO = 0 to 5.5 V,
II/O = 0,
Switch ON or OFF,
Control inputs
∆ICC§
Control inputs
ICCD¶
Per control
input
VCC = 3.6 V,
One input at 3 V,
VCC = 3.6 V,
A and B ports open,
Control input switching at 50% duty cycle
Cin
Control inputs
VCC = 3.3 V,
VIN = VCC or GND
TYP†
0.7
Other inputs at VCC or GND
MAX
UNIT
−1.8
V
±1
µA
±1
µA
1
µA
2
mA
30
VIN = 5.5 V, 3.3 V, or 0
Switch OFF,
VI/O = 5.5 V, 3.3 V, or 0
VIN = VCC or GND,
0.14
0.15
2.5
3.5
pF
3.5
5
pF
pF
Cio(OFF)
VCC = 3.3 V,
Cio(ON)
VCC = 3.3 V,
Switch ON,
VIN = VCC or GND,
VI/O = 5.5 V, 3.3 V, or 0
9
11
VCC = 2.3 V,
TYP at VCC = 2.5 V
VI = 0,
VI = 1.7 V,
IO = 30 mA
IO = −15 mA
4
8
5
9
VCC = 3 V
VI = 0,
VI = 2.4 V,
IO = 30 mA
IO = −15 mA
4
6
5
8
ron#
µA
mA/
MHz
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
¶ This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2).
# Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
PARAMETER
fOE||
tpdk
ten
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
OE
A or B
10
20
MHz
A or B
B or A
0.12
0.2
ns
OE
A or B
5.9
ns
2.8
7.1
2.5
tdis
A or B
1
5.8
1.5
5.8
ns
OE
|| Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0)
k The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
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5
SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004
TYPICAL ron
vs
VI
ron − ON−State Resistance − Ω
16
VCC = 3.3 V
TA = 25°C
IO = −15 mA
14
12
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VI − V
Figure 1. Typical ron vs VI, VCC = 3.3 V and IO = −15 mA
TYPICAL ICC
vs
OE SWITCHING FREQUENCY
12
VCC = 3.3 V
TA = 25°C
A and B ports Open
10
ICC − mA
8
6
4
One OE Switching
2
0
0
2
4
6
8
10
12
14
16
OE Switching Frequency − MHz
Figure 2. Typical ICC vs OE Switching Frequency, VCC = 3.3 V
6
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18
20
SCDS154B − OCTOBER 2003 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
Input Generator
VI
S1
RL
VO
50 Ω
VG2
CL
(see Note A)
RL
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
VCC or GND
VCC or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
GND
GND
500 Ω
500 Ω
VCC
VCC
30 pF
50 pF
0.15 V
0.3 V
Output
Control
(VIN)
V∆
VCC
VCC/2
VCC
VCC/2
0V
tPLH
VOH
Output
VCC/2
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC/2
Open
GND
50 Ω
Output
Control
(VIN)
2 × VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOL + V∆
VOL
tPHZ
VCC/2
VOH − V∆
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74CB3Q3244DBQR
ACTIVE
SSOP/
QSOP
DBQ
20
2500
Pb-Free
(RoHS)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74CB3Q3244DBR
PREVIEW
SSOP
DB
16
2000
None
Call TI
SN74CB3Q3244DGVR
ACTIVE
TVSOP
DGV
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Call TI
Level-1-250C-UNLIM
SN74CB3Q3244DW
PREVIEW
SOIC
DW
16
40
None
Call TI
Call TI
SN74CB3Q3244DWR
PREVIEW
SOIC
DW
16
2000
None
Call TI
Call TI
SN74CB3Q3244GQNR
ACTIVE
VFBGA
GQN
20
1000
None
SNPB
Level-1-240C-UNLIM
SN74CB3Q3244PW
ACTIVE
TSSOP
PW
20
70
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3Q3244PWR
ACTIVE
TSSOP
PW
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3Q3244RGYR
ACTIVE
QFN
RGY
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74CB3Q3244ZQNR
ACTIVE
VFBGA
ZQN
20
1000
SNAGCU
Level-1-260C-UNLIM
Pb-Free
(RoHS)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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