FUJITSU SEMICONDUCTOR DATA SHEET DS601-00001-2v0-E Semicustom CMOS Standard Cell CS401 Series ■ DESCRIPTION The CS401 series of 28 nm standard cells is a line of CMOS ASICs that satisfy demands for lower power consumption, higher speed and higher integration. These cells offer the minimum level of leakage current in the semiconductor industry, and are able to implement a mixture of core transistors with four different threshold voltages, as appropriate for the applications ranging from handheld terminals to digital audiovisual equipment. The integration level in this series is twice the CS302 series with lower power consumption and higher speed. ■ FEATURES • Technology • • • • • • • • • • • • • • : 28 nm Metal-gate CMOS : Maximum 11-metal layers. Ultra low permittivity material is used for dielectric inter-layers. : Four different types of core transistors (low leak, standard, high speed and ultra high speed) can be used on the same chip. Supply voltage : Internal power supply : + 1.0 V ± 0.1 V : External power supply : + 1.8 V ± 0.15 V (1.8V interface on dual-power supply system) + 2.5 V ± 0.2 V (2.5V interface on dual-power supply system) + 3.3 V ± 0.3 V (3.3V interface on dual-power supply system) Junction temperature range: − 40 °C to + 125 °C (standard specification) Gate power consumption: 0.61 nW / gate (operating condition: 1.0 V, operating rate 0.5, 1 MHz) Support high-quality, various types of cell sets developed by FUJITSU SEMICONDUCTOR (from low power versions to high speed versions). Support SRAMs with standby-mode and power-down mode for lower power consumption memories. Compiled cells (RAM, ROM, others) Support special interfaces (LVDS, SSTL, others). Support boundary SCAN test. Support use of industry standard libraries. Support use of industry standard tools. Short-term development using a physical prototyping tool One pass design using a physical synthesis tool Hierarchical design environment for supporting large-scale circuits Support Signal Integrity, EMI noise reduction. (Continued) Copyright©2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2012.10 CS401 Series (Continued) • Support static timing sign-off. • Improve timing convergence by using Statistical Static Timing Analysis (SSTA). • Design For Manufacturing (DFM) enables stable product-supply and reduced variation. • Package lineup: FBGA, PBGA, TEBGA, FC-BGA Note: Including items under development. ■ MACRO LIBRARIES (INCLUDING MACROS CURRENTLY BEING PREPARED) 1. Logic cells (about 400 types) Library sets having four different threshold voltages of core transistors. • Adder • AND • AND-OR • AND-OR Inverter • Buffer • Clock-Buffer • Delay Buffer • ENOR • EOR • Inverter • Latch • NAND • NOR • OR • OR-AND • OR-AND Inverter • SCAN Flip flop • Non-SCAN Flip flop • Selector • Others 2. IP macros CPU/DSP ARMTM* cores (ARM7TDMI-STM*, ARM946E-STM*, ARM926EJ-STM*, ARM1176JZF-STM*, Cortex-M3TM*, Cortex-R4FTM*, Cortex-A9TM* MPCore), Peripherals IP Mixed signal macro ADC, DAC, OPAMP, others Compiled macro SRAM (1 Port, 2 Port), ROM, product sum calculator, others PLL Analog PLL *: ARM, ARM7TDMI-S, ARM946E-S, ARM926EJ-S, ARM1176JZF-S, Cortex-M3, Coretex-R4F and Cortex-A9 are the trademarks of ARM Limited in the EU and other countries. 3. Special I/O interface macro Special I/O LVDS, SSTL18, PCI, I2C Interface macro USB2.0 Device/host, Serial-ATA, PCI-Express, DDR2, HDMI, others 2 DS601-00001-2v0-E CS401 Series ■ COMPILED CELL Compiled cells are macro cells that can be automatically generated by specifying the bit/word configuration. The following compiled cells are available for the CS401 series. • Memory capacity Name Category Memory capacity (bit) High-Density 64 to 1152 K High-Speed 32 to 80 K Large-Scale 16 K to 9 M High-Density 32 to 144 K Clock synchronous ROM ⎯ 128 to 1152 K Clock synchronous register file (1RW) ⎯ 80 to 36 K Clock synchronous register file (1R1W) ⎯ 32 to 72 K Clock synchronous register file (2R2W) ⎯ 16 to 18 K Clock synchronous single-port RAM (1RW) Clock synchronous dual port RAM (2RW) DS601-00001-2v0-E 3 CS401 Series ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Remarks Min Max − 0.4 + 1.4 − 0.5 + 2.5 − 0.5 + 3.6 − 0.5 + 4.6 *5 − 0.5 VDD + 0.5 ( ≤ 2.5 V) *3 − 0.5 VDD + 0.5 ( ≤ 3.6 V) − 0.5 VDD + 0.5 ( ≤ 4.6 V) *5 − 0.5 VDD + 0.5 ( ≤ 2.5 V) *3 − 0.5 VDD + 0.5 ( ≤ 3.6 V) − 0.5 VDD + 0.5 ( ≤ 4.6 V) TSTG − 55 + 125 °C Operation junction temperature Tj − 40 + 125 °C Output current*6 IO ⎯ ⎯ mA ID ⎯ ⎯ mA Power supply voltage*1 VDD 1 VI Input voltage* Output voltage*1 VO Storage temperature 7 Power supply pin current* *2 V V V *3 *4 *4 *4 *5 *1: VSS = 0 V *2: Internal gates *3: 1.8 V interface on dual-power supply system *4: 2.5 V interface on dual-power supply system *5: 3.3 V interface on dual-power supply system *6: The output current varies depending on the number of wiring layers in the chip and the wiring configuration of the I/O cells. Contact the sales representative for details. *7: For details about the power supply pin current, contact the sales representative. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 4 DS601-00001-2v0-E CS401 Series ■ DESIGN METHODS Fujitsu Semiconductor's Reference Design Flow provides the following functions that help reduce the development time of large scale, high quality LSIs. • Statistical Static Timing Analysis (SSTA) improves timing convergence. • Physical Prototyping enables more accurate estimation of highly reliable designs. • Layout synthesis with optimized timing is realized by Physical Synthesis Tool. • High accuracy design environment where drop in power supply voltage, signal noise, delay penalty and crosstalk are considered • I/O design environment (power line design, assignment and selection of I/Os, package selection) where noise is considered ■ PACKAGES The CS401 series can use the same packages that were available for the previous series, allowing a smooth transition from previously developed models. For details of delivery times, contact the sales representative. • • • • FBGA packages PBGA packages TEBGA packages FC-BGA packages DS601-00001-2v0-E 5 CS401 Series MEMO 6 DS601-00001-2v0-E CS401 Series MEMO DS601-00001-2v0-E 7 CS401 Series FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. 30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District, Shanghai 201204, China Tel : +86-21-6146-3688 Fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 2/F, Green 18 Building, Hong Kong Science Park, Shatin, N.T., Hong Kong Tel : +852-2736-3232 Fax : +852-2314-4207 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. 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