FUJITSU CS402

FUJITSU SEMICONDUCTOR
DATA SHEET
DS601-00002-0v01-E
Semicustom
CMOS
Standard Cell
CS402 Series
■ DESCRIPTION
The CS402 series of 28 nm standard cells is a line of CMOS ASICs of high-performance with minimum
power consumption.
By the adoption of core transistors with high current drivability operating at low voltages, the operating
frequency approximately twice that of CS401 series is realized at power supply voltages 10% lower than
those of CS401 series.
This series is appropriate for high-performance/high-end applications ranging from the engines of handheld
terminals to telecommunication equipment.
■ FEATURES
• Technology
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: 28 nm Metal-gate CMOS
: Maximum 11-metal layers. Ultra low permittivity material is used for inter-layer dielectric.
: Core transistors with different threshold voltages can be used on the same chip
(ultra low leak, low leak, standard, high speed and ultra high speed).
Supply voltage : Internal power supply : + 0.9 V ± 0.09 V
: External power supply : + 1.8 V ± 0.15 V
(1.8V interface on dual-power supply system)
Junction temperature range: − 40 °C to + 125 °C (Standard specification)
Operating frequency: Approximately twice that of CS401 series
Support various types of high-quality cell sets developed by FUJITSU SEMICONDUCTOR (from low power
versions to high speed versions).
Support SRAMs with standby-mode and power-down mode for lower power consumption memories.
Compiled cells (RAM, ROM, others)
Support special interfaces (LVDS, SSTL, others).
Support boundary SCAN test.
Support use of industry standard libraries.
Support use of industry standard tools.
Short-term development using a physical prototyping tool
One-pass design using a physical synthesis tool
Hierarchical design environment for supporting large-scale circuits
Support Signal Integrity, EMI noise reduction.
Support static timing sign-off.
Improve timing convergence by the introduction of Statistical Static Timing Analysis (SSTA).
Design For Manufacturing (DFM) enables stable product-supply and reduced variation.
Package lineup: FBGA, PBGA, TEBGA, FC-BGA
Note: Including items under development.
Copyright©2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.6
CS402 Series
■ MACRO LIBRARIES (MACROS CURRENTLY BEING PREPARED ARE INCLUDED)
1. Logic cells (about 400 types)
Library sets for four types of core transistors with different threshold voltages.
• Adder
• AND
• AND-OR
• AND-OR Inverter
• Buffer
• Clock-Buffer
• Delay Buffer
• ENOR
• EOR
• Inverter
• Latch
• NAND
• NOR
• OR
• OR-AND
• OR-AND Inverter
• SCAN Flip flop
• Non-SCAN Flip flop
• Selector
• Others
2. IP macros
CPU/DSP
ARMTM* cores (ARM7TDMI-STM*, ARM946E-STM*, ARM926EJ-STM*,
ARM1176JZF-STM*, Cortex-M3TM*, Cortex-R4FTM*, Cortex-A9TM* MPCore),
Peripherals IP
Mixed signal macro
ADC, DAC,OPAMP, others
Compiled macro
SRAM (1 Port, 2 Port), ROM, product sum calculator, others
PLL
Analog PLL
*: ARM, ARM7TDMI-S, ARM946E-S, ARM926EJ-S, ARM1176JZF-S, Cortex-M3, Cortex-R4F and Cortex-A9
are the trademarks of ARM Limited in the EU and other countries.
3. Special I/O interface macros
Special I/O
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LVCMOS, LVDS, SSTL
DS601-00002-0v01-E
CS402 Series
■ COMPILED CELLS
Compiled cells are macro cells that can be automatically generated by specifying the bit/word configuration.
The following compiled cells are available for the CS402 series.
• Memory capacity
Name
Clock synchronous single-port RAM (1RW)
Clock synchronous dual port RAM (2RW)
Clock synchronous ROM
Clock synchronous register file (1RW)
Clock synchronous register file (1R1W)
Clock synchronous register file (2R2W)
DS601-00002-0v01-E
Category
Memory capacity (bit)
High-Density
64 to 1152K
High-Speed
32 to 80K
Large-Scale
TBD
High-Density
32 to 144K
⎯
128 to 1152K
High-Speed
96 to 36K
High-Density
96 to 36K
High-Speed
32 to 36K
High-Density
128 to 72K
⎯
16 to 18K
3
CS402 Series
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage*1
Symbol
VDD
Rating
Min
Max
− 0.4
+ 1.3
− 0.5
+ 2.5
Unit
V
Remarks
*2
*3
Input voltage*
VI
− 0.5
VDD + 0.5 ( ≤ 2.5 V )
V
*3
Output voltage*1
VO
− 0.5
VDD + 0.5 ( ≤ 2.5 V )
V
*3
Storage temperature
TSTG
− 55
+ 125
°C
Junction temperature
Tj
− 40
+ 125
°C
IO
⎯
⎯
mA
ID
⎯
⎯
mA
1
Output current*
4
Power supply pin current*5
*1: VSS = 0 V
*2: Internal gates
*3: 1.8 V interface on dual-power supply system
*4: The output current varies depending on the number of chip metal layers and the wiring configuration of the
I/O cells. For details, contact the sales representative.
*5: For details about the power supply pin current, contact the sales representative.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
4
DS601-00002-0v01-E
CS402 Series
■ DESIGN METHODS
Fujitsu Semiconductor's Reference Design Flow provides the following functions that help reduce the development time of large scale, high quality LSIs.
• Statistical Static Timing Analysis (SSTA) improves timing convergence.
• Physical Prototyping enables more accurate estimation of highly reliable designs.
• Layout synthesis with optimized timing is realized by Physical Synthesis Tool.
• High accuracy design environment where voltage drop of power supply, signal noise, delay penalty and
crosstalk are considered
• I/O design environment (power line design, assignment and selection of I/Os, package selection) where
noise is considered
■ PACKAGES
The CS402 series can use the same packages that are available for the previous series, allowing a smooth
transition from previously developed models. For details of delivery times, contact the sales representative.
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FBGA packages
PBGA packages
TEBGA packages
FC-BGA packages
DS601-00002-0v01-E
5
CS402 Series
MEMO
6
DS601-00002-0v01-E
CS402 Series
MEMO
DS601-00002-0v01-E
7
CS402 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
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http://sg.fujitsu.com/semiconductor/
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http://emea.fujitsu.com/semiconductor/
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Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
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FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
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limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
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Edited: Sales Promotion Department