SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS SCLS036B – MARCH 1984 – REVISED MAY 1997 D D D D D Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as ’HC32 Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54HC7032 . . . J OR W PACKAGE SN74HC7032 . . . D OR N PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y SN54HC7032 . . . FK PACKAGE (TOP VIEW) description + 1B 1A NC VCC 4B In these devices, each circuit functions as a quadruple OR gate. They perform the Boolean A • B or Y A B in positive function Y logic. However, because of the Schmitt action, the inputs have different input threshold levels for positive- and negative-going signals. + ) 1Y NC 2A NC 2B 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals. 4 The SN54HC7032 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC7032 is characterized for operation from –40°C to 85°C. NC – No internal connection FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H X H X H H L L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS SCLS036B – MARCH 1984 – REVISED MAY 1997 logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 1 ≥1 2 3 1Y 4 6 5 2Y 9 8 10 3Y 12 11 13 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages. logic diagram, each gate (positive logic) A Y B absolute maximum ratings over operating free-air temperature range‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS SCLS036B – MARCH 1984 – REVISED MAY 1997 recommended operating conditions SN54HC7032 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL Low-level input voltage Input voltage TA Operating free-air temperature NOM MAX 2 5 6 Output voltage MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 VCC = 4.5 V VCC = 6 V VI VO SN74HC7032 MIN UNIT V V 4.2 0 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC V 0 VCC VCC –55 125 –40 85 °C V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOL SN54HC7032 MIN MAX SN74HC7032 MIN MAX 1.9 1.998 1.9 1.9 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = –4 mA IOH = –5.2 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 VI = VIH or VIL VI = VIH or VIL VT+ VT– VT+ – VT– VI = VCC or 0 VI = VCC or 0, TA = 25°C TYP MAX 2V IOL = 4 mA IOL = 5.2 mA II ICC MIN 4.5 V IOH = –20 µA VOH VCC Ci V V 0.33 2V 0.7 1.2 1.5 0.7 1.5 0.7 1.5 4.5 V 1.55 2.5 3.15 1.55 3.15 1.55 3.15 6V 2.1 3.3 4.2 2.1 4.2 2.1 4.2 2V 0.3 0.6 1 0.3 1 0.3 1 4.5 V 0.9 1.6 2.45 0.9 2.45 0.9 2.45 6V 1.2 2 3.2 1.2 3.2 1.2 3.2 2V 0.2 0.6 1.2 0.2 1.2 0.2 1.2 4.5 V 0.4 0.9 2.1 0.4 2.1 0.4 2.1 6V 0.5 1.3 2.5 0.5 2.5 0.5 2.5 ±0.1 ±100 ±1000 ±1000 nA 2 40 20 µA 10 10 10 pF 6V IO = 0 UNIT 6V 2 V to 6 V 3 V V V PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS SCLS036B – MARCH 1984 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) PARAMETER tpd TO (OUTPUT) A or B Y tt Any VCC MIN TA = 25°C TYP MAX SN54HC7032 MIN SN74HC7032 MAX MIN MAX 2V 60 130 195 163 4.5 V 18 26 39 33 6V 14 22 33 28 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 UNIT ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate No load TYP UNIT 20 pF PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr tPHL VCC 50% 10% 0 V Out-of-Phase Output 90% tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. 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