MICROCHIP MCP3550-50-E/SN

MCP3550/1/3
Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs
Features
Description
• 22-bit ADC in Small 8-pin MSOP Package with
Automatic Internal Offset and Gain Calibration
• Low-Output Noise of 2.5 µVRMS with Effective
Resolution of 21.9 bits (MCP3550/1)
• 3 µV Typical Offset Error
• 2 ppm Typical Full Scale Error
• 6 ppm Maximum INL Error
• Total Unadjusted Error Less Than 10 ppm
• No Digital Filter Settling Time, Single-Command
Conversions through 3-wire SPI Interface
• Ultra-Low Conversion Current (MCP3550/1):
- 100 µA typical (VDD = 2.7V)
- 120 µA typical (VDD = 5.0V)
• Differential Input with VSS to VDD Common Mode
Range
• 2.7V to 5.5V Single-Supply Operation
• Extended Temperature Range:
- -40°C to +125°C
The Microchip Technology Inc. MCP3550/1/3 devices
are 2.7V to 5.5V low-power, 22-bit Delta-Sigma
Analog-to-Digital Converters (ADCs). The devices offer
output noise as low as 2.5 µVRMS, with a total
unadjusted error of 10 ppm. The family exhibits 6 ppm
Integral Non-Linearity (INL) error, 3 µV offset error and
less than 2 ppm full scale error. The MCP3550/1/3
devices provide high accuracy and low noise
performance
for
applications
where
sensor
measurements (such as pressure, temperature and
humidity) are performed. With the internal oscillator
and high oversampling rate, minimal external
components
are
required
for
high-accuracy
applications.
Applications
Package Types:
•
•
•
•
•
•
Weigh Scales
Direct Temperature Measurement
6-digit DVMs
Instrumentation
Data Acquisition
Strain Gauge Measurement
MSOP, SOIC
Internal
Oscillator
© 2009 Microchip Technology Inc.
VDD
Serial Interface
VIN-
3rd-Order
DS ADC
Modulator
w/ Internal
Calibration
VREF 1
8 VDD
VIN+ 2
7 CS
VIN– 3
6 SDO/RDY
VSS 4
5 SCK
VSS VDD
SINC 4
VIN+
The MCP3550/1/3 devices operate from -40°C to
+125°C and are available in the space-saving 8-pin
MSOP and SOIC packages.
MCP3550/1/3
Block Diagram
VREF
This product line has fully differential analog inputs,
making it compatible with a wide variety of sensor,
industrial control or process control applications.
SCK
SDO
RDY
CS
POR
DS21950E-page 1
MCP3550/1/3
NOTES:
DS21950E-page 2
© 2009 Microchip Technology Inc.
MCP3550/1/3
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
† Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
VDD...................................................................................7.0V
All inputs and outputs w.r.t VSS .... .......... -0.3V to VDD+ 0.3V
Difference Input Voltage ....................................... |VDD - VSS|
Output Short Circuit Current ................................ Continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±10 mA
Storage Temperature ....................................-65°C to +150°C
Ambient temp. with power applied ................-55°C to +125°C
ESD protection on all pins (HBM, MM) ............ ≥ 6 kV, ≥ 400V
Maximum Junction Temperature (TJ). .........................+150°C
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C ≤ TA ≤ +85°C, VDD = 2.7V or 5.0V.
VREF = 2.5V. VIN+ = VIN- = VCM = VREF/2. All ppm units use 2*VREF as full scale range. Unless otherwise noted, specification
applies to entire MCP3550/1/3 family.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Noise Performance (MCP3550/1)
No Missing Codes
NMC
22
—
—
bits
Output Noise
eN
—
2.5
—
µVRMS
Effective Resolution
ER
—
21.9
—
bits RMS
At DC (Note 5)
VREF = 5V
Noise Performance (MCP3553)
No Missing Codes
NMC
20
—
—
bits
Output Noise
eN
—
6
—
µVRMS
Effective Resolution
ER
—
20.6
—
bits RMS
At DC (Note 5)
VREF = 5V
Conversion Times
MCP3550-50
tCONV
-2.0%
80
+2.0%
ms
MCP3550-60
tCONV
-2.0%
66.67
+2.0%
ms
MCP3551
tCONV
-2.0%
73.1
+2.0%
ms
MCP3553
tCONV
-2.0%
16.67
+2.0%
ms
Accuracy
TA = +25°C only (Note 2)
Integral Non-Linearity
INL
—
±2
6
ppm
Offset Error
VOS
-12
±3
+12
µV
TA = +25°C
—
±4
—
µV
TA = +85°C
—
±6
—
µV
TA = +125°C
Positive Full Scale Error
VFS,P
-10
±2
+10
ppm
TA = +25°C only
Negative Full Scale Error
VFS,N
-10
±2
+10
ppm
TA = +25°C only
Offset Drift
—
0.040
—
ppm/°C
Positive/Negative Full Scale Error
Drift
—
0.028
—
ppm/°C
Note 1:
2:
3:
4:
5:
6:
This parameter is established by characterization and not 100% tested.
INL is the difference between the endpoints line and the measured code at the center of the quantization band.
This current is due to the leakage current and the current due to the offset voltage between VIN+ and VIN-.
Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. VREF = 5V.
Characterized by design, but not tested.
Rejection performance depends on internal oscillator accuracy; see Section 4.0 “Device Overview” for more information on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61 Hz.
© 2009 Microchip Technology Inc.
DS21950E-page 3
MCP3550/1/3
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C ≤ TA ≤ +85°C, VDD = 2.7V or 5.0V.
VREF = 2.5V. VIN+ = VIN- = VCM = VREF/2. All ppm units use 2*VREF as full scale range. Unless otherwise noted, specification
applies to entire MCP3550/1/3 family.
Parameters
Min
Typ
Max
Units
Common Mode DC Rejection
—
-135
—
dB
Power Supply DC Rejection
—
-115
—
dB
Rejection Performance
Sym
Conditions
(1,6)
VCM range from 0 to VDD
Common Mode 50/60 Hz Rejection
CMRR
—
-135
—
dB
VCM varies from 0V to VDD
Power Supply 50/60 Hz Rejection
PSRR
—
-85
—
dB
MCP3551 only, VDD varies from
4.5V to 5.5V
Power Supply 50/60 Hz Rejection
PSRR
—
-120
—
dB
MCP3550-50 or MCP3550-60 only
at 50 or 60 Hz respectively, VDD
varies from 4.5V to 5.5V
Normal Mode 50 and 60 Hz
Rejection
NMRR
—
-85
—
dB
MCP3551 only,
0 < VCM < VDD,
-VREF < VIN = (VIN + -VIN-) < +VREF
Normal Mode 50 or 60 Hz
Rejection
NMRR
—
-120
—
dB
MCP3550-50 or MCP3550-60 only
at 50 or 60 Hz respectively,
0 < VCM < VDD,
-VREF < VIN = (VIN + -VIN-) < +VREF
V
Analog Inputs
VIN+ − VIN-
-VREF
—
+VREF
Absolute/Common Mode Voltages
VSS - 0.3
—
VDD + 0.3
V
Analog Input Sampling Capacitor
—
10
—
pF
Differential Input Impedance
—
2.4
—
MΩ
Shutdown Mode Leakage Current
—
1
—
nA
Differential Input Range
Note 5
VIN+ = VIN- = VDD; CS = VDD
(Note 3)
Reference Input
Voltage Range
0.1
—
VDD
V
Reference Input Sampling
Capacitor
—
15
—
pF
Reference Input Impedance
—
2.4
—
MΩ
Note 4
Shutdown Mode Reference
Leakage Current
—
1
—
nA
VIN+ = VIN- = VSS; CS = VDD
Note 5
Power Requirements
Power Supply Voltage Range
VDD
2.7
—
5.5
V
MCP3550-50, MCP3551 Supply
Current
IDD
—
120
170
µA
—
100
—
µA
VDD = 2.7V
MCP3550-60, MCP3553 Supply
Current
IDD
—
140
185
µA
VDD = 5V
—
µA
VDD = 2.7V
—
120
Supply Current, Sleep Mode
IDDSL
—
10
Supply Current, Shutdown Mode
IDDS
—
—
Voltage Input High (CS, SCK)
VIH
0.7 VDD
—
—
V
Voltage Input Low (CS, SCK)
VIL
—
—
0.4
V
Voltage Output High (SDO/RDY)
VOH
VDD - 0.5
—
—
V
VDD = 5V
µA
1
µA
CS = SCK = VDD
Serial Interface
Note 1:
2:
3:
4:
5:
6:
VOH = 1 mA, VDD = 5.0V
This parameter is established by characterization and not 100% tested.
INL is the difference between the endpoints line and the measured code at the center of the quantization band.
This current is due to the leakage current and the current due to the offset voltage between VIN+ and VIN-.
Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. VREF = 5V.
Characterized by design, but not tested.
Rejection performance depends on internal oscillator accuracy; see Section 4.0 “Device Overview” for more information on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61 Hz.
DS21950E-page 4
© 2009 Microchip Technology Inc.
MCP3550/1/3
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C ≤ TA ≤ +85°C, VDD = 2.7V or 5.0V.
VREF = 2.5V. VIN+ = VIN- = VCM = VREF/2. All ppm units use 2*VREF as full scale range. Unless otherwise noted, specification
applies to entire MCP3550/1/3 family.
Parameters
Voltage Output Low (SDO/RDY)
Input leakage Current
(CS, SCK)
Internal Pin Capacitance
(CS, SCK, SDO/RDY)
Note 1:
2:
3:
4:
5:
6:
Sym
Min
Typ
Max
Units
VOL
—
—
0.4
V
ILI
-1
—
1
µA
CINT
—
5
—
pF
Conditions
VOH = -1 mA, VDD = 5.0V
Note 1
This parameter is established by characterization and not 100% tested.
INL is the difference between the endpoints line and the measured code at the center of the quantization band.
This current is due to the leakage current and the current due to the offset voltage between VIN+ and VIN-.
Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. VREF = 5V.
Characterized by design, but not tested.
Rejection performance depends on internal oscillator accuracy; see Section 4.0 “Device Overview” for more information on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61 Hz.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+125
°C
Thermal Resistance, 8L-MSOP
θJA
—
211
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
149.5
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
SERIAL TIMINGS
Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C ≤ TA ≤ +85°C,
VDD = 3.3V or 5.0V, SDO load = 50 pF.
Parameters
Sym
Min
Typ
Max
Units
fSCK
—
—
5
MHz
CLK High
tHI
90
—
—
ns
CLK Low
tLO
90
—
—
ns
CLK fall to output data valid
tDO
0
—
90
ns
CS low to indicate RDY state
tRDY
0
—
50
ns
CS minimum low time
tCSL
50
—
—
ns
RDY flag setup time
tSU
20
—
—
ns
CS rise to output disable
tDIS
20
—
—
ns
CS disable time
tCSD
90
—
—
ns
Power-up to CS LOW
tPUCSL
—
10
—
µs
CS High to Shutdown Mode
tCSHSD
—
10
—
µs
CLK Frequency
© 2009 Microchip Technology Inc.
Conditions
DS21950E-page 5
MCP3550/1/3
tRDY
tCSHSD
tCSD
CS
tCSL
tDIS
SDO
/RDY
tDO
tHI
tSU
SCK
FIGURE 1-1:
fSCK
tLO
Serial Timing.
VDD
tPUCSL
CS
FIGURE 1-2:
DS21950E-page 6
Power-up Timing.
© 2009 Microchip Technology Inc.
MCP3550/1/3
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
5
4
3
2
1
0
-1
-2
-3
-4
-5
-2.5
10
+125 C
+85 C
INL Error (ppm)
INL (ppm)
Note: Unless otherwise specified, TA = +25°C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-.
All ppm units use 2*VREF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.
-40 C
+25 C
8
6
4
2
0
-1.5
-0.5
0.5
1.5
2.5
0
0.5
1
1.5
VIN (V)
5
4
3
2
1
0
-1
-2
-3
-4
-5
-2.5
INL Error vs. Input Voltage
FIGURE 2-4:
VREF.
+125 C
+85 C
- 40 C
+25 C
-1.5
-0.5
0.5
1.5
2.5
+25 C
-40 C
-4
-3
-2
-1
0
1
2
3
4
5
VIN (V)
FIGURE 2-3:
INL Error vs. Input Voltage
(VDD = 5.0V, VREF = 5V).
© 2009 Microchip Technology Inc.
4
4.5
5
10
9
8
7
6
5
4
3
2
1
0
-50
-25
FIGURE 2-5:
Temperature.
Output Noise (µVRMS)
INL (ppm)
+125 C
+85 C
-5
3.5
0
25
50
75
100
125
Temperature (°C)
INL Error vs. Input Voltage
10
8
6
4
2
0
-2
-4
-6
-8
-10
3
Maximum INL Error vs.
VIN (V)
FIGURE 2-2:
(VDD = 5.0V).
2.5
VREF (V)
Max INL (ppm)
INL (ppm)
FIGURE 2-1:
(VDD = 2.7V).
2
10
9
8
7
6
5
4
3
2
1
0
-2.5
Maximum INL Error vs.
MCP3553
MCP3550/1
-1.5
-0.5
0.5
VIN (Volts)
1.5
2.5
FIGURE 2-6:
Output Noise vs. Input
Voltage (VDD = 2.7V).
DS21950E-page 7
MCP3550/1/3
Note: Unless otherwise specified, TA = +25°C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-.
All ppm units use 2*VREF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.
Output Noise (µVRMS )
Output Noise (µV RMS)
15
10
MCP3553
5
MCP3550/1
0
-2.5
-1.5
-0.5
0.5
1.5
2.5
10
9
8
7
6
5
4
3
2
1
0
MCP3553
MCP3550/1
-50
VIN (V)
-25
0
FIGURE 2-10:
Temperature.
FIGURE 2-7:
Output Noise vs. Input
Voltage (VDD = 5.0V).
25
50
75
Temperature (°C)
100
125
Output Noise vs.
5
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
4
Offset (µV)
Output Noise (µVRMS)
u
MCP3553
MCP3550/1
3
2
1
0
0.0
1.0
2.0
3.0
4.0
5.0
2.5
3
3.5
Output Noise vs. VREF .
FIGURE 2-11:
(VCM = 0V).
5
5.5
Offset Error vs VDD
7
10
9
8
7
6
5
4
3
2
1
0
6
Offset (µV)
Output Noise (µV RMS)
4.5
VDD (V)
VREF (V)
FIGURE 2-8:
4
MCP3553
MCP3550/1
5
4
3
2
1
0
2.5
3
3.5
4
4.5
5
VDD (V)
FIGURE 2-9:
DS21950E-page 8
Output Noise vs.VDD.
5.5
-50
-25
0
25
50
75
100
125
Temperature (°C)
FIGURE 2-12:
Offset Error vs.
Temperature (VREF = 5.0V).
© 2009 Microchip Technology Inc.
MCP3550/1/3
4000
5
4
3
2
1
0
-1
-2
-3
-4
-5
Number of Occurrences
Full Scale Error (ppm)
Note: Unless otherwise specified, TA = +25°C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-.
All ppm units are ratioed against 2*VREF . Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.
Positive Full Scale
Negative Full Scale
VDD = 5V
VREF = 2.5V
VCM = 1.25V
VIN = 0V
TA = 25C
16384
consecutiv
e readings
3500
3000
2500
2000
1500
1000
500
0
2.5
3
3.5
4
4.5
5
5.5
-15
-10
VDD (V)
10
8
6
4
2
0
-2
-4
-6
-8
-10
Full Scale Error vs. VDD .
FIGURE 2-16:
Histogram.
1800
Number of Occurrences
Full Scale Error (ppm)
FIGURE 2-13:
Positive Full Scale
Negative Full Scale
-50
-25
0
25
50
75
100
Full Scale Error vs.
Negative Full Scale
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-15:
Full Scale Error vs.
Temperature (VREF = 5.0V).
© 2009 Microchip Technology Inc.
5
10
15
1400
1200
1000
800
125
MCP3550/1 Output Noise
VDD = 5V
VREF = 2.5V
VCM = 1.25V
VIN = 0V
TA = 25°C
16384
consecutive
readings
600
400
200
FIGURE 2-17:
Histogram.
Positive Full Scale
-50
1600
-15
TUE (ppm)
Full Scale Error (ppm)
10
8
6
4
2
0
-2
-4
-6
-8
-10
0
0
125
Temperature (°C)
FIGURE 2-14:
Temperature.
-5
Output Code (LSB)
-10
-5
0
5
Output Code (LSB)
10
15
MCP3553 Output Noise
5.0
4.0
3.0
2.0
1.0
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
VIN (V)
FIGURE 2-18:
Total Unadjusted Error
(TUE) vs. Input Voltage (VDD = 2.7V).
DS21950E-page 9
MCP3550/1/3
5
4
3
2
1
0
-1
-2
-3
-4
-5
-2.5
6
Maximum TUE (ppm)
TUE (ppm)
Note: Unless otherwise specified, TA = +25°C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-.
All ppm units use 2*VREF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.
-1.5
-1
-0.5 0 0.5
VIN (V)
1
1.5
2
3
2
1
-50
2.5
-3
-2
-1
0
1
0
FIGURE 2-22:
Temperature.
10
8
6
4
2
0
-2
-4
-6
-8
-10
-4
-25
50
75
100
125
2
3
4
5
Maximum TUE vs.
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
2.5
2.7
3
VIN (V)
FIGURE 2-23:
FIGURE 2-20:
Total Unadjusted Error
(TUE) vs. Input Voltage (VREF = 5.0V).
10
9
8
7
6
5
4
3
2
1
0
3.3
VDD (V)
4
5
5.5
Maximum TUE vs. VDD.
0.6
0.5
0.4
IDDS (µA)
Maximum TUE (ppm)
25
Temperature (°C)
TUE (ppm)
TUE (ppm)
4
0
-2
FIGURE 2-19:
Total Unadjusted Error
(TUE) vs. Input Voltage.
-5
5
MCP3550/1
0.3
MCP3553
0.2
0.1
0
-0.1
0
1
2
3
4
5
-50
-25
FIGURE 2-21:
DS21950E-page 10
Maximum TUE vs. VREF .
0
25
50
75
100
125
Temperature (°C)
VREF (V)
FIGURE 2-24:
IDDS vs. Temperature.
© 2009 Microchip Technology Inc.
MCP3550/1/3
160
200
180
160
140
120
100
80
60
40
20
0
140
MCP3550-60, MCP3553
MCP3550-50, MCP3550/1
120
MCP3550-60, MCP3553
IDD (µA)
IDD (µA)
Note: Unless otherwise specified, TA = +25°C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-.
All ppm units use 2*VREF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.
MCP3550-50, MCP3550/1
100
80
60
40
20
0
2.5
3
3.5
4
4.5
5
5.5
-50
-25
VDD (V)
FIGURE 2-25:
IDD vs. VDD.
© 2009 Microchip Technology Inc.
0
25
50
75
100
125
Temperature (°C)
FIGURE 2-26:
IDD vs. Temperature.
DS21950E-page 11
MCP3550/1/3
NOTES:
DS21950E-page 12
© 2009 Microchip Technology Inc.
MCP3550/1/3
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP3550/1/3
PIN FUNCTION TABLE
Symbol
I/O/P
1
VREF
I
Reference Voltage Analog Input Pin
2
VIN+
I
Non-inverting Analog Input Pin
3
VIN-
I
Inverting Analog Input Pin
MSOP, SOIC
Description
4
VSS
P
Ground Pin
5
SCK
I
Serial Clock Digital Input Pin
6
SDO/RDY
O
Data/Ready Digital Output Pin
7
CS
I
Chip Select Digital Input Pin
8
VDD
P
Positive Supply Voltage Pin
Type Identification: I = Input; O = Output; P = Power
3.1
Voltage Reference (VREF)
The MCP3550/1/3 devices accept single-ended
reference voltages from 0.1V to VDD. Since the
converter output noise is dominated by thermal noise,
which is independent of the reference voltage, the
output noise is not significantly improved by
diminishing the reference voltage at the VREF input pin.
A reduced voltage reference will significantly improve
the INL performance (see Figure 2-4); the INL max
error is proportional to VREF2.
3.2
Analog Inputs (VIN+, VIN-)
The MCP3550/1/3 devices accept a fully differential
analog input voltage to be connected on the VIN+ and
VIN- input pins. The differential voltage that is
converted is defined by VIN = VIN+ – VIN-. The
differential voltage range specified for ensured
accuracy is from -VREF to +VREF. However, the
converter will still output valid and usable codes with
the inputs overranged by up to 12% (see Section 5.0
“Serial Interface”) at room temperature. This
overrange is clearly specified by two overload bits in
the output code.
The absolute voltage range on these input pins extends
from VSS – 0.3V to VDD + 0.3V. Any voltage above or
below this range will create leakage currents through
the Electrostatic Discharge (ESD) diodes. This current
will increase exponentially, degrading the accuracy and
noise performance of the device. The common mode of
the analog inputs should be chosen such that both the
differential analog input range and the absolute voltage
range on each pin are within the specified operating
range
defined
in
Section 1.0
“Electrical
Characteristics”.
© 2009 Microchip Technology Inc.
3.3
Supply Voltage (VDD, VSS)
VDD is the power supply pin for the analog and digital
circuitry within the MCP3550/1/3. This pin requires an
appropriate bypass capacitor of 0.1 µF. The voltage on
this pin should be maintained in the 2.7V to 5.5V range
for specified operation. VSS is the ground pin and the
current return path for both analog and digital circuitry
of the MCP3550/1/3. If an analog ground plane is
available, it is recommended that this device be tied to
the analog ground plane of the Printed Circuit Board
(PCB).
3.4
Serial Clock (SCK)
SCK synchronizes data communication with the
device. The device operates in both SPI mode 1,1 and
SPI mode 0,0. Data is shifted out of the device on the
falling edge of SCK. Data is latched in on the rising
edge of SCK. During CS high times, the SCK pin can
idle either high or low.
3.5
Data Output (SDO/RDY)
SDO/RDY is the output data pin for the device. Once a
conversion is complete, this pin will go active-low,
acting as a ready flag. Subsequent falling clock edges
will then place the 24-bit data word (two overflow bits
and 22 bits of data, see Section 5.0 “Serial
Interface”) on the SPI bus through the SDO pin. Data
is clocked out on the falling edge of SCK.
DS21950E-page 13
MCP3550/1/3
3.6
Chip Select (CS)
CS gates all communication to the device and can be
used to select multiple devices that share the same
SCK and SDO/RDY pins. This pin is also used to
control the internal conversions, which begin on the
falling edge of CS. Raising CS before the first internal
conversion is complete places the device in Single
Conversion mode. Leaving CS low will place the
device in Continuous Conversion mode (i.e., additional
internal conversions will automatically occur). CS may
be tied permanently low for two-wire Continuous
Conversion mode operation. SDO/RDY enters a highimpedance state with CS high.
DS21950E-page 14
© 2009 Microchip Technology Inc.
MCP3550/1/3
4.0
DEVICE OVERVIEW
The MCP3550/1/3 devices communicate with a simple
3-wire SPI interface. The interface controls the
conversion start event, with an added feature of an
auto-conversion at system power-up by tying the CS
pin to logic-low. The device can communicate with bus
speeds of up to 5 MHz, with 50 pF capacitive loading.
The interface offers two conversion modes: Single
Conversion mode for multiplexed applications and a
Continuous Conversion mode for multiple conversions
in series. Every conversion is independent of each
other. That is, all internal registers are flushed between
conversions. When the device is not converting, it automatically goes into Shutdown mode and, while in this
mode, consumes less than 1 µA.
The MCP3550/1/3 devices are 22-bit delta-sigma
ADCs that include fully differential analog inputs, a
third-order delta-sigma modulator, a fourth-order
modified SINC decimation filter, an on-chip, low-noise
internal oscillator, a power supply monitoring circuit and
an SPI 3-wire digital interface. These devices can be
easily used to measure low-frequency, low-level
signals such as those found in pressure transducers,
temperature, strain gauge, industrial control or process
control applications. The power supply range for this
product family is 2.7V to 5.5V; the temperature range is
-40°C to +125°C. The functional block diagram for the
MCP3550/1/3 devices is shown in Figure 4-1.
A Power-On Reset (POR) monitoring circuit is included
to ensure proper power supply voltages during the
conversion process. The clock source for the part is
internally generated to ±0.5% over the full-power
supply voltage range and industrial temperature range.
This stable clock source allows for superior conversion
repeatability and minimal drift across conversions.
The MCP3550/1/3 devices employ a delta-sigma
conversion technique to realize up to 22 bits of no
missing code performance with 21.9 Effective Number
of Bits (ENOB). These devices provide single-cycle
conversions with no digital filter settling time. Every
conversion includes an internal offset and gain autocalibration to reduce device error. These calibrations
are transparent to the user and are done in real-time
during the conversion. Therefore, these devices do not
require any additional time or conversion to proceed,
allowing easy usage of the devices for multiplexed
applications. The MCP3550/1/3 devices incorporate a
fourth-order digital decimation filter in order to allow
superior averaging performance, as well as excellent
line frequency rejection capabilities. The oversampling
frequency also reduces any external anti-aliasing filter
requirements.
Reference
Input
Differential
Analog Input
Gain and
Offset
Calibration
Charge
Transfer Third-Order
ΔΣ
Modulator
Bit
Stream
Digital
Decimation
Filter (SINC4)
Conversion
Code
SPI 3-wire
Interface
Output
Code
Clock
Internal
Oscillator
FIGURE 4-1:
MCP3550/1/3 Functional Block Diagram.
© 2009 Microchip Technology Inc.
DS21950E-page 15
MCP3550/1/3
4.1
MCP3550/1/3 Delta-Sigma
Modulator with Internal Offset and
Gain Calibration
4.2
The MCP3550/1/3 devices include a digital decimation
filter, which is a fourth-order modified SINC filter. This
filter averages the incoming bit stream from the
modulator and outputs a 22-bit conversion word in
binary two's complement. When all bits have been
processed by the filter, the output code is ready for SPI
communication, the RDY flag is set on the SDO/RDY
pin and all the internal registers are reset in order to
process the next conversion.
The converter core of the MCP3550/1/3 devices is a
third-order delta-sigma modulator with automatic gain
and offset error calibrations. The modulator uses a 1-bit
DAC structure. The delta-sigma modulator processes
the sampled charges through switched capacitor
structures controlled by a very low drift oscillator for
reduced clock jitter.
Like the commonly used SINC filter, the modified SINC
filter in the MCP3550/1/3 family has the main notch
frequency located at fS/(OSR*L), where fS is the bit
stream sample frequency. OSR is the Oversampling
Ratio and L is the order of the filter.
During the conversion process, the modulator outputs
a bit stream with the bit frequency equivalent to the
fOSC/4 (see Table 4-1). The high oversampling
implemented in the modulator ensures very high
resolution and high averaging factor to achieve lownoise specifications. The bit stream output of the
modulator is then processed by the digital decimation
filter in order to provide a 22-bit output code at a data
rate of 12.5 Hz for the MCP3550-50, 15 Hz for the
MCP3550-60, 13.75 Hz for the MCP3551 and 60 Hz
for the MCP3553. Since the oversampling ratio is lower
with the MCP3553 device, a much higher output data
rate is achieved while still achieving 20 bits No Missing
Codes (NMC) and 20.6 ENOB.
The MCP3550-50 device has the main filter notch
located at 50 Hz. For the MCP3550-60 device, the
notch is located at 60 Hz. The MCP3551 device has its
notch located at 55 Hz, and for the MCP3553 device,
the main notch is located at 240 Hz, with an OSR of
128. (see Table 4-1 for rejection performance).
The digital decimation SINC filter has been modified in
order to offer staggered zeros in its transfer function.
This modification is intended to widen the main notch in
order to be less sensitive to oscillator deviation or linefrequency drift. The MCP3551 filter has staggered
zeros spread in order to reject both 50 Hz and 60 Hz
line frequencies simultaneously (see Figure 4-2).
A self-calibration of offset and gain occurs at the onset
of every conversion. The conversion data available at
the output of the device is always calibrated for offset
and gain through this process. This offset and gain
auto-calibration is performed internally and has no
impact on the speed of the converter since the offset
and gain errors are calibrated in real-time during the
conversion. The real-time offset and gain calibration
schemes do not affect the conversion process.
TABLE 4-1:
Digital Filter
DATA RATE, OUTPUT NOISE AND DIGITAL FILTER SPECIFICATIONS BY DEVICE
Output Data
Rate (tCONV)
(Note)
Output
Noise
(µVRMS)
Primary
Notch
(Hz)
Sample
Frequency
(fS)
Internal
Clock
fOSC
MCP3550-50
80.00 ms
2.5
50
25600 Hz
102.4 kHz
-120 dB min. at
50 Hz
MCP3550-60
66.67 ms
2.5
60
30720 Hz
122.88 kHz
-120 dB min. at
60 Hz
MCP3551
72.73 ms
2.5
55
28160 Hz
112.64 kHz
-82 dB min. from
48 Hz to 63 Hz. 82 dB at 50 Hz and
-88 dB at 60 Hz
MCP3553
16.67 ms
6
240
30720 Hz
122.88 kHz
Not Applicable
Device
Note:
50/60 Hz Rejection
For the first conversion after exiting Shutdown, tCONV must include an additional 144 fOSC periods before
the conversion is complete and the RDY (Ready) flag appears on SDO/RDY.
DS21950E-page 16
© 2009 Microchip Technology Inc.
MCP3550/1/3
0
0
-20
-20
Normal Mode Rejection (dB)
Attenuation (dB)
:
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
50
100
150
200
-140
0
Frequency (Hz)
28160
56320
84480 112640 140800 168960 197120 225280 253440
Frequency (Hz)
FIGURE 4-5:
SINC Filter Response at
Integer Multiples of the Sampling Frequency (fs).
FIGURE 4-2:
SINC Filter Response,
MCP3550-50 Device.
:
4.3
0
The MCP3550/1/3 devices include a highly stable and
accurate internal oscillator that provides clock signals
to the delta-sigma ADC with minimum jitter. The
oscillator is a specialized structure with a low
temperature coefficient across the full range of
specified operation. See Table 4-1 for oscillator
frequencies.
Attenuation (dB)
-20
-40
-60
-80
-100
-120
0
60
120
180
240
Frequency (Hz)
FIGURE 4-3:
SINC Filter Response,
MCP3550-60 Device.
:
Attenuation (dB)
Internal Oscillator
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
10 20 30 40 50 60 70 80 90 100 110
Frequency (Hz)
FIGURE 4-4:
SINC Filter Response,
MCP3551 Device, Simultaneous 50/60 Hz
Rejection.
© 2009 Microchip Technology Inc.
The conversion time is an integer multiple of the
internal clock period and, therefore, has the same
accuracy as the internal clock frequency. The internal
oscillator frequency is 102.4 kHz ±1% for the
MCP3550-50, 112.64 kHz ±1% for the MCP3551, and
122.88 kHz ±1% for the MCP3550-60 and MCP3553
devices, across the full power supply voltage and
specified temperature ranges.
The notch of the digital filter is proportional to the
internal oscillator frequency, with the exact notch
frequency equivalent to the oscillator accuracy
(< 1% deviation). This high accuracy, combined with
wide notches, will ensure that the MCP3551 will have
simultaneous 50 Hz and 60 Hz line frequency rejection
and the MCP3550-50 or MCP3550-60 devices will
have greater than 120 dB rejection (at either 50 or
60 Hz) by the digital filtering, even when jitter is
present.
The internal oscillator is held in the reset condition
when the part is in Shutdown mode to ensure very low
power consumption (< 1 µA in Shutdown mode). The
internal oscillator is independent of all serial digital
interface edges (i.e., state machine processing the
digital SPI interface is asynchronous with respect to the
internal clock edges).
DS21950E-page 17
MCP3550/1/3
4.4
Differential Analog Inputs
The MCP3550/1/3 devices accept a fully differential
analog input voltage to be connected to the VIN+ and
VIN- input pins. The differential voltage that is converted
is defined by VIN = VIN+ – VIN-. The differential voltage
range specified for ensured accuracy is from -VREF to
+VREF.
The converter will output valid and usable codes from
-112% to 112% of output range (see Section 5.0
“Serial Interface”) at room temperature. The ±12%
overrange is clearly specified by two overload bits in
the output code: OVH and OVL. This feature allows for
system calibration of a positive gain error.
The absolute voltage range on these input pins extends
from VSS - 0.3V to VDD + 0.3V. If the input voltages are
above or below this range, the leakage currents of the
ESD diodes will increase exponentially, degrading the
accuracy and noise performance of the converter. The
common mode of the analog inputs should be chosen
such that both the differential analog input range and
absolute voltage range on each pin are within the
specified operating range defined in Section 1.0
“Electrical Characteristics”.
Both the analog differential inputs and the reference
input have switched-capacitor input structures. The
input capacitors are charged and discharged
alternatively with the input and the reference in order to
process a conversion. The charge and discharge of the
input capacitors create dynamic input currents at the
VIN+ and VIN- input pins inversely proportional to the
sampling capacitor. This current is a function of the
differential input voltages and their respective common
modes. The typical value of the differential input
impedance is 2.4 MΩ, with VCM = 2.5V, VDD = VREF =
5V. The DC leakage current caused by the ESD input
diodes, even though on the order of 1 nA, can cause
additional offset errors proportional to the source
resistance at the VIN+ and VIN- input pins.
From a transient response standpoint and as a firstorder approximation, these input structures form a
simple RC filtering circuit with the source impedance in
series with the RON (switched resistance when closed)
of the input switch and the sampling capacitor. In order
to ensure the accuracy of the sampled charge, proper
settling time of the input circuit has to be considered.
Slow settling of the input circuit will create additional
gain error. As a rule of thumb, in order to obtain 1 ppm
absolute measurement accuracy, the sampling period
must be 14 times greater than the input circuit RC time
constant.
DS21950E-page 18
4.5
Voltage Reference Input Pin
The MCP3550/1/3 devices accept a single-ended
external reference voltage, to be connected on the
VREF input pin. Internally, the reference voltage for the
ADC is a differential voltage with the non-inverting input
connected to the VREF pin and the inverting input
connected to the VSS pin. The value of the reference
voltage is VREF - VSS and the common mode of the
reference is always (VREF - VSS)/2.
The MCP3550/1/3 devices accept a single-ended
reference voltage from 0.1V to VDD. The converter
output noise is dominated by thermal noise that is
independent of the reference voltage. Therefore, the
output noise is not significantly improved by lowering
the reference voltage at the VREF input pin. However, a
reduced reference voltage will significantly improve the
INL performance since the INL max error is
proportional to VREF2 (see Figure 2-4).
The charge and discharge of the input capacitor create
dynamic input currents at the VREF input pin inversely
proportional to the sampling capacitor, which is a function of the input reference voltage. The typical value of
the single-ended input impedance is 2.4 MΩ, with
VDD = VREF = 5V. The DC leakage current caused by
the ESD input diodes, though on the order of 1 nA
typically, can cause additional gain error proportional to
the source resistance at the VREF pin.
4.6
Power-On Reset (POR)
The MCP3550/1/3 devices contain an internal PowerOn Reset (POR) circuit that monitors power supply
voltage VDD during operation. This circuit ensures
correct device start-up at system power-up and powerdown events. The POR has built-in hysteresis and a
timer to give a high degree of immunity to potential
ripple and noise on the power supplies, as well as to
allow proper settling of the power supply during powerup. A 0.1 µF decoupling capacitor should be mounted
as close as possible to the VDD pin, providing additional
transient immunity.
The threshold voltage is set at 2.2V, with a tolerance of
approximately ±5%. If the supply voltage falls below
this threshold, the MCP3550/1/3 devices will be held in
a reset condition or in Shutdown mode. When the part
is in Shutdown mode, the power consumption is less
than 1 µA. The typical hysteresis value is around
200 mV in order to prevent reset during brown-out or
other glitches on the power supply.
© 2009 Microchip Technology Inc.
MCP3550/1/3
Once a power-up event has occurred, the device must
require additional time before a conversion can take
place. During this time, all internal analog circuitry must
settle before the first conversion can occur. An internal
timer counts 32 internal clock periods before the
internal oscillator can provide clock to the conversion
process. This allows all internal analog circuitry to
settle to their proper operating point. This timing is
typically less than 300 µs, which is negligible compared
to one conversion time (e.g. 72.7 ms for the
MCP3551). Figure 4-6 illustrates the conditions for a
power-up and power-down event under typical start-up
conditions.
4.8
Sleep Mode
During Sleep mode, the device is not converting and is
awaiting data retrieval; the internal analog circuitry is
still running and the device typically consumes 10 µA.
In order to restart a conversion while in Sleep mode,
toggling CS to a logic-high (placing the part in Shutdown mode) and then back to a logic-low will restart the
conversion. Sleep can only be entered in Single
Conversion mode. Once a conversion is complete in
Single Conversion mode, the device automatically
enters Sleep mode.
VDD
2.2V
2.0V
300 µs
0V
Reset
FIGURE 4-6:
4.7
Start-up
Normal
Operation
Time
Reset
Power-On Reset Operation.
Shutdown Mode
When not internally converting, the two modes of
operation for the MCP3550/1/3 devices are the
Shutdown and Sleep modes. During Shutdown mode,
all internal analog circuitry, including the POR, is turned
off and the device consumes less than 1 µA. When
exiting Shutdown mode, the device must require
additional time before a conversion can take place.
During this time, all internal analog circuitry must settle
before the first conversion can occur. An internal timer
counts 32 internal clock periods before the internal
oscillator can provide clock to the conversion process.
This allows all internal analog circuitry to settle to their
proper operating point. This timing is typically less than
300 µs, which is negligible compared to one conversion
time (72.7 ms for MCP3551).
© 2009 Microchip Technology Inc.
DS21950E-page 19
MCP3550/1/3
NOTES:
DS21950E-page 20
© 2009 Microchip Technology Inc.
MCP3550/1/3
5.0
SERIAL INTERFACE
5.1
Overview
Serial communication between the microcontroller and
the MCP3550/1/3 devices is achieved using CS, SCK
and SDO/RDY. There are two modes of operation:
Single Conversion and Continuous Conversion. CS
controls the conversion start. There are 24 bits in the
data word: 22 bits of conversion data and two overflow
bits. The conversion process takes place via the
internal oscillator and the status of this conversion
must be detected. The typical method of
communication is shown in Figure 5-1. The status of
the internal conversion is the SDO/RDY pin and is
available with CS low. A High state on SDO/RDY
means the device is busy converting, while a Low
state means the conversion is finished and data is
ready for transfer using SCK. SDO/RDY remains in a
high-impedance state when CS is held high. CS must
be low when clocking out the data using SCK and
SDO/RDY.
Bit 22 is Overflow High (OVH) when VIN > VREF – 1 LSB,
OVH toggles to logic ‘1’, detecting an overflow high in
the analog input voltage.
Bit 23 is Overflow Low (OVL) when VIN < -VREF, OVL
toggles to logic ‘1’, detecting an overflow low in the
analog input voltage. The state OVH = OVL = ‘1’ is not
defined and should be considered as an interrupt for
the SPI interface meaning erroneous communication.
Bit 21 to bit 0 represents the output code in 22-bit
binary two's complement. Bit 21 is the sign bit and is
logic ‘0’ when the differential analog input is positive
and logic ‘1’ when the differential analog input is
negative. From Bit 20 to bit 0, the output code is given
MSb first (MSb is bit 20 and LSB is Bit 0). When the
analog input value is comprised between -VREF and
VREF – 1 LSB, the two overflow bits are set to logic ‘0’.
The relationship between input voltage and output
code is shown in Figure 5-1.
The delta-sigma modulator saturation point for the
differential analog input is located at around ±112% of
VREF (at room temperature), meaning that the
modulator will still give accurate output codes with an
overrange of 12% below or above the reference
voltage. Unlike the usual 22-bit device, the 22-bit output code will not lock at 0x1FFFFF for positive sign
inputs or 0x200000 for negative sign inputs in order to
take advantage of the overrange capabilities of the
device. This can be practical for closed-loop
operations, for instance. In case of an overflow, the
output code becomes a 23-bit two's complement output
code, where the sign bit will be the OVL bit. If an
overflow high or low is detected, OVL (bit 23) becomes
the sign bit (instead of bit 21), the MSb is then bit 21
and the converter can be used as a 23-bit two's
complement code converter, with output code from bits
B21 to B0, and OVL as the sign bit. Figure 5-1
summarizes the output coding data format with or
without overflow high and low.
CS
SCK
SDO/RDY
READY
D
R
O O
21 20 19 18 17
L H
16
15 14 13 12 11 10 9
8
7 6 5 4 3
2 1
0
HI-Z
FIGURE 5-1:
Typical Serial Device Communication and Example Digital Output Codes for Specific
Analog Input Voltages.
© 2009 Microchip Technology Inc.
DS21950E-page 21
MCP3550/1/3
5.2
Controlling Internal Conversions
and the Internal Oscillator
During Shutdown mode, on the falling edge of CS, the
conversion process begins. During this process, the
internal oscillator clocks the delta-sigma modulator and
the SINC filter until a conversion is complete. This
conversion time is tCONV and the timing is shown in
Figure 5-2. At the end of tCONV, the digital filter has
settled completely and there is no latency involved with
the digital SINC filter of the MCP3550/1/3.
In Continuous Conversion mode, a consecutive
conversion will be automatic. In this mode, the device
is continuously converting, independent of the serial
interface. The most recent conversion data will always
be available in the Output register.
When the device exits Shutdown, there is an internal
power-up delay that must be observed.
The two modes of conversion for the MCP3550/1/3
devices are Single Conversion and Continuous
Conversion. In Single Conversion mode, a consecutive
conversion will not automatically begin. Instead, after a
single conversion is complete and the SINC filter have
settled, the device puts the data into the output register
and enters shutdown.
CS
Int. Osc
tCONV
Shutdown
Sleep
SCK (opt)
x24
FIGURE 5-2:
Hi-Z
Hi-Z
SDO/RDY
Single Conversion Mode.
CS
Shutdown
Int. Osc
tCONV
tCONV
SCK (opt)
x24
Hi-Z
SDO/RDY
FIGURE 5-3:
DS21950E-page 22
tCONV
Continuous Conversion Mode.
© 2009 Microchip Technology Inc.
MCP3550/1/3
5.3
Single Conversion Mode
If a rising edge of Chip Select (CS) occurs during tCONV,
a subsequent conversion will not take place and the
device will enter low-power Shutdown mode after
tCONV completes. This is referred to as Single
Conversion mode. This operation is demonstrated in
Figure 5-2. Note that a falling edge of CS during the
same conversion that detected a rising edge, as in
Figure 5-2, will not initiate a new conversion. The data
must be read during sleep mode, with CSN low, and will
be lost as soon as the part enters in shutdown mode
(with a rising edge of CSN). After the final data bit has
been clocked out on the 25th clock, the SDO/RDY pin
will go active-high.
5.3.1
READY FUNCTION OF SDO/RDY
PIN, SINGLE CONVERSION MODE
At every falling edge of CS during the internal
conversion, the state of the internal conversion is
latched on the SDO/RDY pin to give ready or busy
information. A High state means the device is currently
performing an internal conversion and data cannot be
clocked out. A Low state means the device has finished
its conversion and the data is ready for retrieval on the
falling edge of SCK. This operation is demonstrated in
Figure 5-4. Note that the device has been put into
Single Conversion mode with the first rising edge of
CS.
Note:
The Ready state is latched on each falling
edge of CS and will not dynamically
update if CS is held low. CS must be
toggled high through low.
CS
Continuous Conversion Mode
If no rising edge of CS occurs during any given
conversion per Figure 5-3, a subsequent conversion
will take place and the contents of the previous conversion will be overwritten. This operation is demonstrated
in Figure 5-5. Once conversion output data has started
to be clocked out, the output buffer is not refreshed until
all 24 bits have been clocked. A complete read must
occur in order to read the next conversion in this mode.
The subsequent conversion data to be read will then be
the most recent conversion. The conversion time is
fixed and cannot be shortened by the rising edge of CS.
This rising edge will place the part in Shutdown mode
and all conversion data will be lost.
The transfer of data from the SINC filter to the output
buffer is demonstrated in Figure 5-5. If the previous
conversion data is not clocked out of the device, it will
be lost and replaced by the new conversion. When the
device is in Continuous Conversion mode, the most
recent conversion data is always present at the output
register for data retrieval.
CS
Int. Osc
tCONV
A
tCONV
tCONV
B
C
SCK & SDO/RDY
Conversion B data is clocked
out of the device here.
FIGURE 5-5:
Most Current Continuous
Conversion Mode Data.
If a conversion is in process, it cannot be terminated
with the rising edge of CS. SDO/RDY must first
transition to a Low state, which will indicate the end of
conversion.
Int. Osc
tCONV
SDO/RDY
5.4
Hi-Z
FIGURE 5-4:
RDY Functionality in Single
Conversion Mode.
© 2009 Microchip Technology Inc.
DS21950E-page 23
MCP3550/1/3
5.4.1
READY FUNCTION OF SDO/RDY
PIN IN CONTINUOUS CONVERSION
MODE
The device enters Continuous Conversion mode if no
rising edge of CS is seen during tCONV and
consecutive conversions ensue. SDO/RDY will be
high, indicating that a conversion is in process. When
a conversion is complete, SDO/RDY will change to a
Low state. With the Low state of SDO/RDY after this
first conversion, the conversion data can be accessed
with the combination of SCK and SDO/RDY. If the data
ready event happens during the clocking out of the
data, the data ready bit will be displayed after the
complete 24-bit word communication (i.e., the data
ready event will not interrupt a data transfer).
5.4.2
2-WIRE CONTINUOUS
CONVERSION OPERATION,
(CS TIED PERMANENTLY LOW)
It is possible to use only two wires to communicate with
the MCP3550/1/3 devices. In this state, the device is
always in Continuous Conversion mode, with internal
conversions continuously occurring. This mode can be
entered by having CS low during power-up or changing
it to a low position after power-up. If CS is low at powerup, the first conversion of the converter is initiated
approximately 300 µs after the power supply has
stabilized.
If 24 bits of data are required from this conversion, they
must be accessed during this communication. You can
terminate data transition by bringing CS high, but the
remaining data will be lost and the converter will go into
Shutdown mode. Once the data has been transmitted
by the converter, the SDO/RDY pin will remain in the
LSB state until the 25th falling edge of SCK. At this
point, SDO/RDY is released from the Data Acquisition
mode and changed to the RDY state.
Note:
The RDY state is not latched to CS in this
mode; the RDY flag dynamically updates
on the SDO/RDY pin and remains in this
state until data is clocked out using the
SCK pin.
DS21950E-page 24
© 2009 Microchip Technology Inc.
MCP3550/1/3
5.5
Using The MCP3550/1/3 with
Microcontroller (MCU) SPI Ports
It is required that the microcontroller SPI port be
configured to clock out data on the falling edge of clock
and latch data in on the rising edge. Figure 5-6 depicts
the operation shown in SPI mode 1,1, which requires
that the SCK from the MCU idles in the High state,
while Figure 5-7 shows the similar case of SPI Mode
0,0, where the clock idles in the Low state. The
waveforms in the figures are examples of an MCU
operating the SPI port in 8-bit mode, and the
MCP3550/1/3 devices do not require data in 8-bit
groups.
In SPI mode 1,1, data is read using only 24 clocks or
three byte transfers. The data ready bit must be read
by testing the SDO/RDY line prior to a falling edge of
the clock.
In SPI mode 0,0, data is read using 25 clocks or four
byte transfers. Please note that the data ready bit is
included in the transfer as the first bit in this mode.
CS
SCK
SDO/RDY
MCU
Receive
Buffer
D
R
O O
21 20 19 18 17
H L
OL OH 21 20 19 18 17 16
Data stored into MCU
receive
register
after
transmission of first byte
FIGURE 5-6:
16
7 6 5 4 3 2 1
8
15 14 13 12 11 10 9
15 14 13 12 11 10 9
7
8
6
5
4
3
2
1
0
0
Data stored into MCU
receive
register
after
transmission of third byte
Data stored into MCU
receive
register
after
transmission of second byte
SPI Communication – Mode 1,1.
CS
SCK
SDO/RDY
MCU
Receive
Buffer
DR
O O
21 20 19 18 17
H L
16
15 14 13 12 11 10 9
DR OH OL 21 20 19 18 17
16 15 14 13 12 11 10 9
Data stored into MCU
receive
register
after
transmission of first byte
Data stored into MCU
receive
register
after
transmission of second byte
FIGURE 5-7:
7 6 5 4 3 2 1
8
8
7
6
5
4
3
2
0
1
Data stored into MCU
receive
register
after
transmission of third byte
0
Data stored into MCU
receive
register
after
transmission of fourth byte
SPI Communication – Mode 0,0.
© 2009 Microchip Technology Inc.
DS21950E-page 25
MCP3550/1/3
NOTES:
DS21950E-page 26
© 2009 Microchip Technology Inc.
MCP3550/1/3
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
8-Lead MSOP
XXXXXX
3553E
YWWNNN
951256
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
Example (MCP3550):
3550-50E
e3 0951
SN^^
256
Example (MCP3551):
MCP3551E
e3 0951
SN^^
256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS21950E-page 27
MCP3550/1/3
1
%&
%!%2") ' %
2$%
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&32
D
N
E
E1
NOTE 1
1
2
e
b
A2
A
c
φ
L
L1
A1
4%
& 5&%
6!&(
$
55**
6
6
67
8
9
%
7;%
<
:+./
<
""22
+
9+
+
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$$
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+
7="%
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75%
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1
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5
1
%%
5
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:
9
+*1
1
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9>
5"2
9
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5"="%
(
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%")%%%"
& "*"
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, & "%
*-+
./0 . & %#%! ))%
!%%
*10 $& '! !)%
!%%
'$
$
&%
!
) /.
DS21950E-page 28
© 2009 Microchip Technology Inc.
MCP3550/1/3
!"#$%&'()
1
%&
%!%2") ' %
2$%
%"%
%%033)))&
&32
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
A2
A
c
φ
L
A1
L1
4%
& 5&%
6!&(
$
β
55**
6
6
67
8
9
%
7;%
<
./
<
""22
+
<
<
%"
$$?
<
+
7="%
*
""2="%
*
,./
75%
./
+
:./
/&[email protected]
%
A
+
<
+
1
%5%
5
<
1
%%
5
*1
1
%
>
<
9>
5"2
<
+
5"="%
(
,
<
+
"$%
+>
<
+>
"$%.
%%
&
+>
<
+>
!"#$%!&'(!%&! %(
%")%%%"
?$%/% %
, & "*"
%!"&
"$ %! "$ %! %#"+&& "
& "%
*-+
./0 . & %#%! ))%
!%%
*10 $& '! !)%
!%%
'$
$
&%
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© 2009 Microchip Technology Inc.
DS21950E-page 29
MCP3550/1/3
!"#$%&'()
1
%&
%!%2") ' %
2$%
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&32
DS21950E-page 30
© 2009 Microchip Technology Inc.
MCP3550/1/3
APPENDIX A:
REVISION HISTORY
Revision E (April 2009)
The following is the list of modifications:
1.
2.
3.
Numerous changes made throughout document. Too numerous to itemize.
DC Characteristics Table, Conversion Times:
Changed all minimums from -1.0% to -2.0%.
Changed typical for MCP3551 from 72.73 to
73.1. Changed all maximums from +1.0% to
+2.0%.
Packaging Outline drawings updated..
Revision D (January 2007)
The following is the list of modifications:
• This update includes revisions to the packaging
diagrams.
Revision C (December 2005)
The following is the list of modifications:
• Added MCP3550-50, MCP3550-60 references
throughout this document.
Revision B (October 2005)
The following is the list of modifications:
• Changed LSb refefences to LSB.
Revision A (September 2005)
• Original Release of this Document.
© 2009 Microchip Technology Inc.
DS21950E-page 31
MCP3550/1/3
NOTES:
DS21950E-page 32
© 2009 Microchip Technology Inc.
MCP3550/1/3
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device:
PART NO.
–X
/XX
Device
Temperature
Range
Package
MCP3550-50: Single Channel 22-Bit Delta-Sigma ADC
MCP3550T-50: Single Channel 22-Bit Delta-Sigma ADC
(Tape and Reel)
MCP3550-60: Single Channel 22-Bit Delta-Sigma ADC
MCP3550T-60: Single Channel 22-Bit Delta-Sigma ADC
(Tape and Reel)
MCP3551:
Single Channel 22-Bit Delta-Sigma ADC
MCP3551T:
Single Channel 22-Bit Delta-Sigma ADC
(Tape and Reel)
MCP3553:
Single Channel 22-Bit Delta-Sigma ADC
MCP3553T:
Single Channel 22-Bit Delta-Sigma ADC
(Tape and Reel)
Temperature Range: E
Package:
= -40°C to +125°C
MS = Plastic MSOP, 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
© 2009 Microchip Technology Inc.
Examples:
a)
b)
c)
d)
MCP3550-50E/MS:
Extended Temp.,
8LD MSOP.
MCP3550T-50E/MS: Tape and Reel,
Extended Temp.,
8LD MSOP.
MCP3550-60E/SN: Extended Temp.,
8LD SOIC.
MCP3550T-60E/SN: Tape and Reel,
Extended Temp.,
8LD SOIC.
a)
MCP3551-E/MS:
b)
MCP3551T-E/MS:
a)
MCP3553-E/SN:
b)
MCP3553T-E/SN:
Extended Temp.,
8LD MSOP.
Tape and Reel,
Extended Temp.,
8LD MSOP.
Extended Temp.,
8LD SOIC.
Tape and Reel,
Extended Temp.,
8LD SOIC.
DS21950E-page 33
MCP3550/1/3
NOTES:
DS21950E-page 34
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS21950E-page 35
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ASIA/PACIFIC
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EUROPE
Corporate Office
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Tel: 480-792-7200
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Technical Support:
http://support.microchip.com
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Thailand - Bangkok
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03/26/09
DS21950E-page 36
© 2009 Microchip Technology Inc.