MICROCHIP MCP3909

MCP3909
Energy Metering IC with SPI Interface and Active Power Pulse Output
Features
Description
• Supports IEC 62053 International Energy
Metering Specification and legacy IEC 1036/
61036/687 Specifications
• Digital waveform data access through SPI
interface
- 16-bit Dual ADC output data words
- 20-bit Multiplier output data word
• Dual functionality pins support serial interface
access and simultaneous Active Power Pulse
Output
• Two 16-bit second order delta-sigma Analog-toDigital Converters (ADCs) with multi-bit DAC
- 81 dB SINAD (typ.) both channels
• 0.1% typical active energy measurement error
over 1000:1 dynamic range
• PGA for small signal inputs supports low value
shunt current sensor
• Ultra-low drift on-chip reference: 15 ppm/°C (typ.)
• Direct drive for electromagnetic mechanical
counter and two-phase stepper motors
• Low IDD of 4 mA (max.)
• Tamper output pin for negative power indication
• Industrial Temperature Range: -40°C to +85°C
The MCP3909 device is an energy-metering IC
designed to support the IEC 62053 international
metering standard specification. It supplies a frequency
output proportional to the average active real power,
with simultaneous serial access to ADC channels and
multiplier output data. This output waveform data is
available at up to 14 kHz with 16-bit ADC output and
20-bit multiplier output words. The 16-bit, delta-sigma
ADCs allow for a wide range of IB and IMAX currents
and/or small shunt (<200 µOhms) meter designs. A noload threshold block prevents any current creep
measurements for the active power pulse outputs. The
integrated on-chip voltage reference has an ultra-low
temperature drift of 15 ppm per degree C.This accurate
energy metering IC with high field reliability is available
in the industry standard 24-lead SSOP pinout.
Package Type
24-Lead
SSOP
DVDD
HPF
AVDD
NC
CH0+
CHOCH1CH1+
MCLR
REFIN / OUT
AGND
F2 / SCK
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
FOUT0
FOUT1
HFOUT
DGND
NEG / SDO
NC
9
10
11
16
15
14
G0
12
13
F1 / SDI
CLKOUT
CLKIN
G1
F0 / CS
Functional Block Diagram
HPF
G0 G1
F2/SCK F1/SDI F0/CS NEG/SDO
CH0+
+
PGA
–
CH0-
16-bit
Multi-level
ΔΣ ADC
4 kΩ
16
HPF1
MCLR
16
Serial Control
And Output
Buffers
REFIN/
OUT
2.4V
Reference
CH1+
+
–
CH1-
16
16-bit
Multi-level
ΔΣ ADC
HFOUT
FOUT0 FOUT1
Active Power
DTF
conversion
Stepper
Motor
Output Drive
for
Active Power
20
X
© 2006 Microchip Technology Inc.
SPI
Interface
16
HPF1
Clock
Sub-system
OSC1 OSC2
Dual Functionality Pin
Control
LPF1
DS22025A-page 1
MCP3909
1.0
ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings †
VDD ...................................................................................7.0V
Digital inputs and outputs w.r.t. AGND ........ -0.6V to VDD +0.6V
Analog input w.r.t. AGND ..................................... ....-6V to +6V
VREF input w.r.t. AGND ............................... -0.6V to VDD +0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) .................4.0 kV, 400V
ESD on all other pins (HBM,MM) ........................4.0 kV, 400V
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V to 5.5V,
Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter
Sym
Min
Typ.
Max
Units
Comment
E
—
0.1
—
% FOUT Channel 0 swings 1000:1 range,
FOUT0, FOUT1 Frequency outputs
only, does not apply to serial interface data. (Note 1, Note 4)
NLT
—
0.0015
—
% FOUT Frequency outputs only, does not
Max
apply to serial interface data.
Disabled when F2, F1, F0 = 0, 1, 1
(Note 5, Note 6)
—
1
5
% FOUT (Note 2, Note 5)
AC Power Supply Rejection
(output frequency variation)
AC PSRR
—
0.01
—
% FOUT F2, F1, F0 = 0, 1, 1 (Note 3)
DC Power Supply Rejection
DC PSRR
—
0.01
—
% FOUT HPF = 1, Gain = 1 (Note 3)
SINAD
—
81
—
dB
Applies to both channels,
VIN = 0 dBFS at 50 Hz
(VIN = Full Scale)
Bandwidth
(Notch Frequency)
—
14
—
kHz
Applies to both channels,
MCLK/256
Phase Delay Between
Channels
—
—
1/MCLK
s
Active Power Measurement Accuracy
Active Energy Measurement
Error
No-Load Threshold/
Minimum Load
System Gain Error
(output frequency
variation)
Waveform Sampling
A/D Converter Signal-toNoise and Distortion Ratio
Note 1:
2:
3:
4:
5:
6:
7:
HPF = 0 and 1, < 1 MCLK period
(Note 4, Note 6, Note 7)
Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is
measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 75 Hz.
See typical performance curves for higher frequencies and increased dynamic range.
Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between
measured output frequency and expected transfer function.
Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @ 50 Hz,
CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV
Error applies down to 60 degree lead (PF = 0.5 capacitive) and 60 degree lag (PF = 0.5 inductive).
Refer to Section 4.0 “Device Overview” for complete description.
Specified by characterization, not production tested.
1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz.
DS22025A-page 2
© 2006 Microchip Technology Inc.
MCP3909
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V to 5.5V,
Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter
Sym
Min
Typ.
Max
Units
VOS
—
2
5
mV
—
0.5
—
Voltage
—
2.4
—
V
Tolerance
—
±2
—
%
Tempco
—
15
—
ppm/°C
Input Range
2.2
—
2.6
V
Input Impedance
3.2
—
—
kΩ
Input Capacitance
—
—
10
pF
Maximum Signal Level
—
—
±1
V
Differential Input Voltage
Range Channel 0
—
—
±470/G
mV
Differential Input Voltage
Range Channel 1
—
—
±660
mV
390
—
—
kΩ
1
—
4
MHz
4.5
—
5.5
V
Comment
ADC/PGA Specifications
Offset Error
Gain Error Match
Referred to Input, applies to both
channels
% FOUT (Note 5)
Internal Voltage Reference
Reference Input
Analog Inputs
Input Impedance
CH0+,CH0-,CH1+,CH1- to AGND
G = PGA Gain on Channel 0
Proportional to 1/MCLK
Oscillator Input
Frequency Range
MCLK
Power Specifications
Operating Voltage
AVDD, DVDD
IDD,A
IDD,A
—
2.3
2.8
mA
AVDD pin only
IDD,D
IDD,D
—
0.8
1.2
mA
DVDD pin only
Note 1:
2:
3:
4:
5:
6:
7:
Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is
measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 75 Hz.
See typical performance curves for higher frequencies and increased dynamic range.
Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between
measured output frequency and expected transfer function.
Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @ 50 Hz,
CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV
Error applies down to 60 degree lead (PF = 0.5 capacitive) and 60 degree lag (PF = 0.5 inductive).
Refer to Section 4.0 “Device Overview” for complete description.
Specified by characterization, not production tested.
1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz.
© 2006 Microchip Technology Inc.
DS22025A-page 3
MCP3909
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 4.5V to 5.5V, AGND, DGND = 0V.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Conditions
Temperature Ranges
Note:
Note
The MCP3909 operates over this extended temperature range, but with reduced performance. In any case,
the Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
DS22025A-page 4
© 2006 Microchip Technology Inc.
MCP3909
TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V to 5.5V,
AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter
Sym
Min
Typ
Max
Units
Comment
FOUT0 and FOUT1 Pulse Width
(Logic Low)
tFW
—
275
—
ms
984376 MCLK periods
(Note 1)
HFOUT Pulse Width
tHW
—
90
—
ms
322160 MCLK periods
(Note 2)
Frequency Outputs
FOUT0 and FOUT1 Pulse Period
tFP
Refer to Equation 4-1
s
HFOUT Pulse Period
tHP
Refer to Equation 4-2
s
FOUT0 to FOUT1 Falling-Edge
Time
tFS2
—
0.5 tFP
—
FOUT0 to FOUT1 Minimum Separation
tFS
—
4/MCLK
—
FOUT0 and FOUT1 Output High
Voltage
VOH
4.5
—
—
V
IOH = 12 mA, DVDD = 5.0V
FOUT0 and FOUT1 Output Low
Voltage
VOL
—
—
0.5
V
IOL = 12 mA, DVDD = 5.0V
HFOUT and NEG Output High
Voltage
VOH
4.5
—
—
V
IOH = 12 mA, DVDD = 5.0V
HFOUT and NEG Output Low
Voltage
VOL
—
—
0.5
V
IOL = 12 mA, DVDD = 5.0V
High-Level Input Voltage
(All Digital Input Pins)
VIH
2.4
—
—
V
DVDD = 5.0V
Low Level Input Voltage
(All Digital Input Pins)
VIL
—
—
0.85
V
DVDD = 5.0V
Input Leakage Current
—
0.1
±1
µA
VIN = 0, VIN = DVDD
Pin Capacitance
—
—
10
pF
(Note 3)
—
MCLK/256
—
Digital I/O
Serial Interface Timings (Note 4)
Output Data Rate
fADC
—
20
MHz
Window for serial mode entry
codes
tWINDOW
—
—
8/MCLK
—
Last bit must be clocked in
before this time.
Window start time for serial
mode entry codes
tWINSET
1/MCLK
—
—
—
First bit must be clocked in
after this time.
Serial Clock High Time
tHI
10
—
40
ns
Serial Clock Low Time
tLO
30
—
20
ns
tSUCS
15
—
—
ns
tSU
10
—
—
ns
Serial Clock Frequency
CS Fall to First Rising CLK Edge
Data Input Setup Time
fCLK
Data Input Hold Time
tHD
—
—
10
ns
CS Rise to Output Disable
tDIS
—
—
150
ns
CLK Fall to Output Data Valid
tDO
—
—
30
ns
Note 1:
2:
3:
4:
VDD = 5V
If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP.
If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP. When F2, F1, F0
equals 0,1,1, the HFOUT pulse time is fixed at 64 x MCLK periods or 18 µs for MCLK = 3.58 MHz
Specified by characterization, not production tested.
Serial timings specified and production tested with 180 pF load.
© 2006 Microchip Technology Inc.
DS22025A-page 5
MCP3909
TIMING CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V to 5.5V,
AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter
Sym
Min
Typ
Max
Units
SDO Rise Time
tR
—
2
—
ns
SDO Fall Time
tF
—
2
—
ns
Note 1:
2:
3:
4:
Comment
If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP.
If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP. When F2, F1, F0
equals 0,1,1, the HFOUT pulse time is fixed at 64 x MCLK periods or 18 µs for MCLK = 3.58 MHz
Specified by characterization, not production tested.
Serial timings specified and production tested with 180 pF load.
tFP
tFW
FOUT0
tFS
tFS2
FOUT1
tHW
HFOUT
tHP
NEG
FIGURE 1-1:
Output Timings for Active Power Pulse Outputs and Negative Power Pin.
CS
tSUCS
tCLK
tHI
tLO
CLK
tSU
tHD
SDI
tDO
SDO
Hi-z
FIGURE 1-2:
DS22025A-page 6
tR
tDIS
tF
Serial Interface Timings showing Output, Rise, Hold, and CS Times.
© 2006 Microchip Technology Inc.
MCP3909
VDD
SPI Data
Output
Pin
FIGURE 1-3:
( V DD – V OL )
R = -----------------------------I OL
180 pF
( V OH )
R = -------------I OH
SPI Output Pin Loading Circuit During SPI Testing.
© 2006 Microchip Technology Inc.
DS22025A-page 7
MCP3909
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
1
0.8
0.6
0.4
0.2 +25°C
0
-0.2
-0.4
-0.6
-0.8
-1
0.0000
Measurement Error (%)
Measurement Error (%)
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz, CH1 input = 660 mVP-P at 50 Hz, CH0 amplitude sweeps at 50 Hz.
+85°C
-40°C
0.0001
`
0.0010
0.0100
0.1000
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0000
CH0 Vp-p Amplitude (V)
+25°C
- 40°C
0.0010
0.0100
0.1000
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0000
+85°C
- 40°C
0.0100
0.1000
+25°C
1.0000
CH0 Vp-p Amplitude (V)
FIGURE 2-3:
Active Power Measurement
Error (Gain = 2, PF = 1).
DS22025A-page 8
0.0010
0.0100
0.1000
+85°C
+25°C
-40°C
0.0001
0.0010
0.0100
0.1000
FIGURE 2-5:
Active Power Measurement
Error (Gain = 16, PF = 0.5).
Measurement Error (%)
Measurement Error (%)
FIGURE 2-2:
Active Power Measurement
Error (Gain = 16, PF = 1).
0.0010
0.0001
CH0 Vp-p Amplitude (V)
CH0 Vp-p Amplitude (V)
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0001
-40°C
FIGURE 2-4:
Active Power Measurement
Error (Gain = 8, PF = 0.5).
Measurement Error (%)
Measurement Error (%)
+85°C
0.0001
+25°C
CH0 Vp-p Amplitude (V)
FIGURE 2-1:
Active Power Measurement
Error (Gain = 8 PF = 1).
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0000
+85°C
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0001
+85°C
+25°C
-40°C
0.0010
0.0100
0.1000
1.0000
CH0 Vp-p Amplitude (V)
FIGURE 2-6:
Active Power Measurement
Error (Gain =2, PF = 0.5).
© 2006 Microchip Technology Inc.
MCP3909
3000
16384 Samples
Mean = -1.20 mV
Std. Dev. = 25.1 µV
2500
+85°C
+25°C
- 40°C
2000
1500
1000
500
-1.11
-1.13
-1.16
-1.18
CH0 Vp-p Amplitude (V)
-1.20
1.0000
-1.22
0.1000
-1.25
0.0100
-1.27
0
0.0010
-1.30
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0001
Occurance
Measurement Error (%)
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz, CH1 input = 660 mVP-P at 50 Hz, CH0 amplitude sweeps at 50 Hz.
Bin (mV)
FIGURE 2-7:
Active Power Measurement
Error (Gain = 1, PF = 1).
FIGURE 2-10:
Channel 0 Offset Error
(DC Mode, HPF off, G = 2, PF = 1).
1200
1000
+85°C
+25°C
-40°C
800
16384 Samples
Mean = -1.65 mV
Std. Dev = 16.99 µV
600
400
200
FIGURE 2-8:
Active Power Measurement
Error (Gain = 1, PF = 0.5).
-1.59
-1.60
-1.61
-1.62
FIGURE 2-11:
Channel 0 Offset Error
(DC Mode, HPF off, G = 8, PF = 1).
600
3000
16,384 Samples
Mean = -1.62 mV
Std. Dev = 54.6 µV
500
Occurance
Occurance
-1.64
Bin (mV)
CH0 Vp-p Amplitude (V)
2500
-1.65
-1.66
1.0000
-1.67
0.1000
-1.68
0.0100
-1.69
0.0010
-1.70
0
-1.72
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0001
Occurance
Measurement Error (%)
L
2000
1500
1000
16384 Samples
Mean = - 17.91 mV
Std. Dev = - 1.22 µV
400
300
200
100
500
0
-1.77
-1.68
-1.59
-1.50
Bin (mV)
FIGURE 2-9:
Channel 0 Offset Error
(DC Mode, HPF off, G = 1, PF = 1).
© 2006 Microchip Technology Inc.
0
-1.30
-1.25
-1.23
-1.20
-1.17
Bin (mV)
FIGURE 2-12:
Channel 0 Offset Error
(DC Mode, HPF Off, G = 16, PF = 1).
DS22025A-page 9
MCP3909
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz, CH1 input = 660 mVP-P at 50 Hz, CH0 amplitude sweeps at 50 Hz.
0.3
0.2
Measurement Error (%)
Measurement Error (%)
0.3
0.25
VDD=5.0V
0.15
0.1
VDD=4.5V
0.05
VDD=5.25V
0
VDD=4.75V
-0.05
VDD=5.5V
-0.1
-0.15
0.0001
0.0010
0.0100
0.1000
0.2
0.1
-0.2
FIGURE 2-13:
Active Power Measurement
Error over VDD , Internal VREF (G = 16, PF = 1).
Measurement Error (%)
Measurement Error (%)
0.15
VDD=4.5V
VDD=4.75V
0.05
VDD=5.0V
VDD=5.25V
-0.05
VDD=5.5V
-0.1
0.0001
0.0010
0.0100
0.1000
1.0000
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.0001
PF = 0.5
PF = 1
50
55
60
65
70
75
Frequency (Hz)
FIGURE 2-15:
Active Power Measurement
Error vs. Input Frequency (G = 16).
DS22025A-page 10
1.0000
+85°C
+25°C
-40°C
0.0010
0.0100
0.1000
1.0000
FIGURE 2-17:
Active Power Measurement
Error with External VREF (G = 1, PF = 0.5).
Measurement Error (%)
% Error
FIGURE 2-14:
Active Power Measurement
Error over VDD, External VREF (G = 1, PF = 1).
45
0.1000
CH1 Vp-p Amplitude (V)
CH0 Vp-p Amplitude (V)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0100
FIGURE 2-16:
Active Power Measurement
Error with External VREF (G = 1, PF = 1).
0.2
0
0.0010
CH0 Vp-p Amplitude (V)
CH0 Vp-p Amplitude (V)
0.1
+25°C
- 40°C
-0.1
-0.3
0.0001
1.0000
+85°C
0
0.5
0.4
0.3
0.2
0.1
0 +25°C
-0.1
-0.2
-0.3
-0.4
-0.5
0.0001
+85°C
- 40°C
0.0010
0.0100
0.1000
1.0000
CH0 Vp-p Amplitude (V)
FIGURE 2-18:
Active Power Measurement
Error with External VREF (G = 2, PF = 1).
© 2006 Microchip Technology Inc.
MCP3909
+85°C
-40°C
0.0100
0.1000
1
0.8
0.6
0.4
0.2
0
-0.2 - 40°C
-0.4
-0.6
-0.8
-1
0.0000
1.0000
CH1 Vp-p Amplitude (V)
-40°C
0.0010
0.0100
0.1000
1
0.8
0.6
0.4
0.2 +25°C
0
-0.2
-0.4
-0.6
-0.8
-1
0.0000
+85°C
-40°C
0.0010
0.0100
0.1000
CH1 Vp-p Amplitude (V)
FIGURE 2-21:
Active Power Measurement
Error with External VREF (G = 8, PF = 0.5).
© 2006 Microchip Technology Inc.
0.0100
0.1000
-40°C
+85°C
0.0001
0.0010
0.0100
0.1000
FIGURE 2-23:
Active Power Measurement
Error with External VREF (G =16, PF = 0.5).
SINAD (dBFS)
Measurement Error (%)
FIGURE 2-20:
Active Power Measurement
Error with External VREF (G = 8, PF = 1).
0.0001
0.0010
CH1 Vp-p Amplitude (V)
CH1 Vp-p Amplitude (V)
1
0.8
0.6
0.4
0.2 +25°C
0
-0.2
-0.4
-0.6
-0.8
-1
0.0000
0.0001
FIGURE 2-22:
Active Power Measurement
Error with External VREF (G = 16, PF = 1).
Measurement Error (%)
Measurement Error (%)
+85°C
0.0001
+25°C
CH1 Vp-p Amplitude (V)
FIGURE 2-19:
Active Power Measurement
Error with External VREF (G = 2, PF = 0.5).
1
0.8
0.6
0.4
0.2
+25°C
0
-0.2
-0.4
-0.6
-0.8
-1
0.0000
+85°C
100
90
80
70
60
50
40
30
20
10
0
0.0001
SINAD (dBFS)
SINAD(dB)
0.0010
0.0100
0.1000
100
90
80
70
60
50
40
30
20
10
0
SINAD (dB)
1
0.8
0.6
0.4
0.2
0
-0.2
+25°C
-0.4
-0.6
-0.8
-1
0.0001
0.0010
Measurement Error (%)
Measurement Error (%)
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz, CH1 input = 660 mVP-P at 50 Hz, CH0 amplitude sweeps at 50 Hz.
1.0000
CH0 Vp-p Amplitude (V)
FIGURE 2-24:
Signal-to-Noise and
Distortion Ratio vs. Input Signal Amplitude
(G = 1).
DS22025A-page 11
MCP3909
100
100
90
90
80
80
SINAD (dBFS)
70
70
60
60
50
50
40
40
30
30
SINAD (dB)
20
20
10
10
0
0
0.000010 0.000100 0.001000 0.010000 0.100000
CH0 Vp-p Amplitude (V)
CH0 Vp-p Amplitude (V)
SINAD (dBFS)
SINAD (dB)
0.0001
0.001
0.01
0.1
0
-20
Amplitude (dB)
100
90
80
70
60
50
40
30
20
10
0
FIGURE 2-27:
Signal-to-Noise and
Distortion Ratio vs. Input Signal Amplitude
(G = 16).
SINAD (dB)
SINAD (dBFS)
FIGURE 2-25:
Signal-to-Noise and
Distortion Ratio vs. Input Signal Amplitude
(G = 2).
100
90
80
70
60
50
40
30
20
10
0
0.00001
-40
-60
-80
-100
-120
-140
-160
0
CH0 Vp-p Amplitude (V)
FIGURE 2-26:
Signal-to-Noise and
Distortion Ratio vs. Input Signal Amplitude
(G = 8).
DS22025A-page 12
SINAD (dB)
SINAD (dBFS)
100
100
90
90
SINAD (dBFS)
80
80
70
70
60
60
50
50
SINAD (dB)
40
40
30
30
20
20
10
10
0
0
0.000100 0.001000 0.010000 0.100000 1.000000
SINAD (dB)
SINAD (dBFS)
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz, CH1 input = 660 mVP-P at 50 Hz, CH0 amplitude sweeps at 50 Hz.
2000
4000
6000
Frequency (Hz)
FIGURE 2-28:
Input Signal.
Frequency Spectrum, 50 Hz
© 2006 Microchip Technology Inc.
MCP3909
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
3.1
PIN FUNCTION TABLE
Pin No.
Symbol
Function
1
DVDD
Digital Power Supply Pin
2
HPF
High-Pass Filters Control Logic Pin
3
AVDD
4
NC
5
CH0+
Non-Inverting Analog Input Pin for Channel 0 (Current Channel)
6
CH0-
Inverting Analog Input Pin for Channel 0 (Current Channel)
7
CH1-
Inverting Analog Input Pin for Channel 1 (Voltage Channel)
8
CH1+
Non-Inverting Analog Input Pin for Channel 1 (Voltage Channel)
9
MCLR
Master Clear Logic Input Pin
10
REFIN/OUT
Analog Power Supply Pin
No Connect
Voltage Reference Input/Output Pin
11
AGND
Analog Ground Pin, Return Path for internal analog circuitry
12
SCK / F2
Serial Clock or Frequency Control for HFOUT Logic Input Pin
13
SDI / F1
Serial Data Input or Frequency Control for FOUT0/1 Logic Input Pin
14
CS / F0
Chip Select or Frequency Control for FOUT0/1 Logic Input Pin
15
G1
Gain Control Logic Input Pin
16
G0
Gain Control Logic Input Pin
17
OSC1
Oscillator Crystal Connection Pin or Clock Input Pin
18
OSC2
Oscillator Crystal Connection Pin or Clock Output Pin
19
NC
20
SDO / NEG
No Connect
21
DGND
Digital Ground Pin, Return Path for Internal Digital Circuitry
22
HFOUT
High-Frequency Logic Output Pin (Intended for Calibration)
23
FOUT1
Differential Mechanical Counter Logic Output Pin
24
FOUT0
Differential Mechanical Counter Logic Output Pin
Serial Data Out or Negative Power Logic Output Pin
Digital VDD (DVDD)
DVDD is the power supply pin for the digital circuitry
within the MCP3909.
This pin requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified
operation. Refer to Section 6.0 “Applications
Information”.
3.2
High-Pass Filter Input Logic Pin
(HPF)
HPF controls the state of the high-pass filter in both
input channels. A logic ‘1’ enables both filters,
removing any DC offset coming from the system or the
device. A logic ‘0’ disables both filters allowing DC
voltages to be measured.
3.3
Analog VDD (AVDD)
AVDD is the power supply pin for the analog circuitry
within the MCP3909.
This pin requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified
operation. Refer to Section 6.0 “Applications
Information”.
3.4
Current Channel (CH0-, CH0+)
CH0- and CH0+ are the fully differential analog voltage
input channels for the current measurement,
containing a PGA for small-signal input, such as shunt
current sensing. The linear and specified region of this
channel is dependant on the PGA gain. This
corresponds to a maximum differential voltage of
±470 mV/G and maximum absolute voltage, with
respect to AGND, of ±1V. Up to ±6V can be applied to
these pins without the risk of permanent damage.
Refer to Section 1.0 “Electrical Characteristics”.
© 2006 Microchip Technology Inc.
DS22025A-page 13
MCP3909
3.5
Voltage Channel (CH1-,CH1+)
CH1- and CH1+ are the fully differential analog voltage
input channels for the voltage measurement. The linear
and specified region of these channels have a
maximum differential voltage of ±660 mV and a
maximum absolute voltage of ±1V, with respect to
AGND. Up to ±6V can be applied to these pins without
the risk of permanent damage.
3.10
Serial Data Input or F1 Frequency
Control Pin
Refer to Section 1.0 “Electrical Characteristics”.
This dual function pin can act as either the serial data
input for SPI communication or the F1 selection for the
high-frequency output and low-frequency output pin
ranges, changing the value of the constants FC and
HFC used in the device transfer function. FC and HFC
are the frequency constants that define the period of
the output pulses for the device.
3.6
3.11
Master Clear (MCLR)
MCLR controls the reset for both delta-sigma ADCs, all
digital registers, the SINC filters for each channel and
all accumulators post multiplier. The MCLR pin is also
used to change pin functionality and enter the serial
interface mode. A logic ‘0’ resets all registers and holds
both ADCs in a Reset condition. The charge stored in
both ADCs is flushed and their output is maintained to
0x0000h. The only block consuming power on the
digital power supply during Reset is the oscillator
circuit.
3.7
Reference (REFIN/OUT)
REFIN/OUT is the output for the internal 2.4V
reference. This reference has a typical temperature
coefficient of 15 ppm/°C and a tolerance of ±2%. In
addition, an external reference can also be used by
applying voltage to this pin within the specified range.
This pin requires appropriate bypass capacitors to
AGND, even when using the internal reference only.
Refer to Section 6.0 “Applications Information”.
3.8
Analog Ground (AGND)
AGND is the ground connection to internal analog
circuitry (ADCs, PGA, band gap reference, POR). To
ensure accuracy and noise cancellation, this pin must
be connected to the same ground as DGND, preferably
with a star connection. If an analog ground plane is
available, it is recommended that this device be tied to
this plane of the PCB. This plane should also reference
all other analog circuitry in the system.
3.9
Serial Clock Input or F2 Frequency
Control Pin
This dual function pin can act as either the serial clock
input for SPI communication or the F2 selection for the
high-frequency output and low-frequency output pin
ranges, changing the value of the constants FC and
HFC used in the device transfer function. FC and HFC
are the frequency constants that define the period of
the output pulses for the device.
DS22025A-page 14
Chip Select (CS) or F0 Frequency
Control Pin
This dual function pin can act as either the chip select
for SPI communication or the F0 selection for the highfrequency output and low-frequency output pin ranges
by changing the value of the constants FC and HFC
used in the device transfer function. FC and HFC are
the frequency constants that define the period of the
output pulses for the device.
3.12
Gain Control Logic Pins (G1, G0)
G1 and G0 select the PGA gain (G) on Channel 0 from
four different values: 1, 2, 8 and 16.
3.13
Oscillator (OSC1, OSC2)
OSC1 and OSC2 provide the master clock for the
device. A resonant crystal or clock source with a similar
sinusoidal waveform must be placed across these pins
to ensure proper operation. The typical clock frequency
specified is 3.579545 MHz. However, the clock
frequency can be within the range of 1 MHz to 4 MHz
without disturbing measurement error. Appropriate
load capacitance should be connected to these pins for
proper operation.
A full-swing, single-ended clock source may be
connected to OSC1 with proper resistors in series to
ensure no ringing of the clock source due to fast
transient edges.
3.14
Serial Data Output or Negative
Power Output Logic Pin (NEG)
This dual function pin can act as either the serial data
output for SPI communication or NEG. NEG detects
the phase difference between the two channels and will
go to a logic ‘1’ state when the phase difference is
greater than 90° (i.e., when the measured real power is
negative). The output state is synchronous with the
rising-edge of HFOUT and maintains the logic ‘1’ until
the real power becomes positive again and HFOUT
shows a pulse.
© 2006 Microchip Technology Inc.
MCP3909
3.15
Ground Connection (DGND)
DGND is the ground connection to internal digital
circuitry (SINC filters, multiplier, HPF, LPF, digital-tofrequency converter and oscillator). To ensure
accuracy and noise cancellation, DGND must be
connected to the same ground as AGND, preferably
with a star connection. If a digital ground plane is
available, it is recommended that this device be tied to
this plane of the Printed Circuit Board (PCB). This
plane should also reference all other digital circuitry in
the system.
3.16
3.17
Frequency Output (FOUT0, FOUT1)
FOUT0 and FOUT1 are the frequency outputs of the
device that supply the average real-power information.
The outputs are periodic pulse outputs, with its period
proportional to the measured real power, and to the FC
constant, defined by F0 and F1 pin logic states. These
pins include high-output drive capability for direct use
of electromechanical counters and 2-phase stepper
motors. Since this output supplies average real power,
any 2ω ripple on the output pulse period is minimal.
High-Frequency Output (HFOUT)
HFOUT is the high-frequency output of the device and
supplies the instantaneous real-power information. The
output is a periodic pulse output, with its period proportional to the measured real power, and to the HFC
constant defined by F0, F1 and F2 pin logic states. This
output is the preferred output for calibration due to
faster output frequencies, giving smaller calibration
times. Since this output gives instantaneous real
power, the 2ω ripple on the output should be noted.
However, the average period will show minimal drift.
© 2006 Microchip Technology Inc.
DS22025A-page 15
MCP3909
4.0
DEVICE OVERVIEW
4.1
Active Power
The instantaneous power signal contains the activepower information; it is the DC component of the
instantaneous power. The averaging technique can be
used with both sinusoidal and non-sinusoidal waveforms, as well as for all power factors. The
instantaneous power is thus low-pass filtered in order
to produce the instantaneous real-power signal.
The MCP3909 is an energy metering IC that serves two
distinct functions that can operate simultaneously:
- Active Power Pulse Output
- Waveform Output via SPI Interface
For the active power output, the device supplies a
frequency output proportional to active (real) power,
and higher frequency output proportional to the
instantaneous power for meter calibration.
A digital-to-frequency converter accumulates the
instantaneous active real power information to produce
output pulses with a frequency proportional to the
average real power. The low-frequency pulses present
at the FOUT0 and FOUT1 outputs are designed to drive
electromechanical counters and two-phase stepper
motors displaying the real-power energy consumed.
Each pulse corresponds to a fixed quantity of real
energy, selected by the F2, F1 and F0 logic settings. The
HFOUT output has a higher frequency setting and less
integration period such that it can represent the instantaneous real-power signal. Due to the shorter accumulation time, it enables the user to proceed to faster
calibration under steady load conditions (see
Section 4.8 “Active Power FOUT0/1 and HFOUT Output Frequencies”).
For the waveform output, it can be used serially to
gather 16-bit voltage channel and current channel A/D
data, or 20-bit wide multiplier output data. Both
channels use 16-bit, second-order, delta-sigma ADCs
that oversample the input at a frequency equal to
MCLK/4, allowing for wide dynamic range input signals.
A Programmable Gain Amplifier (PGA) increases the
usable range on the current input channel (Channel 0).
Figure 4-1 represents the simplified block diagram of
the MCP3909, detailing its main signal processing
blocks.
Two digital high-pass filters cancel the system offset on
both channels such that the real-power calculation
does not include any circuit or system offset. After
being high-pass filtered, the voltage and current signals
are multiplied to give the instantaneous power signal.
This signal does not contain the DC offset components,
such that the averaging technique can be efficiently
used to give the desired active-power output.
MCP3909
CH0+
+
CH0-
PGA
ADC
ANALOG
HPF
X
DIGITAL
..0101...
LPF
CH1+
+
CH1-
ADC
FOUT0
FOUT1
HFOUT
DTF
HPF
Frequency
Content
0
0
Input Signal with
System offset and
line frequency
FIGURE 4-1:
DS22025A-page 16
ADC Output code
contains System
and ADC offset
0
DC Offset
removed by HPF
0
INSTANTANEOUS
POWER
0
INSTANTANEOUS
REAL POWER
Active Power Signal Flow with Frequency Contents.
© 2006 Microchip Technology Inc.
MCP3909
Analog Inputs
The MCP3909 analog inputs can be connected directly
to the current and voltage transducers (such as shunts
or current transformers). Each input pin is protected by
specialized ESD structures that are certified to pass
4 kV HBM and 400V MM contact charge. These
structures also allow up to ±6V continuous voltage to
be present at their inputs without the risk of permanent
damage.
Both channels have fully differential voltage inputs for
better noise performance. The absolute voltage at each
pin relative to AGND should be maintained in the ±1V
range during operation in order to ensure the measurement error performance. The common-mode signals
should be adapted to respect both the previous
conditions and the differential input voltage range. For
best performance, the common-mode signals should
be referenced to AGND.
The current channel comprises a PGA on the front-end
to allow for smaller signals to be measured without
additional signal conditioning. The maximum
differential voltage specified on Channel 0 is equal to
±470 mV/Gain (see Table 4-1). The maximum peak
voltage specified on Channel 1 is equal to ±660 mV.
TABLE 4-1:
GAIN SELECTIONS
G1
G0
CH0 Gain
Maximum
CH0 Voltage
0
0
1
1
0
1
0
1
1
2
8
16
±470 mV
±235 mV
±60 mV
±30 mV
4.3
16-Bit Delta-Sigma A/D Converters
The ADCs used in the MCP3909 for both current and
voltage channel measurements are delta-sigma ADCs.
They comprise a second-order, delta-sigma modulator
using a multi-bit DAC and a third-order SINC filter. The
delta-sigma architecture is very appropriate for the
applications targeted by the MCP3909 because it is a
waveform-oriented converter architecture that can offer
both high linearity and low distortion performance
throughout a wide input dynamic range. It also creates
minimal requirements for the anti-aliasing filter design.
The multi-bit architecture used in the ADC minimizes
quantization noise at the output of the converters
without disturbing the linearity.
Both ADCs have a 16-bit resolution, allowing wide input
dynamic range sensing. The oversampling ratio of both
converters is 64. Both converters are continuously
converting during normal operation. When the MCLR
pin is low, both converters will be in Reset and output
code 0x0000h. If the voltage at the inputs of the ADC is
larger than the specified range, the linearity is no longer
specified. However, the converters will continue to
© 2006 Microchip Technology Inc.
produce output codes until their saturation point is
reached. The DC saturation point is around 700 mV for
Channel 0 and 1V for Channel 1, using internal voltage
reference. The output code will be locked past the
saturation point to the maximum output code.
The clocking signals for the ADCs are equally
distributed between the two channels in order to
minimize phase delays to less than 1 MCLK period
(see Section 3.2 “High-Pass Filter Input Logic Pin
(HPF)”). The SINC filters main notch is positioned at
MCLK/256 (14 kHz with MCLK = 3.58 MHz), allowing
the user to be able to measure wide harmonic content
on either channel. The data ready signals used for
synchronization of the part with a MCU will come at a
rate of MCLK/256 and a pipeline delay of 3 data readys
is required to settle the SINC 3rd order digital filter. The
magnitude response of the SINC filter is shown in
Figure 4-2.
Normal Mode Rejection (dB)
4.2
0
-20
-40
-60
-80
-100
-120
0
5
10
15
20
25
30
Frequency (kHz)
FIGURE 4-2:
SINC Filter Magnitude
Response (MCLK = 3.58 MHz).
4.4
Ultra-Low Drift VREF
The MCP3909 contains an internal voltage reference
source specially designed to minimize drift over
temperature. This internal VREF supplies reference
voltage to both current and voltage channels ADCs.
The typical value of this voltage reference is 2.4V
±100 mV. The internal reference has a very low typical
temperature coefficient of ±15 ppm/°C, allowing the
output frequencies to have minimal variation with
respect to temperature since they are proportional to
(1/VREF)².
The output pin for the voltage reference is REFIN/OUT.
Appropriate bypass capacitors must be connected to
the REFIN/OUT pin for proper operation (see
Section 6.0 “Applications Information”). The
voltage reference source impedance is typically 4 kΩ,
which enables this voltage reference to be overdriven
by an external voltage reference source.
If an external voltage reference source is connected to
the REFIN/OUT pin, the external voltage will be used
as the reference for both current and voltage channel
ADCs. The voltage across the source resistor will then
DS22025A-page 17
MCP3909
4.5
Power-On Reset (POR)
The MCP3909 contains an internal POR circuit that
monitors analog supply voltage AVDD during operation.
This circuit ensures correct device startup at system
power-up and system power-down events. The POR
circuit has built-in hysteresis and a timer to give a high
degree of immunity to potential ripple and noise on the
power supplies, allowing proper settling of the power
supply during power-up. A 0.1 µF decoupling capacitor
should be mounted as close as possible to the AVDD
pin, providing additional transient immunity (see
Section 6.0 “Applications Information”).
The threshold voltage is typically set at 4V, with a
tolerance of about ±5%. If the supply voltage falls
below this threshold, the MCP3909 will be held in a
Reset condition (equivalent to applying logic ‘0’ on the
MCLR pin). The typical hysteresis value is approximately 200 mV in order to prevent glitches on the
power supply.
Once a power-up event has occurred, an internal timer
prevents the part from outputting any pulse for
approximately 1s (with MCLK = 3.58 MHz), thereby
preventing potential metastability due to intermittent
resets caused by an unsettled regulated power supply.
Figure 4-3 illustrates the different conditions for a
power-up and a power-down event in the typical
conditions.
AVDD
5V
4.2V
4V
1s
affects the DC component of the instantaneous power
and will cause the real-power calculation to be
erroneous. In order to remove DC offset components
from the instantaneous power signal, a high-pass filter
has been introduced on each channel. Since the highpass filtering introduces phase delay, identical highpass filters are implemented on both channels. The
filters are clocked by the same digital signal, ensuring
a phase difference between the two channels of less
than one MCLK period. Under typical conditions
(MCLK = 3.58 MHz), this phase difference is less than
0.005°, with a line frequency of 50 Hz. The cut-off
frequency of the filter (4.45 Hz) has been chosen to
induce minimal gain error at typical line frequencies,
allowing sufficient settling time for the desired
applications. The two high-pass filters can be disabled
by applying logic ‘0’ to the HPF pin.
Normal Mode Rejection (dB)
be the difference between the internal and external
voltage. The allowed input range for the external
voltage source goes from 2.2V to 2.6V for accurate
measurement error. A VREF value outside of this range
will cause additional heating and power consumption
due to the source resistor, which might affect measurement error.
0V
RESET
NO
PULSE
OUT
FIGURE 4-3:
4.6
Time
PROPER
OPERATION
RESET
Power-on Reset Operation.
High-Pass Filters and Multiplier
The active real-power value is extracted from the DC
instantaneous power. Therefore, any DC offset
component present on Channel 0 and Channel 1
DS22025A-page 18
-10
-15
-20
-25
-30
-35
-40
0.1
1
10
100
1000
Frequency (Hz)
FIGURE 4-4:
HPF Magnitude Response
(MCLK = 3.58 MHz).
The multiplier output gives the product of the two highpass filtered channels, corresponding to instantaneous
real power. Multiplying two sine wave signals by the
same ω frequency gives a DC component and a 2ω
component. The instantaneous power signal contains
the real power of its DC component, while also
containing 2ω components coming from the line
frequency multiplication. These 2ω components come
for the line frequency (and its harmonics) and must be
removed in order to extract the real-power information.
This is accomplished using the low-pass filter and DTF
converter.
4.7
DEVICE
MODE
0
-5
Active Power Low-Pass Filter and
DTF Converter
For the active power signal calculation, the MCP3909
uses a digital low-pass filter. This low-pass filter is a
first-order IIR filter, which is used to extract the active
real-power information (DC component) from the
instantaneous power signal. The magnitude response
of this filter is detailed in Figure 4-5. Due to the fact that
the instantaneous power signal has harmonic content
(coming from the 2ω components of the inputs), and
© 2006 Microchip Technology Inc.
MCP3909
application will then remove the small sinusoidal
content of the output frequency and filter out the
remaining 2ω ripple.
The cut-off frequency of the filter (8.9 Hz) has been
chosen to have sufficient rejection for commonly-used
line frequencies (50 Hz and 60 Hz). With a standard
input clock (MCLK = 3.58 MHz) and a 50 Hz line
frequency, the rejection of the 2ω component (100 Hz)
will be more than 20 dB. This equates to a 2ω
component containing 10 times less power than the
main DC component (i.e., the average active real
power).
HFOUT is intended to be used for calibration purposes
due to its instantaneous power content. The shorter
integration period of HFOUT demands that the 2ω
component be given more attention. Since a sinusoidal
signal average is zero, averaging the HFOUT signal in
steady-state conditions will give the proper real energy
value.
Normal Mode Rejection (dB)
since the filter is not ideal, there will be some ripple at
the output of the low-pass filter at the harmonics of the
line frequency.
0
4.8
Active Power FOUT0/1 and HFOUT
Output Frequencies
The thresholds for the accumulated energy are
different for FOUT0/1 and HFOUT (i.e., they have
different transfer functions). The FOUT0/1 allowed
output frequencies are quite low in order to allow
superior integration time (see Section 4.7 “Active
Power Low-Pass Filter and DTF Converter”). The
FOUT0/1 output frequency can be calculated with the
following equation:
-5
-10
-15
-20
-25
-30
-35
-40
0.1
1
10
100
1000
EQUATION 4-1:
Frequency (Hz)
FIGURE 4-5:
LPF1 Magnitude Response
(MCLK = 3.58 MHz).
The output of the low-pass filter is accumulated in the
digital-to-frequency converter. This accumulation is
compared to a different digital threshold for FOUT0/1
and HFOUT, representing a quantity of real energy
measured by the part. Every time the digital threshold
on FOUT0/1 or HFOUT is crossed, the part will output a
pulse (See Section 4.8 “Active Power FOUT0/1 and
HFOUT Output Frequencies”).
The equivalent quantity of real energy required to
output a pulse is much larger for the FOUT0/1 outputs
than the HFOUT. This is such that the integration period
for the FOUT0/1 outputs is much larger. This larger
integration period acts as another low-pass filter so that
the output ripple due to the 2ω components is minimal.
However, these components are not totally removed,
since realized low-pass filters are never ideal. This will
create a small jitter in the output frequency. Averaging
the output pulses with a counter or a MCU in the
TABLE 4-2:
Where:
FOUT FREQUENCY
OUTPUT EQUATION
8.06 × V 0 × V 1 × G × F C
F OUT ( Hz ) = ---------------------------------------------------------2
( V REF )
V0
=
the RMS differential voltage on Channel 0
V1
=
the RMS differential voltage on Channel 1
G
=
the PGA gain on Channel 0 (current
channel)
FC
=
the frequency constant selected
VREF
=
the voltage reference
For a given DC input V, the DC and RMS values are
equivalent. For a given AC input signal with amplitude
of V, the equivalent RMS value is V/ sqrt(2), assuming
purely sinusoidal signals. Note that since the real
power is the product of two RMS inputs, the output frequencies of AC signals are half of the DC inputs ones,
again assuming purely sinusoidal AC signals. The
constant FC depends on the FOUT0 and FOUT1 digital
settings. Table 4-2 shows FOUT0/1 output frequencies
for the different logic settings.
ACTIVE POWER OUTPUT FREQUENCY CONSTANT FC FOR FOUT0/1 (VREF = 2.4V)
F1
F0
FC (Hz)
FC (Hz)
(MCLK = 3.58 MHz)
FOUT Frequency (Hz)
with Full-Scale
DC Inputs
FOUT Frequency (Hz)
with Full-Scale
AC Inputs
0
0
MCLK/221
1.71
0.74
0.37
0
1
20
MCLK/2
3.41
1.48
0.74
1
0
MCLK/219
6.83
2.96
1.48
1
18
13.66
5.93
2.96
1
MCLK/2
© 2006 Microchip Technology Inc.
DS22025A-page 19
MCP3909
The high-frequency output HFOUT has lower
integration times and, thus, higher frequencies. The
output frequency value can be calculated with the
following equation:
EQUATION 4-2:
ACTIVE POWER HFOUT
FREQUENCY OUTPUT
EQUATION
8.06 × V 0 × V 1 × G × HF C
HF OUT ( Hz ) = --------------------------------------------------------------2
( V REF )
Where:
V0
=
the RMS differential voltage on Channel 0
V1
=
the RMS differential voltage on Channel 1
G
=
the PGA gain on Channel 0 (current
channel)
HFC
=
the frequency constant selected
VREF
=
the voltage reference
The constant HFC depends on the FOUT0 and FOUT1
digital settings with the Table 4-3.
The detailed timings of the output pulses are described
in the Timing Characteristics table (see Section 1.0
“Electrical Characteristics” and Figure 1-1).
TABLE 4-3:
4.8.1
MINIMAL OUTPUT FREQUENCY
FOR NO-LOAD THRESHOLD
The MCP3909 also includes, on each output
frequency, a no-load threshold circuit that will eliminate
any creep effects in the meter. The outputs will not
show any pulse if the output frequency falls below the
no-load threshold. This threshold only applies to the
pulse outputs and does not gate any serial data coming
from either the A/D output or the multiplier output. The
minimum output frequency on FOUT0/1 and HFOUT is
equal to 0.0015% of the maximum output frequency
(respectively FC and HFC) for each of the F2, F1 and F0
selections (see Table 4-2 and Table 4-3); except when
F2, F1, F0 = 011. In this last configuration, the no-load
threshold feature is disabled. The selection of FC will
determine the start-up current load. In order to respect
the IEC standards requirements, the meter will have to
be designed to allow start-up currents compatible with
the standards by choosing the FC value matching
these requirements. For additional applications
information on no-load threshold, startup current and
other meter design points, refer to AN994, "IEC Compliant Active Energy Meter Design Using The
MCP3905/6”, (DS00994).
OUTPUT FREQUENCY CONSTANT HFC FOR HFOUT (VREF = 2.4V)
F2
F1
F0
HFC
HFC (Hz)
HFC (Hz)
(MCLK = 3.58 MHz)
HFOUT Frequency (Hz) with
full-scale AC Inputs
0
0
0
64 x FC
MCLK/215
109.25
27.21
0
0
1
32 x FC
MCLK/215
109.25
27.21
16 x FC
MCLK/215
109.25
27.21
2048 x FC
MCLK/27
27968.75
6070.12
0
0
1
1
0
1
1
0
0
128 x FC
MCLK/216
219.51
47.42
1
0
1
64 x FC
MCLK/216
219.51
47.42
32 x FC
MCLK/216
219.51
47.42
16 x FC
MCLK/216
219.51
47.42
1
1
1
1
DS22025A-page 20
0
1
© 2006 Microchip Technology Inc.
MCP3909
5.0
SERIAL INTERFACE
DESCRIPTION
with multiple ADCs, this fast communication is essential to allow for power calculation windows between
conversions, as shown in Figure 5-3.
5.1
Dual Functionality Pin And Serial
Interface Overview
After a serial mode has been entered, all blocks of the
MCP3909 device are still operational. The PGA, A/D
converters, HPF, multiplier, LPF, and other digital
sections are still functional, allowing the device to have
true dual functionality in energy metering systems.
The MCP3909 device contains three serial modes that
are accessible by changing the pin functionality of the
NEG, F2, F1, and F0 pins to SDO, SCK, SDI and CS,
respectively.
These modes are entered by giving the MCP3909
device a serial command on these pins during a time
window after device reset or POR. During this window
of time, F2 acts as SCK, F1 acts as SDI and F0 acts
as CS. Once a serial mode has been entered, the
device must be reset to disable mode functionality, or
change to another serial mode. This is done by using
MCLR pin or power on reset event.
During serial mode entry and the three serial modes,
data is clocked into the device on the rising edge of
SCK and out of the device on the falling edge of SCK.
The SPI data can be access at up to 20 MHz. This
speed enables quick data retrieval in between
conversion times. For 3-phase metering applications
DVDD
HPF
AVDD
NC
CH0+
CHOCH1CH1+
MCLR
REFIN / OUT
AGND
F2 / SCK
FIGURE 5-1:
the MCP3909.
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
FOUT0
FOUT1
HFOUT
DGND
NEG / SDO
NC
9
10
11
16
15
14
G0
12
13
F1 / SDI
CLKOUT
CLKIN
G1
F0 / CS
Dual Functionality Pins for
IRQ
tSAMPLE
tLINE_CYC
IRQ
Phase A,B,C I & V Data
SDO DR
16 bits
x 6 ADCs
DR
tSAMPLE
FIGURE 5-2:
Data Access between Data Ready Pulses using SPI Interface for a 3-phase System.
© 2006 Microchip Technology Inc.
DS22025A-page 21
MCP3909
MCLR
tWINDOW
tWINSET
1
2
3
4
5
6
7
8
F2 / SCK
F0 / CS
F1 / SDI
FIGURE 5-3:
DS22025A-page 22
D7 D6 D5 D4 D3 D2
D1 D0
Dual Functionality Pin Serial Mode Entry Protocol.
© 2006 Microchip Technology Inc.
MCP3909
5.2
Serial Mode Entry Codes
The MCP3909 devices contains three different serial
modes with data presented in 2's complement coding.
• Multiplier Output
• Dual Channel Output
• Filter Input
the F2, F1, F0 output frequency selection constant can
be changed with multiple command bytes for serial
mode entry.
The command bytes to enter these modes are
described in Table 5-1.
After entering any of these modes the active power
calculation block is still functional and presents output
pulses on FOUT0, FOUT1, and HFOUT. For this reason,
TABLE 5-1:
ENTRY CODES
Command
D7......D0
Serial Mode
1 0 1 0 0 0 0 1
Internal State of F2, F1, F0 Constants Frequency
Selection During Serial Mode (1)
F2
F1
F0
Multiplier Output
0
F1 pin
1
1 0 1 0 1 0 0 1
Multiplier Output
1
F1 pin
1
1 0 1 0 0 1 0 0
Dual Channel Output Pre HPF1
0
F1 pin
1
1 0 1 0 1 1 0 0
Dual Channel Output Post HPF1
1
F1 pin
1
1 0 1 0 1 0 1 0
Filter Input
1
0
F0 pin
1 0 1 0 1 1 1 0
Filter Input
1
1
F0 pin
1 0 1 0 0 0 1 0
Filter Input
0
0
F0 pin
1 0 1 0 0 1 1 0
Filter Input
0
1
F0 pin
Note 1:
The active power frequency outputs FOUT0, FOUT1, and HFOUT remain active after serial mode entry.
Leaving the SDI (F1) and CS (F0) pins at a known state after serial communication will control the
frequency selection. The HPF pin controls the state of the HPF for the multiplier mode output and the output pulses from the active power D to F block.
© 2006 Microchip Technology Inc.
DS22025A-page 23
MCP3909
5.3
Multiplier Output Mode
clock cycles and a new multiplier output value is
ready. If the multiplier value is not clocked out of the
device it will be over-written. Data is clocked out on the
rising edge of SCK.
Multiplier mode allows the user to retrieve the output
of the multiplier on the MCP3909 device. Data is
presented in a 20 bit (19 bit + sign) protocol, MSB first.
A data ready flag (DR) is output for every MCLK/256
+
–
+
–
( CH0 – CH0 ) ( CH1 – CH1 )
Multiplier Code = --------------------------------------------------------------------------------- • 524288 • 8.06 • G
V REF 2
TABLE 5-2:
MULTIPLIER OUTPUT MODE CODING
Binary
Decimal
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+524287
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
+524286
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
-1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
-524287
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-524288
F0 / CS
1
2
3
4
X 20
17 18
19 20
F2 / SCK
X 20
NEG / SDO
Hi-z
DR
D19 D18 D17 D16
D3
SIGN MSB
DS22025A-page 24
D1
D0
0
Hi-z
LSB
Hi-z
F1 / SDI
FIGURE 5-4:
D2
Multiplier Output Mode.
© 2006 Microchip Technology Inc.
MCP3909
5.4
Dual Channel Output Mode
A data ready flag (DR) is output for every MCLK / 256
clock cycles and a new filter output value is ready. If the
dual channel output values are not clocked, and is not
clocked out of the device, they will be over-written.
This mode allows the user to retrieve the individual
channel information from the ADC outputs. The ADC
outputs of both channels are synchronized together
and their data ready is represented by the data ready
pulse on SDO. If the ADC output values are not clocked
out of the device, they will be over-written. A 32-bit data
word is given, each channel is 16 bits (15 bits + sign),
presented in 2's complement coding. Channel 1 comes
first then channel 0.
The following formulas relate the channel input
voltages to their respective output code. The code
locks to +32767 on the positive side, and to -32768 on
the negative side.
⎛ ( V IN+ – V IN- )⎞
0.66
Channel 0 Code = ⎜ ------------------------------------⎟ × 32768 × ⎛⎝ 8.06 × -----------⎞⎠ × PGA
V
0.47
⎝
⎠
REF
( V IN+ – V IN- )
0.47
Channel 1 Code = ------------------------------------ × 32768 × ⎛⎝ 8.06 × -----------⎞⎠
V
0.66
REF
TABLE 5-3:
Binary
0
0
0
1
1
1
111
111
000
111
000
000
1111
1111
0000
1111
0000
0000
5.5
CHANNEL OUTPUT MODE
CODING
1111
1111
0000
1111
0000
0000
There are two options for the channel output data. The
first options collects the channel data pre-high pass filter, or the output of the SINC filter of the delta sigma
modulator. The second option collects the channel data
post high pass filter. It is important to note that the HPF
pin controls the state of the high pass filter for this second option. If the HPF pin is low, the post high pass filter mode will output all zero's. This HPF pin must be
high to access the post HPF data in the channel output
mode.
Decimal
1111
1110
0000
1111
0001
0000
High-Pass Filter Control
+ 32,767
+ 32,766
0
-1
- 32,767
- 32,768
F0 / CS
1
2
X 32
X 16
15 16
X 16
17 18 31 32
F2 / SCK
X 16
NEG / SDO
Hi-z
DR
X 32
D15 D14 D1
D31 D30 D17 D16
D0
Hi-z
Channel 0
Channel 1
Hi-z
F1 / SDI
FIGURE 5-5:
X 16
Dual Channel Output Mode.
© 2006 Microchip Technology Inc.
DS22025A-page 25
MCP3909
5.6
Filter Input Mode
When using filter input mode, the user must wait for
the data ready flag (DR) to appear on SDO before
attempting to clock in data to the device. The user can
not access either the multiplier output or the dual
channel output while in this mode.
The filter input mode allows the user to feed the
MCP3909 device an input to the LPF1. Data is
received MSB first. The MCP3909 will treat this data
as if it were the output of the multiplier and will LPF
and D-F the result as normal, giving the resulting
output frequency on HFOUT, FOUT0 and FOUT1. See
Tables 4-2 and 4-3 for transfer functions of the output
frequencies.
F0 / CS
X 20
1
2
3
4
17 18
19 20
D3
D1
F2 / SCK
X 20
F1 / SDI
NEG / SDO
FIGURE 5-6:
DS22025A-page 26
D19
Hi-z
D18 D17 D16
D2
D0
Hi-z
DR
Filter Input Mode.
© 2006 Microchip Technology Inc.
MCP3909
5.7
Using the MCP3909 with
Microcontroller (MCU) SPI Ports
With microcontroller SPI ports, it is required to send
groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on
the falling edge of clock and latch data in on the rising
edge, or vice versa depending on the mode.
TABLE 5-4:
Standard SPI
Mode
Terminology
5.7.1
SPI MODE DEFINITIONS
The following table represents the standard SPI mode
terminology, the respective PIC bit settings, and a
description of compatibility for the MCP3909 device.
The MCP3909 works in SPI mode 0,1 mode, that is the
data is clocked out of the part on the rising edge and
clocked in on the falling edge of SCK.
SPI MODE COMPATIBILITY
PIC Control Bits
State
MCP3909
Compatibility
Description
CKP
CKE
0,0
0
1
—
Idle state for clock is low level, transmit (from PIC)
occurs from active to idle clock state
0,1
0
0
√
Idle state for clock is low level, transmit (from PIC)
occurs from idle to active clock state
1,0
1
1
—
Idle state for clock is high level, transmit (from PIC)
occurs from active to idle clock state
1,1
1
0
—
Idle state for clock is high level, transmit (from PIC)
occurs from idle to active clock state
© 2006 Microchip Technology Inc.
DS22025A-page 27
MCP3909
F0 / CS
MCU latches data from
Device on falling edges of SCK
F2 / SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data is clocked out
on rising edges of SCK
F1 / SDI
Don’t Care
NEG / SDO
D19 D18 D17 D16 D15 D14 D13
MCU Transmit Buffer
MCU Receive Buffer
X
X
X
X
X
X
X
D12
D11 D10 D9
X
X
D19 D18 D17 D16 D15 D14 D13 D12
Data stored into MCU receive register
after transmission of first 8 bits
X
X
D11 D10 D9
D8
D7
D6
D5
X
X
X
X
X
D8
D7
D6
D5
D4
D4
Data stored into MCU receive register
after transmission of second 8 bits
F0 / CS
F2 / SCK
17
18
F1 / SDI
19
20
21
22
23
24
Don’t Care
D3
NEG / SDO
D2
D1 D0
MCU Transmit Buffer
X
X
X
X
X
X
X
X
MCU Receive Buffer
D3
D2
D1 D0
0
0
0
0
X = Don’t Care Bits
Data stored into MCU receive register
after transmission of third 8 bits
FIGURE 5-7:
idles low).
DS22025A-page 28
N = Null Bits
Multiplier Output Mode 1 SPI Communication using 8-bit segments (Mode 0,1: SCK
© 2006 Microchip Technology Inc.
MCP3909
F0 / CS
MCU latches data from
Device on falling edges of SCK
1
F2 / SCK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data is clocked out
on rising edges
F1 / SDI
Don’t Care
CHANNEL 0
NEG / SDO
D15 D14 D13 D12 D11 D10 D9
MCU Transmit Buffer
X
MCU Receive Buffer
X
X
X
X
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CH0 Data stored into MCU receive register
after transmission of second 8 bits
CH0 Data stored into MCU receive register after transmission of first 8 bits
F0 / CS
MCU latches data from
Device on falling edges of SCK
F2 / SCK
17
18
20
19
21
22
23
24
25
26
27
28
29
30
31
32
Data is clocked out
on rising edges
F1 / SDI
Don’t Care
CHANNEL 1
NEG / SDO
D15 D14 D13 D12 D11 D10 D9
MCU Transmit Buffer
MCU Receive Buffer
X
X
X
X
X
X
D8
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CH1 Data stored into MCU receive register after transmission of third 8 bits
FIGURE 5-8:
SCK idles low).
D7
CH1 Data stored into MCU receive register
after transmission of fourth 8 bits
Dual Channel Output Mode SPI Communication using 8-bit segments (Mode 0,1:
© 2006 Microchip Technology Inc.
DS22025A-page 29
MCP3909
6.0
APPLICATIONS INFORMATION
6.1
The following application figures represent meter
designs using the MCP3909 device. Some of these
applications ideas are available as fully function meter
reference designs and demo boards. For complete
schematic and for fully function meter designs, visit
Microchip’s web page for demo board and reference
design availability.
Performing RMS, Apparent Power,
and Active Power using MCP3909
Waveform data
Figure 6-1 represents power calculations from waveform data based on a PIC MCU and MCP3909 device.
The PIC MCU accomplishes the following energy
meter calculation outputs per phase, per line cycle:
-
RMS Current
RMS Voltage
Active Power
Apparent Power
Output registers for the power quantities and calibration registers for phase, offset, gain, and LSB adjustment are available through a serial interface to the PIC
microcontroller. See Microchip’s web page for firmware
solution and demo board.
The example signal flow here shows 4 output power
quantities and 6 calibration registers. For a 60 Hz
design that is using 128 samples per line cycle for the
power calculation the MCP3909 would have a new
data ready pulse every 130 µs. The SPI communication to gather 16-bits x 2 channels at 10 MHz is
approximately 3.2 µs, leaving ~125 µs for the power
calculations before the next sample is ready.
.
MCP3909
PIC Microcontroller
RMS Current
X
Σ
X2
ADC
X
Apparent Power
CURRENT
PHA_I_RMS_OFF:16
X
X
Σ
PHA_VA_GAIN:16
Active Power
VOLTAGE
Φ
ADC
PHA_DELAY:8
PHA_W_GAIN:16
PHA_W_OFF:32
PHA_V_RMS_OFF:16
X2
Σ
RMS Voltage
FIGURE 6-1:
Power Calculations from Waveform sampling using PIC MCU. Register names shown
are used on MCP3909 Energy Meter Reference Design.
DS22025A-page 30
© 2006 Microchip Technology Inc.
MCP3909
6.2
Achieving Line Cycle Sampling
with Zero Blind Cycles
A simpler lower cost option would be to choose a
frequency that would give an integer number of line
cycles for exactly 50 Hz (or 60 Hz). This is possible
using a 39.3216 MHz crystal for the PIC18F device.
In most energy meter applications, it will be necessary
to have 2N samples for each 50 or 60 Hz line cycle,
where N is typically 64, 128 or 256. Controlling the
MCLK of the MCP3909 allows you to control the
sample rate and ultimately the data ready (DR) pulses
for coherent waveform sampling. The following
scheme shows how the TIMER and COMPARATOR
modules of the PIC MCU can be used to generate the
clock for the MCP3909 from either a PLL internal
MCLK. For class 0.2 or class 0.1 meter designs that
require harmonic analysis using a PLL is recommended to shift sample rate with line cycle drift, e.g.
line cycle changes from 60 Hz to 59.1 Hz. This is
shown as option 1 in Figure 6-2.
Figure 6-2 shows example clock frequencies to
achieve 128 samples for each line cycle, 1.63 MHz for
a 50 Hz line, or 1.96 MHz for a 60 Hz line. The
MCP3909 clock can operate from 1 MHz to 4 MHz.
Using this approach, the PIC MCU can gather the
waveform data immediately after the data ready pulse,
at up to 10 MHz. The remainder of the time can be used
to calculate the power measurements to achieve true
line cycle sampling with zero blind cycles.
For more information and firmware, see the Microchip’s
web page for demo board information.
128 samples/line cycle
X1
Phase A || B || C
50 (or 60 Hz)
39.3216 MHz
(50 or 60 Hz)
1.63 MHz (50)
PLL Circuit
x 32768
1.96 MHz (60)
3.579 MHz
PIC MCU
CCP2 / 32768
Option 1
Option 2
MCLK input
SDO
SDO
To PIC MCU
IRQ
MCP3909
SDO
MCP3909
MCP3909
IRQ
DR Pulse
tSAMPLE
tLINE_CYC
IRQ
Phase A,B,C I & V Data
SDO DR
16 bits
x 6 ADCs
DR
tSAMPLE
FIGURE 6-2:
Using the PIC device to control the MCP3909 MCLK to achieve 2N samples per line
cycle, 3-phase sampling shown with 6 ADCs
© 2006 Microchip Technology Inc.
DS22025A-page 31
MCP3909
N
PHA_W:16
ENERGY_W:64
ENERGY_VA_GLSB:16
PHA_I_RMS:16
PHA_V_RMS:16
L
kW
kWhr
kVAhr
A
V
CH1+
CH1-
MCP3909
AGND,DGND
...
RB0
RC1/CCP2
RC3/SCK
RC5/SDO
RC4/SDI
RA0/ANO
SCK
SDI
SDO
CS
OSC1
Power Supply
Circuitry
40 MHZ
Resistor Divider
AVDD,DVDD CLKIN
PIC MCU
CH0+
CH0-
RB7
LCD
OSC2
RX/RC6
TX/RC7
GND
FIGURE 6-3:
6.3
Simplified MCU Based Energy Meter.
Meter Calibration
To achieve meter calibration the MCP3909 waveform
samples are adjusted during the power calculations on
the PIC MCU. In Figure 6-3, this interface is shown via
RS-232 on the PIC microcontroller. This process is
streamlined using calibration software available from
Microchip’s web site.
DS22025A-page 32
RS-232
To PC or
Calibration
Equipment
6.4
Analog Meter Design Tips
For analog design tips and PCB layout recommendations, refer to AN994, "IEC Compliant Active Energy
Meter Design Using The MCP390X” (DS00994). This
application note includes all required energy meter
design information, including the following:
•
•
•
•
•
•
•
•
•
•
•
•
Meter rating and current sense choices
Shunt design
PGA selection
F2, F1, F0 selection
Meter calibration
Anti-aliasing filter design
Compensation for parasitic shunt inductance
EMC design
Power supply design
No-Load threshold
Start-up current
Accuracy Testing Results from MCP390X-based
meter
• EMC Testing Results from MCP390X-based
meter
© 2006 Microchip Technology Inc.
MCP3909
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
24-Lead SSOP
Examples:
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
MCP3909
e3
I/SS^^
0648256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS22025A-page 33
MCP3909
24-Lead Plastic Shrink Small Outline (SS) (SSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
p
E1
D
B
2
1
n
A
c
φ
A2
A1
L
Units
Dimension Limits
n
p
MIN
INCHES
NOM
24
.026 BSC.
.073
.068
.005
.307
.209
.323
.030
.006
4°
–
MAX
MILLIMETERS*
NOM
24
0.65 BSC.
1.73
1.86
1.68
1.73
0.05
0.13
7.65
7.80
5.20
5.30
8.07
8.20
0.63
0.75
0.09
0.15
0°
4°
0.25
–
MIN
MAX
Number of Pins
Pitch
A
.078
Overall Height
.068
1.99
A2
.070
Molded Package Thickness
.066
1.78
Standoff
A1
.008
.002
0.21
E
.311
Overall Width
.301
7.90
E1
.212
Molded Package Width
.205
5.38
D
.328
Overall Length
.318
8.33
L
.025
0.95
.037
Foot Length
c
.004
–
–
Lead Thickness
φ
0°
8°
8°
Foot Angle
B
.010
0.38
.015
Lead Width
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.010" (0.254mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEDEC Equivalent: MO-150
Revised 9-14-05
Drawing No. C04-132
DS22025A-page 34
© 2006 Microchip Technology Inc.
MCP3909
APPENDIX A:
REVISION HISTORY
Revision A (December 2006)
• Original Release of this Document.
© 2006 Microchip Technology Inc.
DS22025A-page 35
MCP3909
NOTES:
DS22025A-page 36
© 2006 Microchip Technology Inc.
MCP3909
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
–X
/XX
Device
Temperature
Range
Package
Device:
MCP3909: Energy Metering IC
MCP3909T: Energy Metering IC
(Tape and Reel)
Temperature Range:
I
Package:
SS = Plastic Shrink Small Outline (209 mil Body),
24-lead
Examples:
a)
MCP3909-I/SS:
b)
Industrial Temperature,
24LD SSOP.
MCP3909T-I/SS: Tape and Reel,
Energy Metering IC
Energy Metering IC
Industrial Temperature,
24LD SSOP.
= -40°C to +85°C
© 2006 Microchip Technology Inc.
DS22025A-page 37
MCP3909
NOTES:
DS22025A-page 38
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
microperipherals, nonvolatile memory and analog products. In
addition, Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS22025A-page 39
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
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Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
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Tel: 678-957-9614
Fax: 678-957-1455
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Tel: 774-760-0087
Fax: 774-760-0088
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Fax: 630-285-0075
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Canada
Tel: 905-673-0699
Fax: 905-673-6509
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Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
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Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
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Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
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Tel: 86-532-8502-7355
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Tel: 63-2-634-9065
Fax: 63-2-634-9069
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Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS22025A-page 40
© 2006 Microchip Technology Inc.