SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193 – D3992, MARCH 1992 – REVISED APRIL 1993 • • • • • • • DW PACKAGE (TOP VIEW) Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot Caused By Line Reflections Repetitive Peak Forward Current . . . IFRM = 100 mA Inputs Are TTL-Voltage Compatible Low Power Consumption (Like CMOS) ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise D1 D2 D3 D4 GND GND D5 D6 D7 D8 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 D16 D15 D14 D13 VCC VCC D12 D11 D10 D9 description This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or pulldown resistors. The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state. The SN74ACT1073 is characterized for operation from – 40°C to 85°C. logic diagram, one of sixteen channels (positive logic) D1 VCC VCC 1 16 15 TG GND GND 6 5 Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–1 SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193 – D3992, MARCH 1992 – REVISED APRIL 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Continuous input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Positive-peak input clamp current, IIK (VI > VCC) (tw < 1 µs, duty cycle < 20%) . . . . . . . . . . . . . . . . . 100 mA Negative-peak input clamp current, IIK (VI < 0) (tw < 1 µs, duty cycle < 20%) . . . . . . . . . . . . . . . . . . –100 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input negative-voltage rating may be exceeded if the input clamp-current rating is observed. recommended operating conditions MIN MAX VCC VIH Supply voltage 4.5 5.5 High-level input voltage 2.5 VIL VI Low-level input voltage TA Operating free-air temperature Input voltage UNIT V V 0 – 40 0.8 V VCC 85 °C V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IIL IIH VCC = 4.5 to 5.5 V, VCC = 4.5 to 5.5 V, VIKL VIKH ICC‡ IIN = –18 mA IIN = 18 mA ∆ICC§ Ci VCC = 5.5 V, One input at 3.4 V, VI = 0.8 V VI = 2.5 V MIN TA = 25°C TYP† MAX MIN MAX 0.15 0.3 0.9 0.1 1 mA – 0.2 – 0.5 –1.4 – 0.15 –1.5 mA –1.5 –1.5 V VCC + 2 4 VCC + 2 40 µA Inputs open Other inputs at VCC or GND 0.9 VI = VCC or GND 3 † All typical values are at VCC = 5 V. ‡ Inputs may be set high or low prior to the ICC measurement. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. 4–2 POST OFFICE BOX 655303 UNIT • DALLAS, TEXAS 75265 1 V mA pF SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193 – D3992, MARCH 1992 – REVISED APRIL 1993 TYPICAL CHARACTERISTICS FORWARD CURRENT vs INPUT VOLTAGE (LOWER CLAMPING DIODE) 60 5 55 0 50 –5 I F – Forward Current – mA I F – Forward Current – mA FORWARD CURRENT vs INPUT VOLTAGE (UPPER CLAMPING DIODE) 45 40 35 30 25 20 – 10 – 15 – 20 – 25 – 30 – 35 – 40 15 – 45 10 – 50 5 – 55 0 5.5 6 8 6.5 7 7.5 VI – Input Voltage – V 8.5 – 60 –2 9 –1.75 –1.5 –1.25 –1 – 0.75 – 0.5 – 0.25 VI – Input Voltage – V Figure 1 Figure 2 INPUT CURRENT vs INPUT VOLTAGE SUPPLY CURRENT vs INPUT VOLTAGE 1 5 0.8 4.5 0.6 4 I CC – Supply Current – mA I I – Input Current – mA 0 0.4 0.2 0 – 0.2 – 0.4 3.5 3 2.5 2 1.5 – 0.6 1 – 0.8 0.5 –1 0 0 1 2 3 4 VI – Input Voltage – V 5 6 0 0.5 Figure 3 1 1.5 2 2.5 3 3.5 4 4.5 5 VI – Input Voltage – V 5.5 Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–3 SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193 – D3992, MARCH 1992 – REVISED APRIL 1993 APPLICATION INFORMATION The SN74ACT1073 terminates the output of a driving device and holds the input of the driven device at the logic level of the driver output prior to establishment of the high-impedance state on that output (see Figure 5). Bus Typical Output Input CMOS Input D1 (external connection point) VCC 15 16 1 SN74ACT1073 5 6 GND Figure 5. Bus-Hold Application 4–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Output IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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