MCP3202
2.7V Dual Channel 12-Bit A/D Converter
with SPI® Serial Interface
FEATURES
•
•
1
2
3
4
CS/SHDN
CH0
CH1
VSS
8
7
6
5
VDD/VREF
CLK
DOUT
DIN
SOIC, TSSOP
1
2
3
4
CS/SHDN
CH0
CH1
VSS
MCP3202
•
•
•
•
•
•
PDIP
12-bit resolution
±1 LSB max DNL
±1 LSB max INL (MCP3202-B)
±2 LSB max INL (MCP3202-C)
Analog inputs programmable as single-ended or
pseudo-differential pairs
On-chip sample and hold
SPI® serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100ksps max. sampling rate at VDD = 5V
50ksps max. sampling rate at VDD = 2.7V
Low power CMOS technology
- 500nA typical standby current, 5µA max.
- 550µA max. active current at 5V
Industrial temp range: -40°C to +85°C
8-pin PDIP SOIC and TSSOP packages
MCP3202
•
•
•
•
•
PACKAGE TYPES
8
VDD/VREF
7
6
5
CLK
DOUT
DIN
APPLICATIONS
•
•
•
•
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
FUNCTIONAL BLOCK DIAGRAM
VDD
VSS
DESCRIPTION
The Microchip Technology Inc. MCP3202 is a successive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The
MCP3202 is programmable to provide a single
pseudo-differential input pair or dual single-ended
inputs. Differential Nonlinearity (DNL) is specified at
±1 LSB, and Integral Nonlinearity (INL) is offered in
±1 LSB (MCP3202-B) and ±2 LSB (MCP3202-C) versions. Communication with the device is done using a
simple serial interface compatible with the SPI protocol.
The device is capable of conversion rates of up to
100ksps at 5V and 50ksps at 2.7V. The MCP3202
device operates over a broad voltage range (2.7V 5.5V). Low current design permits operation with typical standby and active currents of only 500nA and
375µA, respectively. The MCP3202 is offered in 8-pin
PDIP, TSSOP and 150mil SOIC packages.
1999 Microchip Technology Inc.
CH0
CH1
Preliminary
Input
Channel
Mux
DAC
Comparator
12-Bit SAR
Sample
and
Hold
Control Logic
CS/SHDN
DIN
CLK
Shift
Register
DOUT
DS21034A-page 1
MCP3202
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
PIN FUNCTION TABLE
NAME
VDD.........................................................................7.0V
All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 seconds) .. +300°C
ESD protection on all pins ...................................> 4kV
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
FUNCTION
VDD/VREF
+2.7V to 5.5V Power Supply and
Reference Voltage Input
CH0
Channel 0 Analog Input
CH1
Channel 1 Analog Input
CLK
Serial Clock
DIN
Serial Data In
DOUT
Serial Data Out
CS/SHDN
Chip Select/Shutdown Input
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5.5V, VSS = 0V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps and fCLK = 18*fSAMPLE
unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
12
clock
cycles
CONDITIONS
Conversion Rate
Conversion Time
tCONV
Analog Input Sample Time
tSAMPLE
Throughput Rate
fSAMPLE
1.5
clock
cycles
100
50
ksps
ksps
VDD = VREF = 5V
VDD = VREF = 2.7V
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
INL
±0.75
±1
±1
±2
LSB
LSB
MCP3202-B
MCP3202-C
Differential Nonlinearity
DNL
±0.5
±1
LSB
No missing codes over
temperature
Offset Error
±1.25
±3
LSB
Gain Error
±1.25
±5
LSB
Dynamic Performance
Total Harmonic Distortion
-82
dB
VIN = 0.1V to 4.9V@1kHz
Signal to Noise and Distortion
(SINAD)
72
dB
VIN = 0.1V to 4.9V@1kHz
Spurious Free Dynamic Range
86
dB
VIN = 0.1V to 4.9V@1kHz
Analog Inputs
Input Voltage Range for CH0 or
CH1 in Single-Ended Mode
VSS
VREF
Input Voltage Range for IN+ in
Pseudo-Differential Mode
IN-
VREF+IN-
Input Voltage Range for IN- in
Pseudo-Differential Mode
VSS-100
VSS+100
mV
±1
µA
Leakage Current
.001
V
See Sections 3.1 and 4.1
See Sections 3.1 and 4.1
Switch Resistance
RSS
1K
Ω
See Figure 4-1
Sample Capacitor
CSAMPLE
20
pF
See Figure 4-1
DS21034A-page 2
Preliminary
1999 Microchip Technology Inc.
MCP3202
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5.5V, VSS = 0V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps and fCLK = 18*fSAMPLE
unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Digital Input/Output
Data Coding Format
Straight Binary
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
0.7 VDD
V
0.3 VDD
4.1
V
V
IOH = -1mA, VDD = 4.5V
0.4
V
IOL = 1mA, VDD = 4.5V
Input Leakage Current
ILI
-10
10
µA
VIN = VSS or VDD
Output Leakage Current
ILO
-10
10
µA
VOUT = VSS or VDD
CIN, COUT
10
pF
VDD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
Clock Frequency
fCLK
1.8
0.9
MHz
MHz
Clock High Time
tHI
250
ns
Clock Low Time
tLO
250
ns
tSUCS
100
ns
Pin Capacitance (All
Inputs/Outputs)
Timing Parameters
CS Fall To First Rising CLK
Edge
Data Input Setup Time
50
tSU
VDD = 5V (Note 2)
VDD = 2.7V (Note 2)
ns
Data Input Hold Time
tHD
50
ns
CLK Fall To Output Data Valid
tDO
200
ns
See Test Circuits, Figure 1-2
CLK Fall To Output Enable
tEN
200
ns
See Test Circuits, Figure 1-2
CS Rise To Output Disable
tDIS
100
ns
See Test Circuits, Figure 1-2
Note 1
CS Disable Time
tCSH
500
ns
DOUT Rise Time
tR
100
ns
See Test Circuits, Figure 1-2
Note 1
DOUT Fall Time
tF
100
ns
See Test Circuits, Figure 1-2
Note 1
5.5
V
Power Requirements
2.7
Operating Voltage
VDD
Operating Current
IDD
375
550
µA
VDD = 5.0V, DOUT unloaded
Standby Current
IDDS
0.5
5
µA
CS = VDD = 5.0V
Note 1: This parameter is guaranteed by characterization and not 100% tested.
Note 2: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
1999 Microchip Technology Inc.
Preliminary
DS21034A-page 3
MCP3202
tCSH
CS
tSUCS
tLO
tHI
CLK
tHD
tSU
DIN
MSB IN
tEN
DOUT
NULL BIT
FIGURE 1-1:
tR
tDO
tF
tDIS
MSB OUT
LSB
Serial Timing.
Load circuit for tDIS and tEN
Load circuit for tR, tF, tDO
Test Point
1.4V
VDD
3K
Test Point
DOUT
3K
tDIS Waveform 2
VDD/2
tEN Waveform
DOUT
100pF
CL = 100pF
Voltage Waveforms for tR, tF
VOH
VOL
DOUT
Voltage Waveforms for tEN
CS
tF
tR
tDIS Waveform 1
VSS
1
2
3
4
CLK
B11
DOUT
tEN
Voltage Waveforms for tDIS
Voltage Waveforms for tDO
CS
CLK
tDO
VIH
DOUT
Waveform 1*
DOUT
90%
TDIS
DOUT
Waveform 2†
10%
* Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control.
† Waveform 2 is for an output with internal conditions such that the output is low, unless disabled
by the output control.
FIGURE 1-2:
Test Circuits.
DS21034A-page 4
Preliminary
1999 Microchip Technology Inc.
MCP3202
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
2.0
Positive INL
INL (LSB)
INL (LSB)
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25°C
Negative INL
0
25
50
75
100
125
V DD = 2.7V
1.5
1.0
0.5
Positive INL
0.0
-0.5
-1.0
-1.5
-2.0
Negative INL
0
150
20
Sample Rate (ksps)
FIGURE 2-1:
Rate.
Integral Nonlinearity (INL) vs. Sample
80
100
1.0
FSAMPLE = 100ksps
0.8
FSAMPLE = 50ksps
0.8
Positive INL
0.6
Positive INL
0.6
0.4
0.4
INL (LSB)
INL (LSB)
60
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample
Rate (VDD = 2.7V).
1.0
0.2
0.0
-0.2
-0.4
0.2
0.0
-0.2
-0.4
Negative INL
-0.6
-0.6
-0.8
-0.8
Negative INL
-1.0
-1.0
3.0
3.5
4.0
4.5
2.5
5.0
3.0
FIGURE 2-2:
3.5
4.0
4.5
5.0
VDD(V)
VDD(V)
FIGURE 2-5:
Integral Nonlinearity (INL) vs. VDD.
1.0
0.8
1.0
0.8
0.6
0.4
0.6
INL (LSB)
INL (LSB)
40
Sample Rate (ksps)
0.2
0.0
-0.2
Integral Nonlinearity (INL) vs. VDD.
VDD = 2.7V
FSAMPLE = 50ksps
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.4
-0.6
-0.8
-1.0
-0.8
-1.0
0
0
512 1024 1536 2048 2560 3072 3584 4096
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code
(Representative Part).
1999 Microchip Technology Inc.
512 1024 1536 2048 2560 3072 3584 4096
Digital Code
Digital Code
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code
(Representative Part, VDD = 2.7V).
Preliminary
DS21034A-page 5
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25°C
1.0
1.0
0.6
0.6
0.4
0.4
0.2
0.0
Negative INL
-0.2
VDD = 2.7V
0.8
Positive INL
INL (LSB)
INL (LSB)
0.8
F SAMPLE = 50ksps
Positive INL
0.2
0.0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
Negative INL
-1.0
-1.0
-50
-25
0
25
50
75
-50
100
-25
0
Temperature (°C)
Integral
Nonlinearity
(INL)
vs.
75
100
(INL)
vs.
2.0
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
V DD = 2.7V
1.5
1.0
Positive DNL
Negative DNL
Positive DNL
0.5
0.0
-0.5
Negative DNL
-1.0
-1.5
-2.0
0
25
50
75
100
125
150
0
20
Sample Rate (ksps)
40
60
80
100
Sample Rate (ksps)
FIGURE 2-8: Differential Nonlinearity (DNL) vs.
Sample Rate.
FIGURE 2-11: Differential Nonlinearity (DNL) vs.
Sample Rate (VDD = 2.7V).
1.0
1.0
FSAMPLE = 100ksps
0.8
0.6
0.6
Positive DNL
0.4
0.2
0.0
-0.2
-0.4
FSAMPLE = 50ksps
0.8
DNL (LSB)
DNL (LSB)
50
FIGURE 2-10: Integral
Nonlinearity
Temperature (VDD = 2.7V).
DNL (LSB)
DNL (LSB)
FIGURE 2-7:
Temperature.
25
Temperature (°C)
Positive DNL
0.4
0.2
0.0
-0.2
-0.4
Negative DNL
-0.6
-0.6
-0.8
-0.8
Negative DNL
-1.0
-1.0
2.5
3.0
3.5
4.0
4.5
2.5
5.0
Differential Nonlinearity (DNL) vs. VDD.
DS21034A-page 6
3.5
4.0
4.5
5.0
VDD(V)
VDD(V)
FIGURE 2-9:
3.0
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VDD.
Preliminary
1999 Microchip Technology Inc.
MCP3202
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
DNL (LSB)
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25°C
0.2
0.0
-0.2
0.2
0.0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
VDD = 2.7V
F SAMPLE = 50ksps
-1.0
0
512
1024 1536 2048 2560 3072 3584 4096
0
512
1024 1536 2048 2560
Digital Code
FIGURE 2-16: Differential Nonlinearity (DNL) vs.
Code (Representative Part, VDD = 2.7V).
1.0
1.0
0.8
0.8
0.6
0.6
Positive DNL
DNL (LSB)
DNL (LSB)
FIGURE 2-13: Differential Nonlinearity (DNL) vs.
Code (Representative Part).
0.4
0.2
0.0
-0.2
Negative DNL
-0.4
VDD = 2.7V
FSAMPLE = 50ksps
Positive DNL
0.4
0.2
0.0
-0.2
Negative DNL
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
-50
-25
0
25
50
75
-50
100
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
FIGURE 2-14: Differential Nonlinearity (DNL) vs.
Temperature.
FIGURE 2-17: Differential Nonlinearity (DNL) vs.
Temperature (VDD = 2.7V).
2.0
2.0
1.8
Offset Error (LSB)
1.5
Gain Error (LSB)
3072 3584 4096
Digital Code
F SAMPLE = 10ksps
1.0
0.5
0.0
-0.5
-1.0
F SAMPLE = 100ksps
-1.5
FSAMPLE = 100ksps
1.6
FSAMPLE = 50ksps
1.4
1.2
1.0
0.8
0.6
FSAMPLE = 10ksps
0.4
0.2
F SAMPLE = 50ksps
-2.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
2.5
VDD(V)
FIGURE 2-15: Gain Error vs. VDD.
1999 Microchip Technology Inc.
3.0
3.5
4.0
4.5
5.0
VDD(V)
FIGURE 2-18: Offset Error vs. VDD.
Preliminary
DS21034A-page 7
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25°C
2.0
1.0
1.8
0.6
VDD = 2.7V
0.4
FSAMPLE = 50ksps
Offset Error (LSB)
Gain Error (LSB)
0.8
0.2
0.0
-0.2
-0.4
-0.6
VDD = 5V
1.4
F SAMPLE = 100ksps
1.2
1.0
0.8
VDD = 2.7V
0.6
F SAMPLE = 50ksps
0.4
VDD = 5V
-0.8
1.6
0.2
FSAMPLE = 100ksps
-1.0
0.0
-50
-25
0
25
50
75
100
-50
-25
0
Temperature (°C)
100
75
100
100
90
VDD = 5V
90
80
FSAMPLE = 100ksps
80
70
60
SINAD (dB)
SNR (dB)
50
FIGURE 2-22: Offset Error vs. Temperature.
FIGURE 2-19: Gain Error vs. Temperature.
VDD = 2.7V
50
FSAMPLE = 50ksps
40
30
VDD = 5V
FSAMPLE = 100ksps
70
60
50
VDD = 2.7V
40
FSAMPLE = 50ksps
30
20
20
10
10
0
0
1
10
100
1
10
Input Frequency (kHz)
100
Input Frequency (kHz)
FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input
Frequency.
FIGURE 2-23:
Signal to Noise and Distortion
(SINAD) vs. Input Frequency.
0
80
-10
VDD = 5V
70
-20
-30
-40
VDD = 2.7V
-50
FSAMPLE = 50ksps
SINAD (dB)
THD (dB)
25
Temperature (°C)
-60
-70
F SAMPLE = 100ksps
60
50
VDD = 2.7V
40
FSAMPLE = 50ksps
30
20
-80
VDD = 5V
-90
10
FSAMPLE = 100ksps
0
-100
1
10
-40
100
-30
-25
-20
-15
-10
-5
0
Input Signal Level (dB)
Input Frequency (kHz)
FIGURE 2-21: Total Harmonic Distortion (THD) vs.
Input Frequency.
DS21034A-page 8
-35
FIGURE 2-24:
Signal to Noise and Distortion
(SINAD) vs. Signal Level.
Preliminary
1999 Microchip Technology Inc.
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25°C
12.0
12.0
F SAMPLE = 50ksps
VDD = 5V
11.5
FSAMPLE = 100ksps
ENOB (rms)
ENOB (rms)
11.5
11.0
F SAMPLE = 100ksps
10.5
10.0
11.0
10.5
10.0
9.5
9.0
9.5
8.5
9.0
8.0
2.0
2.5
3.0
3.5
4.0
4.5
VDD = 2.7V
FSAMPLE = 50ksps
1
5.0
10
Input Frequency (kHz)
VDD (V)
FIGURE 2-25: Effective number of bits (ENOB) vs.
VDD.
FIGURE 2-28: Effective Number of Bits (ENOB) vs.
Input Frequency.
0
100
FSAMPLE = 100ksps
80
SFDR (dB)
Power Supply Rejection (dB)
VDD = 5V
90
70
60
50
VDD = 2.7V
40
FSAMPLE = 50ksps
30
20
10
0
1
10
-10
-20
-30
-40
-50
-60
-70
-80
100
1
10
Input Frequency (kHz)
FIGURE 2-26: Spurious Free
(SFDR) vs. Input Frequency.
Dynamic
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
Range
FSAMPLE = 100ksps
FINPUT = 9.985kHz
4096 points
10000
20000
30000
40000
50000
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
10000
VDD = 2.7V
FSAMPLE = 50ksps
FINPUT = 998.76Hz
4096 points
0
Frequency (Hz)
5000
10000
15000
20000
25000
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10kHz input
(Representative Part).
1999 Microchip Technology Inc.
1000
FIGURE 2-29: Power Supply Rejection (PSR) vs.
Ripple Frequency.
VDD = 5V
0
100
Ripple Frequency (kHz)
Amplitude (dB)
Amplitude (dB)
100
FIGURE 2-30: Frequency Spectrum of 1kHz input
(Representative Part, VDD = 2.7V).
Preliminary
DS21034A-page 9
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25°C
500
80
All points at F CLK = 1.8MHz except
450
60
IDDS (pA)
350
IDD (µA)
CS = VDD
70
at VDD = 2.5V, F CLK = 900kHz
400
300
250
200
150
50
40
30
20
100
10
50
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
6.0
2.5
3.0
3.5
4.5
5.0
5.5
6.0
FIGURE 2-34: IDDS vs. VDD.
FIGURE 2-31: IDD vs. VDD.
500
100.00
450
VDD = CS = 5V
400
VDD = 5V
10.00
350
300
IDDS (nA)
IDD (µA)
4.0
VDD (V)
VDD (V)
250
VDD = 2.7V
200
1.00
150
0.10
100
50
0
0.01
10
100
1000
10000
-50
-25
0
Clock Frequency (kHz)
FIGURE 2-32: IDD vs. Clock Frequency.
50
75
100
FIGURE 2-35: IDDS vs. Temperature.
2.0
500
Analog Input Leakage (nA)
VDD = 5V
450
F CLK = 1.8MHz
400
350
IDD (µA)
25
Temperature (°C)
300
250
VDD = 2.7V
200
FCLK = 900kHz
150
100
50
1.8
1.6
1.4
1.2
VDD = 5V
1.0
FCLK = 1.8MHz
0.8
0.6
0.4
0.2
0.0
0
-50
-25
0
25
50
75
-50
100
FIGURE 2-33: IDD vs. Temperature.
DS21034A-page 10
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
FIGURE 2-36: Analog Input leakage current vs.
Temperature.
Preliminary
1999 Microchip Technology Inc.
MCP3202
3.0
PIN DESCRIPTIONS
4.1
3.1
CH0/CH1
The MCP3202 device offers the choice of using the analog input channels configured as two single-ended
inputs or a single pseudo-differential input. Configuration is done as part of the serial command before each
conversion begins. When used in the psuedo-differential mode, CH0 and CH1 are programmed as the IN+
and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to
VREF (VREF + IN-). The IN- input is limited to ±100mV
from the VSS rail. The IN- input can be used to cancel
small signal common-mode noise which is present on
both the IN+ and IN- inputs.
Analog inputs for channels 0 and 1 respectively. These
channels can programmed to be used as two independent channels in single ended-mode or as a single
pseudo-differential input where one channel is IN+ and
one channel is IN-. See Section 5.0 for information on
programming the channel configuration.
3.2
CS/SHDN(Chip Select/Shutdown)
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a conversion and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions.
3.3
CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 for constraints on clock speed.
3.4
DIN (Serial Data Input)
The SPI port serial data input pin is used to clock in
input channel configuration data.
3.5
DOUT (Serial Data output)
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
4.0
DEVICE OPERATION
The MCP3202 A/D Converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the second rising edge of
the serial clock after the start bit has been received.
Following this sample time, the input switch of the converter opens and the device uses the collected charge
on the internal sample and hold capacitor to produce a
serial 12-bit digital output code. Conversion rates of
100ksps are possible on the MCP3202. See
Section 6.2 for information on minimum clock rates.
Communication with the device is done using a 3-wire
SPI-compatible interface.
Analog Inputs
For the A/D Converter to meet specification, the charge
holding capacitor (CSAMPLE) must be given enough time
to acquire a 12-bit accurate voltage level during the
1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
In this diagram, it is shown that the source impedance
(RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to
charge the capacitor, CSAMPLE. Consequently, larger
source impedances increase the offset, gain, and integral linearity errors of the conversion.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational amplifier such as the MCP601 which has a closed loop output impedance of tens of ohms. The adverse affects of
higher source impedances are shown in Figure 4-2.
When operating in the pseudo-differential mode, if the
voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more
than 1 LSB below VSS, then the voltage level at the IN+
input will have to go below VSS to see the 000h output
code. Conversely, if IN- is more than 1 LSB above VSS,
then the FFFh code will not be seen unless the IN+
input level goes above VREF level.
4.2
Digital Output Code
The digital output code produced by an A/D Converter
is a function of the input signal and the reference voltage. For the MCP3202, VDD is used as the reference
voltage. As the VDD level is reduced, the LSB size is
reduced accordingly. The theoretical digital output code
produced by the A/D Converter is shown below.
Digital Output Code = 4096 * VIN
VDD
where:
VIN = analog input voltage
VDD = supply voltage
1999 Microchip Technology Inc.
Preliminary
DS21034A-page 11
MCP3202
VDD
RS
Sampling
Switch
VT = 0.6V
CHx
CPIN
7pF
VA
VT = 0.6V
SS
ILEAKAGE
±1nA
RSS = 1kΩ
CSAMPLE
= DAC capacitance
= 20 pF
VSS
Legend
VA = Signal Source
RS = Source Impedance
CHx = Input Channel Pad
CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin
due to various junctions
SS = Sampling Switch
RSS = Sampling Switch Resistor
CSAMPLE = Sample/Hold Capacitance
Clock Frequency (MHz)
FIGURE 4-1:
Analog Input Model.
2.0
1.8
VDD = 5V
1.6
1.4
1.2
1.0
0.8
0.6
VDD = 2.7V
0.4
0.2
0.0
100
1000
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input
Resistance (RS) to maintain less than a 0.1 LSB
deviation in INL from nominal conditions.
DS21034A-page 12
Preliminary
1999 Microchip Technology Inc.
MCP3202
5.0
SERIAL COMMUNICATIONS
5.1
Overview
MSB first as shown in Figure 5-1. Data is always output
from the device on the falling edge of the clock. If all 12
data bits have been transmitted and the device continues to receive clocks while the CS is held low, (and
MSBF = 1), the device will output the conversion result
LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
Communication with the MCP3202 is done using a
standard SPI-compatible serial interface. Initiating
communication with the device is done by bringing the
CS line low. See Figure 5-1. If the device was powered
up with the CS pin low, it must be brought high and back
low to initiate communication. The first clock received
with CS low and DIN high will constitute a start bit. The
SGL/DIFF bit and the ODD/SIGN bit follow the start bit
and are used to select the input channel configuration.
The SGL/DIFF is used to select single ended or
psuedo-differential mode. The ODD/SIGN bit selects
which channel is used in single ended mode, and is
used to determine polarity in pseudo-differential mode.
Following the ODD/SIGN bit, the MSBF bit is transmitted to and is used to enable the LSB first format for the
device. If the MSBF bit is low, then the data will come
from the device in MSB first format and any further
clocks with CS low will cause the device to output
zeros. If the MSBF bit is high, then the device will output
the converted word LSB first after the word has been
transmitted in the MSB first format. See Figure 5-2.
Table 5-1 shows the configuration bits for the
MCP3202. The device will begin to sample the analog
input on the second rising edge of the clock, after the
start bit has been received. The sample period will end
on the falling edge of the third clock following the start
bit.
If necessary, it is possible to bring CS low and clock in
leading zeros on the DIN line before the start bit. This is
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
Section 6.1 for more details on using the MCP3202
devices with hardware SPI ports.
CONFIG
BITS
CHANNEL
SELECTION
SGL/
DIFF
ODD/
SIGN
0
SINGLE
ENDED MODE
1
0
+
1
1
PSEUDODIFFERENTIAL
MODE
0
0
IN+
IN-
0
1
IN-
IN+
TABLE 5-1:
GND
1
+
-
Configuration Bits for the MCP3202.
On the falling edge of the clock for the MSBF bit, the
device will output a low null bit. The next sequential
12 clocks will output the result of the conversion with
tCYC
tCYC
tCSH
CS
tSUCS
CLK
DIN
DOUT
Start SGL/ ODD/ MS
DIFF SIGN BF
HI-Z
Null
Bit B11
tSAMPLE
Start SGL/ ODD/
DIFF SIGN
Don’t Care
HI-Z
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0*
tCONV
tDATA**
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See
Figure 5-2 below for details on obtaining LSB first data.
** tDATA: during this time, the bias current and the comparator power down while the reference input becomes a high impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
1999 Microchip Technology Inc.
Preliminary
DS21034A-page 13
MCP3202
FIGURE 5-1:
Communication with the MCP3202 using MSB first format only.
tCYC
tCSH
CS
tSUCS
Power Down
HI-Z
DOUT
tSAMPLE
MSBF
SGL/
DIFF
DIN
ODD/
SIGN
Start
CLK
Don’t Care
HI-Z
Null
*
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
Bit
(MSB)
tDATA **
tCONV
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high impedance
node, leaving the CLK running to clock out LSB first data or zeroes.
FIGURE 5-2:
Communication with MCP3202 using LSB first format.
DS21034A-page 14
Preliminary
1999 Microchip Technology Inc.
MCP3202
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3202 with
Microcontroller (MCU) SPI Ports
which requires that the SCLK from the MCU idles in the
‘low’ state, while Figure 6-2 shows the similar case of
SPI Mode 1,1 where the clock idles in the ‘high’ state.
As shown in Figure 6-1, the first byte transmitted to the
A/D Converter contains seven leading zeros before the
start bit. Arranging the leading zeros this way produces
the output 12 bits to fall in positions easily manipulated
by the MCU. The MSB is clocked out of the A/D Converter on the falling edge of clock number 12. After the
second eight clocks have been sent to the device, the
MCU receive buffer will contain three unknown bits (the
output is at high impedance until the null bit is clocked
out), the null bit and the highest order four bits of the
conversion. After the third byte has been sent to the
device, the receive register will contain the lowest order
eight bits of the conversion results. Easier manipulation
of the converted data can be obtained by using this
method.
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the rising
edge. Depending on how communication routines are
used, it is very possible that the number of clocks
required for communication will not be a multiple of eight.
Therefore, it may be necessary for the MCU to send
more clocks than are actually required. This is usually
done by sending ‘leading zeros’ before the start bit,
which are ignored by the device. As an example,
Figure 6-1 and Figure 6-2 show how the MCP3202 can
be interfaced to a MCU with a hardware SPI port.
Figure 6-1 depicts the operation shown in SPI Mode 0,0,
CS
MCU latches data from A/D Converter
on rising edges of SCLK
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
B5
B4
21
22
23
24
B2
B1
B0
X
X
MSBF
SGL/
DIFF
Start
DIN
ODD/
SIGN
Data is clocked out of
A/D Converter on falling edges
Don’t Care
HI-Z
DOUT
NULL
BIT B11
B10
B9
B8
X
X
X
B7
B6
B3
Start
Bit
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
X
X
CS
X
X
X
X
X
X
X
X
X
SGL/ ODD/
MSBF
DIFF SIGN
1
X
X
X
X
Data stored into MCU receive register
after transmission of first 8 bits
X = Don’t Care Bits
FIGURE 6-1:
X
X
X
X
0
B11
(Null)
B10
B9
X
X
B7
B8
Data stored into MCU receive register
after transmission of second 8 bits
X
B6
X
B5
X
B4
X
B3
B2
B1
X
B0
Data stored into MCU receive register
after transmission of last 8 bits
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
MCU latches data from A/D Converter
on rising edges of SCLK
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
B5
B4
B3
B2
B1
B0
MCU Received Data
(Aligned with rising
edge of clock)
X = Don’t Care Bits
FIGURE 6-2:
MSBF
Don’t Care
HI-Z
DOUT
MCU Transmitted Data
(Aligned with falling
edge of clock)
SGL/
DIFF
Start
DIN
ODD/
SIGN
Data is clocked out of
A/D Converter on falling edges
NULL
BIT B11
B10
B9
X
X
B8
B6
B7
Start
Bit
0
0
X
0
X
0
X
0
X
X
X
SGL/ ODD/
MSBF
DIFF SIGN
1
0
0
X
X
Data stored into MCU receive register
after transmission of first 8 bits
X
X
X
X
X
0
B11
(Null)
B10
X
X
B9
B8
Data stored into MCU receive register
after transmission of second 8 bits
X
B7
X
B6
X
B5
X
B4
X
B3
X
B2
X
B1
B0
Data stored into MCU receive register
after transmission of last 8 bits
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
1999 Microchip Technology Inc.
Preliminary
DS21034A-page 15
MCP3202
6.2
Maintaining Minimum Clock Speed
6.4
When the MCP3202 initiates the sample period,
charge is stored on the sample capacitor. When the
sample period is complete, the device converts one bit
for each clock that is received. It is important for the
user to note that a slow clock rate will allow charge to
bleed off the sample cap while the conversion is taking
place. At 85°C (worst case condition), the part will
maintain proper charge on the sample capacitor for at
least 1.2ms after the sample period has ended. This
means that the time between the end of the sample
period and the time that all 12 data bits have been
clocked out must not exceed 1.2ms (effective clock frequency of 10kHz). Failure to meet this criteria may
induce linearity errors into the conversion outside the
rated specifications. It should be noted that during the
entire conversion cycle, the A/D Converter does not
require a constant clock speed or duty cycle, as long as
all timing specifications are met.
6.3
Buffering/Filtering the Analog Inputs
Layout Considerations
When laying out a printed circuit board for use with analog components, care should be taken to reduce noise
wherever possible. A bypass capacitor should always
be used with this device and should be placed as close
as possible to the device pin. A bypass capacitor value
of 1µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D Converters, refer to AN688 “Layout Tips for 12-Bit A/D Converter Applications”.
If the signal source for the A/D Converter is not a low
impedance source, it will have to be buffered or inaccurate conversion results may occur. It is also recommended that a filter be used to eliminate any signals
that may be aliased back into the conversion results.
This is illustrated in Figure 6-3 below where an op amp
is used to drive the analog input of the MCP3202. This
amplifier provides a low impedance output for the converter input and a low pass filter, which eliminates
unwanted high frequency noise.
VDD
Connection
Device 4
Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab™ software. FilterLab
will calculate capacitor and resistor values, as well as,
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”
VDD
10uF
4.096V
Reference
0.1µF
ADI
REF198
1µF
Tant. 0.1µF
VREF
Device 1
Device 3
Device 2
FIGURE 6-4: VDD traces arranged in a ‘Star’
configuration in order to reduce errors caused by
current return paths.
1µF
IN+
MCP3202
R1
VIN
C1
MCP601
IN-
+
-
R2
C2
R3
R4
FIGURE 6-3: The MCP601 Operational Amplifier is
used to implement a 2nd order anti-aliasing filter for
the signal being converted by the MCP3202.
DS21034A-page 16
FilterLab is a trademark of Microchip Technology Inc. in
the U.S.A and other countries. All rights reserved.
Preliminary
1999 Microchip Technology Inc.
MCP3202
MCP3202 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
MCP3202 - G
T
/P
Package:
Temperature
Range:
Performance
Grade:
Device:
P = PDIP (8 lead)
SN = SOIC (150 mil Body), 8 lead
ST = TSSOP, 8 lead (C Grade only)
I = –40°C to +85°C
B = ±1 LSB INL (TSSOP not available in this grade)
C = ±2 LSB INL
MCP3202 = 12-Bit Serial A/D Converter
MCP3202T = 12-Bit Serial A/D Converter on tape and reel
(SOIC and TSSOP packages only)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999 (480) 786-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
Preliminary
DS21034A-page 17
MCP3202
NOTES:
DS21034A-page 18
Preliminary
1999 Microchip Technology Inc.
MCP3202
NOTES:
1999 Microchip Technology Inc.
Preliminary
DS21034A-page 19
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design and wafer fabrication facilities in
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Company’s quality system processes and
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All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
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1999 Microchip Technology Inc.