MCP3204/3208
2.7V 4-Channel/8-Channel 12-Bit A/D Converters
with SPI® Serial Interface
FEATURES
•
•
•
•
•
•
CH0
CH1
CH2
CH3
NC
NC
DGND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
VDD
VREF
AGND
CLK
DOUT
DIN
CS/SHDN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VREF
AGND
CLK
DOUT
DIN
CS/SHDN
DGND
FUNCTIONAL BLOCK DIAGRAM
VDD
DESCRIPTION
VSS
VREF
The Microchip Technology Inc. MCP3204/3208
devices are successive approximation 12-bit Analog-to-Digital (A/D) Converters with on-board sample
and hold circuitry. The MCP3204 is programmable to
provide two pseudo-differential input pairs or four single-ended inputs. The MCP3208 is programmable to
provide four pseudo-differential input pairs or eight single-ended inputs. Differential Nonlinearity (DNL) is
specified at ±1 LSB, and Integral Nonlinearity (INL) is
offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB
(MCP3204/3208-C) versions. Communication with the
devices is done using a simple serial interface compatible with the SPI protocol. The devices are capable of
conversion rates of up to 100ksps. The MCP3204/3208
devices operate over a broad voltage range (2.7V 5.5V). Low current design permits operation with typical standby and active currents of only 500nA and
320µA, respectively. The MCP3204 is offered in 14-pin
PDIP, 150mil SOIC and TSSOP packages, and the
MCP3208 is offered in 16-pin PDIP and SOIC packages.
1999 Microchip Technology Inc.
14
13
12
11
10
9
8
PDIP, SOIC
APPLICATIONS
•
•
•
•
1
2
3
4
5
6
7
MCP3208
•
•
PDIP, SOIC, TSSOP
12-bit resolution
± 1 LSB max DNL
± 1 LSB max INL (MCP3204/3208-B)
± 2 LSB max INL (MCP3204/3208-C)
4 (MCP3204) or 8 (MCP3208) input channels
Analog inputs programmable as single-ended or
pseudo differential pairs
On-chip sample and hold
SPI® serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100ksps max. sampling rate at VDD = 5V
50ksps max. sampling rate at VDD = 2.7V
Low power CMOS technology
- 500 nA typical standby current, 2µA max.
- 400 µA max. active current at 5V
Industrial temp range: -40°C to +85°C
Available in PDIP, SOIC and TSSOP packages
MCP3204
•
•
•
•
•
•
PACKAGE TYPES
CH0
CH1
Input
Channel
Mux
DAC
CH7*
Preliminary
Comparator
12-Bit SAR
Sample
and
Hold
Control Logic
CS/SHDN DIN
CLK
Shift
Register
DOUT
*Note: Channels 5-7 available on MCP3208 Only
DS21298B-page 1
MCP3204/3208
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
PIN FUNCTION TABLE
NAME
FUNCTION
VDD
+2.7V to 5.5V Power Supply
VDD.........................................................................7.0V
All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 seconds) .. +300°C
ESD protection on all pins ...................................> 4kV
DGND
Digital Ground
AGND
Analog Ground
CH0-CH7
Analog Inputs
CLK
Serial Clock
DIN
Serial Data In
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
DOUT
Serial Data Out
CS/SHDN
Chip Select/Shutdown Input
VREF
Reference Voltage Input
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps and
fCLK = 20*fSAMPLE, unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
12
clock
cycles
CONDITIONS
Conversion Rate
Conversion Time
tCONV
Analog Input Sample Time
tSAMPLE
Throughput Rate
fSAMPLE
1.5
clock
cycles
100
50
ksps
ksps
VDD = VREF = 5V
VDD = VREF = 2.7V
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
INL
±0.75
±1
±1
±2
LSB
MCP3204/3208-B
MCP3204/3208-C
Differential Nonlinearity
DNL
±0.5
±1
LSB
No missing codes over
temperature
Offset Error
±1.25
±3
LSB
Gain Error
±1.25
±5
LSB
Dynamic Performance
Total Harmonic Distortion
-82
dB
VIN = 0.1V to 4.9V@1kHz
Signal to Noise and Distortion
(SINAD)
72
dB
VIN = 0.1V to 4.9V@1kHz
Spurious Free Dynamic
Range
86
dB
VIN = 0.1V to 4.9V@1kHz
VDD
V
Note 2
150
3
µA
µA
CS = VDD = 5V
V
Reference Input
Voltage Range
0.25
Current Drain
100
0.001
Analog Inputs
Input Voltage Range for
CH0-CH7 in Single-Ended
Mode
VSS
VREF
Input Voltage Range for IN+ In
pseudo-differential Mode
IN-
VREF+IN-
Input Voltage Range for IN- In
pseudo-differential Mode
VSS-100
VSS+100
mV
±1
µA
Leakage Current
DS21298B-page 2
0.001
Preliminary
1999 Microchip Technology Inc.
MCP3204/3208
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps and
fCLK = 20*fSAMPLE, unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Analog Inputs (Continued)
Switch Resistance
1K
Ω
See Figure 4-1
Sample Capacitor
20
pF
See Figure 4-1
Digital Input/Output
Data Coding Format
Straight Binary
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
0.7 VDD
V
0.3 VDD
4.1
V
V
IOH = -1mA, VDD = 4.5V
0.4
V
IOL = 1mA, VDD = 4.5V
Input Leakage Current
ILI
-10
10
µA
VIN = VSS or VDD
Output Leakage Current
ILO
-10
10
µA
VOUT = VSS or VDD
CIN, COUT
10
pF
VDD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
fCLK
2.0
1.0
MHz
MHz
Pin Capacitance
(All Inputs/Outputs)
Timing Parameters
Clock Frequency
Clock High Time
tHI
250
ns
Clock Low Time
tLO
250
ns
tSUCS
100
ns
CS Fall To First Rising CLK
Edge
VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
Data Input Setup Time
tSU
50
ns
Data Input Hold Time
tHD
50
ns
CLK Fall To Output Data Valid
tDO
200
ns
See Test Circuits, Figure 1-2
CLK Fall To Output Enable
tEN
200
ns
See Test Circuits, Figure 1-2
CS Rise To Output Disable
tDIS
100
ns
See Test Circuits, Figure 1-2
CS Disable Time
tCSH
500
ns
DOUT Rise Time
tR
100
ns
See Test Circuits, Figure 1-2
(Note 1)
DOUT Fall Time
tF
100
ns
See Test Circuits, Figure 1-2
(Note 1)
Power Requirements
Operating Voltage
VDD
5.5
V
Operating Current
IDD
2.7
320
225
400
µA
VDD = VREF = 5V, DOUT unloaded
VDD = VREF = 2.7V, DOUT unloaded
Standby Current
IDDS
0.5
2
µA
CS = VDD = 5.0V
Note 1: This parameter is guaranteed by characterization and not 100% tested.
Note 2: See graphs that relate linearity performance to VREF levels.
Note 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 3
MCP3204/3208
tCSH
CS
tSUCS
tLO
tHI
CLK
tHD
tSU
DIN
MSB IN
tEN
DOUT
NULL BIT
FIGURE 1-1:
tR
tDO
tF
tDIS
MSB OUT
LSB
Serial Interface Timing.
Load circuit for tDIS and tEN
Load circuit for tR, tF, tDO
1.4V
Test Point
VDD
3K
Test Point
DOUT
3K
tDIS Waveform 2
VDD/2
tEN Waveform
DOUT
100pF
CL = 100pF
Voltage Waveforms for tR, tF
VOH
VOL
DOUT
tF
tR
tDIS Waveform 1
VSS
Voltage Waveforms for tEN
CS
1
2
3
4
CLK
B11
DOUT
tEN
Voltage Waveforms for tDO
Voltage Waveforms for tDIS
CS
CLK
tDO
VIH
DOUT
Waveform 1*
90%
TDIS
DOUT
DOUT
10%
Waveform 2†
* Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control.
† Waveform 2 is for an output with internal conditions such that the output is low, unless disabled
by the output control.
FIGURE 1-2:
Test Circuits.
DS21298B-page 4
Preliminary
1999 Microchip Technology Inc.
MCP3204/3208
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25°C
1.0
2.0
0.8
Positive INL
0.6
1.0
INL (LSB)
0.4
INL (LSB)
VDD = VREF = 2.7V
1.5
0.2
0.0
-0.2
-0.4
Negative INL
Positive INL
0.5
0.0
-0.5
Negative INL
-1.0
-0.6
-1.5
-0.8
-2.0
-1.0
0
0
25
50
75
100
125
10
20
50
60
70
80
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample
Rate (VDD = 2.7V).
2.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
1.5
Positive INL
1.0
Positive INL
INL(LSB)
INL(LSB)
Integral Nonlinearity (INL) vs. Sample
Negative INL
0.5
0.0
-0.5
-1.0
Negative INL
-1.5
-2.0
0
1
2
3
4
5
6
0.0
0.5
1.0
FIGURE 2-2:
1.5
2.0
2.5
3.0
VREF (V)
VREF (V)
FIGURE 2-5:
(VDD = 2.7V).
Integral Nonlinearity (INL) vs. VREF.
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
INL (LSB)
INL (LSB)
40
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-1:
Rate.
30
150
0.2
0.0
-0.2
VDD = VREF = 2.7V
FSAMPLE = 50ksps
0.2
0.0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
Integral Nonlinearity (INL) vs. VREF
-1.0
0
512
1024
1536
2048 2560
3072 3584
4096
0
Digital Code
1024 1536
2048
2560
3072 3584
4096
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code
(Representative Part).
1999 Microchip Technology Inc.
512
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code
(Representative Part, VDD = 2.7V).
Preliminary
DS21298B-page 5
MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25°C
1.0
1.0
0.6
0.6
0.4
0.4
0.2
0.0
Negative INL
-0.2
VDD = VREF = 2.7V
0.8
Positive INL
INL (LSB)
INL (LSB)
0.8
Positive INL
0.2
0.0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
F SAMPLE = 50ksps
Negative INL
-1.0
-50
-25
0
25
50
75
100
-50
-25
0
Temperature (°C)
FIGURE 2-7:
Temperature.
Integral
Nonlinearity
50
75
100
Temperature (°C)
(INL)
vs.
FIGURE 2-10: Integral
Nonlinearity
Temperature (VDD = 2.7V).
1.0
2.0
0.8
1.5
0.6
(INL)
vs.
VDD = VREF = 2.7V
1.0
0.4
Positive DNL
DNL (LSB)
DNL (LSB)
25
0.2
0.0
-0.2
-0.4
0.0
-0.5
Negative DNL
-1.0
Negative DNL
-0.6
Positive DNL
0.5
-1.5
-0.8
-1.0
-2.0
0
25
50
75
100
125
150
0
10
Sample Rate (ksps)
20
30
40
50
60
70
Sample Rate (ksps)
FIGURE 2-8: Differential Nonlinearity (DNL) vs.
Sample Rate.
FIGURE 2-11: Differential Nonlinearity (DNL) vs.
Sample Rate (VDD = 2.7V).
3.0
3.0
2.0
2.0
1.0
DNL (LSB)
DNL (LSB)
VDD = VREF= 2.7V
Positive DNL
0.0
Negative DNL
-1.0
FSAMPLE = 50ksps
Positive DNL
1.0
0.0
Negative DNL
-1.0
-2.0
-2.0
-3.0
-3.0
0
1
2
3
4
5
0.0
VREF (V)
FIGURE 2-9:
VREF.
1.0
1.5
2.0
2.5
3.0
VREF(V)
Differential Nonlinearity (DNL) vs.
DS21298B-page 6
0.5
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF
(VDD = 2.7V).
Preliminary
1999 Microchip Technology Inc.
MCP3204/3208
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
DNL (LSB)
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25°C
0.2
0.0
-0.2
VDD = VREF = 2.7V
FSAMPLE = 50ksps
0.2
0.0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
Digital Code
FIGURE 2-13: Differential Nonlinearity (DNL) vs.
Code (Representative Part).
1.0
0.8
0.8
DNL (LSB)
DNL (LSB)
Positive DNL
0.2
0.0
-0.2
4096
VDD = VREF = 2.7V
0.4
Positive DNL
0.2
0.0
-0.2
-0.4
-0.4
Negative DNL
Negative DNL
-0.6
-0.8
-0.8
-1.0
-1.0
-50
-25
0
25
50
75
-50
100
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
FIGURE 2-14: Differential Nonlinearity (DNL) vs.
Temperature.
FIGURE 2-17: Differential Nonlinearity (DNL) vs.
Temperature (VDD = 2.7V).
20
4
18
3
VDD = 2.7V
2
Offset Error (LSB)
Gain Error (LSB)
3584
FSAMPLE = 50ksps
0.6
0.6
-0.6
3072
FIGURE 2-16: Differential Nonlinearity (DNL) vs.
Code (Representative Part, VDD = 2.7V).
1.0
0.4
2048 2560
Digital Code
F SAMPLE = 50ksps
1
0
-1
VDD = 5V
FSAMPLE = 100ksps
-2
16
VDD = 5V
14
F SAMPLE = 100ksps
12
10
8
VDD = 2.7V
6
F SAMPLE = 50ksps
4
2
-3
0
-4
0
1
2
3
4
0
5
1999 Microchip Technology Inc.
2
3
4
5
VREF (V)
VREF(V)
FIGURE 2-15: Gain Error vs. VREF.
1
FIGURE 2-18: Offset Error vs. VREF.
Preliminary
DS21298B-page 7
MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25°C
2.0
0.2
-0.2
VDD = VREF = 2.7V
1.8
FSAMPLE = 50ksps
1.6
Offset Error (LSB)
Gain Error (LSB)
0.0
-0.4
-0.6
-0.8
-1.0
VDD = VREF = 5V
-1.2
FSAMPLE = 100ksps
-1.4
VDD = VREF = 5V
FSAMPLE = 100ksps
1.4
1.2
1.0
VDD = VREF = 2.7V
0.8
FSAMPLE = 50ksps
0.6
0.4
0.2
-1.6
0.0
-1.8
-50
-25
0
25
50
75
100
-50
-25
0
VDD = VREF = 5V
FSAMPLE = 100ksps
VDD = VREF = 2.7V
FSAMPLE = 50ksps
1
10
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100
100
VDD = VREF = 5V
VDD = VREF = 2.7V
F SAMPLE = 50ksps
1
10
100
Input Frequency (kHz)
FIGURE 2-20: Signal to Noise (SNR) vs. Input
Frequency.
FIGURE 2-23: Signal to Noise
(SINAD) vs. Input Frequency.
and
Distortion
80
VDD = VREF = 5V
70
F SAMPLE = 50ksps
-50
-60
-70
-80
-90
-100
FSAMPLE = 100ksps
60
VDD = VREF = 2.7V
SINAD (dB)
THD (dB)
75
FSAMPLE = 100ksps
Input Frequency (kHz)
0
-10
-20
-30
-40
50
FIGURE 2-22: Offset Error vs. Temperature.
SINAD (dB)
SNR (dB)
FIGURE 2-19: Gain Error vs. Temperature.
100
90
80
70
60
50
40
30
20
10
0
25
Temperature (°C)
Temperature (°C)
50
VDD = VREF = 2.7V
FSAMPLE = 50ksps
40
30
20
VDD = VREF = 5V
10
FSAMPLE = 100ksps
0
1
10
100
-40
-30
-25
-20
-15
-10
-5
0
Input Signal Level (dB)
Input Frequency (kHz)
FIGURE 2-21: Total Harmonic Distortion (THD) vs.
Input Frequency.
DS21298B-page 8
-35
FIGURE 2-24: Signal to Noise
(SINAD) vs. Input Signal Level.
Preliminary
and
Distortion
1999 Microchip Technology Inc.
MCP3204/3208
12.0
12.00
11.75
11.50
11.25
11.00
10.75
10.50
10.25
10.00
9.75
9.50
9.25
9.00
11.5
ENOB (rms)
ENOB (rms)
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25°C
VDD = VREF = 5V
VDD = VREF = 2.7V
FSAMPLE =100ksps
FSAMPLE = 50ksps
11.0
10.5
10.0
VDD = VREF = 5V
F SAMPLE = 100ksps
9.5
VDD = VREF = 2.7V
9.0
F SAMPLE = 50ksps
8.5
8.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1
10
VREF (V)
Input Frequency (kHz)
FIGURE 2-25: Effective Number of Bits (ENOB) vs.
VREF.
FIGURE 2-28: Effective Number of Bits (ENOB) vs.
Input Frequency.
0
90
VDD = VREF = 5V
80
FSAMPLE = 100ksps
Power Supply Rejection (dB)
SFDR (dB)
100
70
60
50
VDD = VREF = 2.7V
40
FSAMPLE = 50ksps
30
20
10
0
1
10
-10
-20
-30
-40
-50
-60
-70
-80
1
100
10
FIGURE 2-26: Spurious Free
(SFDR) vs. Input Frequency.
Dynamic
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
Range
Amplitude (dB)
FSAMPLE = 100ksps
FINPUT = 9.985kHz
4096 points
10000
20000
30000
40000
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
10000
VDD = VREF = 2.7V
FSAMPLE = 50ksps
FINPUT = 998.76Hz
4096 points
0
50000
5000
10000
15000
20000
25000
Frequency (Hz)
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10kHz input
(Representative Part).
1999 Microchip Technology Inc.
1000
FIGURE 2-29: Power Supply Rejection (PSR) vs.
Ripple Frequency.
VDD = VREF = 5V
0
100
Ripple Frequency (kHz)
Input Frequency (kHz)
Amplitude (dB)
100
FIGURE 2-30: Frequency Spectrum of 1kHz input
(Representative Part, VDD = 2.7V).
Preliminary
DS21298B-page 9
MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25°C
500
100
VREF = VDD
450
All points at FCLK = 2MHz except
80
at VREF = VDD = 2.5V, F CLK = 1MHz
at VREF = VDD = 2.5V, F CLK = 1MHz
70
IREF (µA)
350
IDD (µA)
VREF = VDD
90
All points at FCLK = 2MHz except
400
300
250
200
60
50
40
150
30
100
20
50
10
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
6.0
2.5
3.0
3.5
5.0
5.5
6.0
FIGURE 2-34: IREF vs. VDD.
FIGURE 2-31: IDD vs. VDD.
400
100
350
90
VDD = VREF = 5V
80
300
70
VDD = VREF = 5V
IREF (µA)
IDD (µA)
4.5
VDD (V)
VDD (V)
250
200
VDD = VREF = 2.7V
150
60
50
40
VDD = VREF = 2.7V
30
100
20
50
10
0
0
10
100
1000
10
10000
100
1000
10000
Clock Frequency (kHz)
Clock Frequency (kHz)
FIGURE 2-32: IDD vs. Clock Frequency.
FIGURE 2-35: IREF vs. Clock Frequency.
100
400
VDD = VREF = 5V
350
VDD = VREF = 5V
90
FCLK = 2MHz
80
300
FCLK = 2MHz
70
250
IREF (µA)
IDD (µA)
4.0
200
VDD = VREF = 2.7V
150
FCLK = 1MHz
60
50
40
VDD = VREF = 2.7V
30
100
FCLK = 1MHz
20
50
10
0
-50
-25
0
25
50
75
0
100
-50
Temperature (°C)
FIGURE 2-33: IDD vs. Temperature.
DS21298B-page 10
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-36: IREF vs. Temperature.
Preliminary
1999 Microchip Technology Inc.
MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25°C
2.0
Analog Input Leakage (nA)
80
VREF = CS = VDD
70
IDDS (pA)
60
50
40
30
20
10
0
1.8
1.6
1.4
1.2
VDD = VREF = 5V
1.0
FCLK = 2MHz
0.8
0.6
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-50
VDD (V)
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-37: IDDS vs. VDD.
FIGURE 2-39: Analog Input Leakage Current vs.
Temperature.
100.00
VDD = VREF = CS = 5V
IDDS (nA)
10.00
1.00
0.10
0.01
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-38: IDDS vs. Temperature.
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 11
MCP3204/3208
3.0
PIN DESCRIPTIONS
4.1
3.1
CH0 - CH7
The MCP3204/3208 devices offer the choice of using
the analog input channels configured as single-ended
inputs or pseudo-differential pairs. The MCP3204 can
be configured to provide two pseudo-differential input
pairs or four single-ended inputs. the MCP3208 can be
configured to provide four pseudo-differential input
pairs or eight single-ended inputs. Configuration is
done as part of the serial command before each conversion begins. When used in the pseudo-differential
mode, each channel pair (i.e., CH0 and CH1, CH2 and
CH3 etc.) are programmed as the IN+ and IN- inputs as
part of the command string transmitted to the device.
The IN+ input can range from IN- to (VREF + IN-). The
IN- input is limited to ±100mV from the VSS rail. The INinput can be used to cancel small signal common-mode noise which is present on both the IN+ and
IN- inputs.
When operating in the pseudo-differential mode, if the
voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more
than 1 LSB below VSS, then the voltage level at the IN+
input will have to go below VSS to see the 000h output
code. Conversely, if IN- is more than 1 LSB above VSS,
then the FFFh code will not be seen unless the IN+
input level goes above VREF level.
For the A/D Converter to meet specification, the charge
holding capacitor, (CSAMPLE) must be given enough time
to acquire a 12-bit accurate voltage level during the 1.5
clock cycle sampling period. The analog input model is
shown in Figure 4-1.
In this diagram it is shown that the source impedance
(RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to
charge the capacitor, CSAMPLE. Consequently, larger
source impedances increase the offset, gain, and integral linearity errors of the conversion. See Figure 4-2.
Analog inputs for channels 0 - 7 respectively for the
multiplexed inputs. Each pair of channels can be programmed to be used as two independent channels in
single ended-mode or as a single pseudo-differential
input where one channel is IN+ and one channel is IN-.
See Section 4.1 and Section 5.0 for information on programming the channel configuration.
3.2
CS/SHDN(Chip Select/Shutdown)
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a conversion and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions.
3.3
CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 for constraints on clock speed.
3.4
DIN (Serial Data Input)
The SPI port serial data input pin is used to load channel configuration data into the device.
3.5
DOUT (Serial Data output)
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
3.6
AGND
Analog ground connection to internal analog circuitry.
3.7
DGND
Digital ground connection to internal digital circuitry.
4.0
DEVICE OPERATION
The MCP3204/3208 A/D Converters employ a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the fourth rising edge of the
serial clock after the start bit has been received. Following this sample time, the device uses the collected
charge on the internal sample and hold capacitor to
produce a serial 12-bit digital output code. Conversion
rates of 100ksps are possible on the MCP3204/3208.
See Section 6.2 for information on minimum clock
rates. Communication with the device is done using a
4-wire SPI-compatible interface.
DS21298B-page 12
Analog Inputs
4.2
Reference Input
For each device in the family, the reference input (VREF)
determines the analog input voltage range. As the reference input is reduced, the LSB size is reduced
accordingly. The theoretical digital output code produced by the A/D Converter is a function of the analog
input signal and the reference input as shown below.
Digital Output Code = 4096 * VIN
VREF
where:
VIN = analog input voltage
VREF = reference voltage
When using an external voltage reference device, the
system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a
direct effect on the operation of the A/D Converter.
Preliminary
1999 Microchip Technology Inc.
MCP3204/3208
VDD
RS
Sampling
Switch
SS RSS = 1kΩ
VT = 0.6V
CHx
CPIN
7pF
VA
VT = 0.6V
ILEAKAGE
± 1 nA
CSAMPLE
= DAC capacitance
= 20 pF
VSS
Legend
VA = Signal Source
RS = Source Impedance
CHx = Input Channel Pad
CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin
due to various junctions
SS = Sampling Switch
RSS = Sampling Switch Resistor
CSAMPLE = Sample/Hold Capacitance
FIGURE 4-1: Analog Input Model
Clock Frequency (MHz)
2.5
VDD = 5V
2.0
1.5
1.0
VDD = 2.7V
0.5
0.0
100
1000
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input
resistance (RS) to maintain less than a 0.1LSB
deviation in INL from nominal conditions.
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 13
MCP3204/3208
5.0
SERIAL COMMUNICATIONS
Communication with the MCP3204/3208 devices is
done using a standard SPI-compatible serial interface.
Initiating communication with either device is done by
bringing the CS line low. See Figure 5-1. If the device
was powered up with the CS pin low, it must be brought
high and back low to initiate communication. The first
clock received with CS low and DIN high will constitute
a start bit. The SGL/DIFF bit follows the start bit and will
determine if the conversion will be done using single
ended or differential input mode. The next three bits
(D0, D1 and D2) are used to select the input channel
configuration. Table 5-1 and Table 5-2 show the configuration bits for the MCP3204 and MCP3208, respectively. The device will begin to sample the analog input
on the fourth rising edge of the clock after the start bit
has been received. The sample period will end on the
falling edge of the fifth clock following the start bit.
CONTROL BIT
SELECTIONS
CONTROL BIT
SELECTIONS
INPUT
CONFIGURATION
CHANNEL
SELECTION
D2
D1
D0
1
0
0
0
single ended
CH0
1
0
0
1
single ended
CH1
1
0
1
0
single ended
CH2
1
0
1
1
single ended
CH3
1
1
0
0
single ended
CH4
1
1
0
1
single ended
CH5
1
1
1
0
single ended
CH6
1
1
1
1
single ended
CH7
0
0
0
0
differential
CH0 = IN+
CH1 = IN-
0
0
0
1
differential
CH0 = INCH1 = IN+
0
0
1
0
differential
CH2 = IN+
CH3 = IN-
0
0
1
1
differential
CH2 = INCH3 = IN+
0
1
0
0
differential
CH4 = IN+
CH5 = IN-
0
1
0
1
differential
CH4 = INCH5 = IN+
0
1
1
0
differential
CH6 = IN+
CH7 = IN-
0
1
1
1
differential
CH6 = INCH7 = IN+
After the D0 bit is input, one more clock is required to
complete the sample and hold period (DIN is a don’t
care for this clock). On the falling edge of the next clock,
the device will output a low null bit. The next 12 clocks
will output the result of the conversion with MSB first as
shown in Figure 5-1. Data is always output from the
device on the falling edge of the clock. If all 12 data bits
have been transmitted and the device continues to
receive clocks while the CS is held low, the device will
output the conversion result LSB first as shown in
Figure 5-2. If more clocks are provided to the device
while CS is still low (after the LSB first data has been
transmitted), the device will clock out zeros indefinitely.
If necessary, it is possible to bring CS low and clock in
leading zeros on the DIN line before the start bit. This is
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
Section 6.1 for more details on using the
MCP3204/3208 devices with hardware SPI ports.
INPUT
CONFIGURATION
SINGLE/
DIFF
TABLE 5-2:
Configuration Bits for the MCP3208.
CHANNEL
SELECTION
SINGLE/
DIFF
D2*
D1
D0
1
X
0
0
single ended
CH0
1
X
0
1
single ended
CH1
1
X
1
0
single ended
CH2
1
X
1
1
single ended
CH3
0
X
0
0
differential
CH0 = IN+
CH1 = IN-
0
X
0
1
differential
CH0 = INCH1 = IN+
0
X
1
0
differential
CH2 = IN+
CH3 = IN-
0
X
1
1
differential
CH2 = INCH3 = IN+
*D2 is don’t care for MCP3204
TABLE 5-1:
Configuration Bits for the MCP3204.
DS21298B-page 14
Preliminary
1999 Microchip Technology Inc.
MCP3204/3208
tCYC
tCYC
tCSH
CS
tSUCS
CLK
Start SGL/ D2
DIFF
DIN
D1
HI-Z
DOUT
Start SGL/ D2
DIFF
Don’t Care
D0
Null
Bit
HI-Z
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 *
tCONV
tSAMPLE
tDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB
first data, then followed with zeros indefinitely. See Figure 5-2 below.
** tDATA: during this time, the bias current and the comparator power down while the reference input becomes
a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-1:
Communication with the MCP3204 or MCP3208.
tCYC
tCSH
CS
tSUCS
Power Down
CLK
Start
DIN
Don’t Care
D2 D1 D0
SGL/
DIFF
DOUT
* HI-Z
Null
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
Bit
HI-Z
(MSB)
tSAMPLE
tCONV
tDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros
indefinitely.
** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a
high impedance node, leaving the CLK running to clock out LSB first data or zeroes.
FIGURE 5-2:
Communication with MCP3204 or MCP3208 in LSB First Format.
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 15
MCP3204/3208
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3204/3208 with
Microcontroller (MCU) SPI Ports
As shown in Figure 6-1, the first byte transmitted to the
A/D Converter contains five leading zeros before the
start bit. Arranging the leading zeros this way produces
the output 12 bits to fall in positions easily manipulated
by the MCU. The MSB is clocked out of the A/D Converter on the falling edge of clock number 12. After the
second eight clocks have been sent to the device, the
MCUs receive buffer will contain three unknown bits
(the output is at high impedance for the first two clocks),
the null bit and the highest order four bits of the conversion. After the third byte has been sent to the device, the
receive register will contain the lowest order eight bits of
the conversion results. Easier manipulation of the converted data can be obtained by using this method.
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the rising
edge. Because communication with the MCP3204/3208
devices may not need multiples of eight clocks, it will be
necessary to provide more clocks than are required.
This is usually done by sending ‘leading zeros’ before
the start bit. As an example, Figure 6-1 and Figure 6-2
shows how the MCP3204/3208 can be interfaced to a
MCU with a hardware SPI port. Figure 6-1 depicts the
operation shown in SPI Mode 0,0 which requires that the
SCLK from the MCU idles in the ‘low’ state, while
Figure 6-2 shows the similar case of SPI Mode 1,1
where the clock idles in the ‘high’ state.
CS
Figure 6-2 shows the same thing in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
MCU latches data from A/D Converter
on rising edges of SCLK
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
B5
B4
21
22
23
24
B2
B1
B0
Data is clocked out of
A/D Converter on falling edges
SGL/
DIFF
Start
DIN
D2
DO
D1
Don’t Care
HI-Z
DOUT
NULL
BIT B11
B10
B9
B8
X
X
X
X
B7
B6
B3
Start
Bit
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
0
0
?
0
?
0
?
0
?
SGL/
DIFF
1
?
?
D2
?
DO
D1
?
?
Data stored into MCU receive register
after transmission of first 8 bits
?
?
X
0
B11
(Null)
B10
B9
X
X
X
B7
B8
Data stored into MCU receive register
after transmission of second 8 bits
B6
X
B5
X
X
B4
X
B3
B2
X
X
B1
B0
Data stored into MCU receive register
after transmission of last 8 bits
X = Don’t Care Bits
FIGURE 6-1:
CS
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
MCU latches data from A/D Converter
on rising edges of SCLK
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
B5
B4
B3
B2
B1
B0
Data is clocked out of
A/D Converter on falling edges
SGL/
Start DIFF
DIN
D2
D1
DO
Don’t Care
HI-Z
DOUT
NULL
BIT B11
B10
B9
X
X
B8
B6
B7
Start
Bit
MCU Transmitted Data
(Aligned with falling
edge of clock)
0
MCU Received Data
(Aligned with rising
edge of clock)
0
?
0
?
0
?
0
?
1
?
SGL/
DIFF
?
D2
?
DO
D1
?
Data stored into MCU receive register
after transmission of first 8 bits
?
X
?
X
?
X
0
B11
(Null)
B10
X
X
B9
B8
Data stored into MCU receive register
after transmission of second 8 bits
X
B7
X
B6
X
B5
X
B4
X
B3
X
B2
X
B1
B0
Data stored into MCU receive register
after transmission of last 8 bits
X = Don’t Care Bits
FIGURE 6-2:
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
DS21298B-page 16
Preliminary
1999 Microchip Technology Inc.
MCP3204/3208
6.2
Maintaining Minimum Clock Speed
6.4
When the MCP3204/3208 initiates the sample period,
charge is stored on the sample capacitor. When the
sample period is complete, the device converts one bit
for each clock that is received. It is important for the
user to note that a slow clock rate will allow charge to
bleed off the sample capacitor while the conversion is
taking place. At 85°C (worst case condition), the part
will maintain proper charge on the sample capacitor for
at least 1.2ms after the sample period has ended. This
means that the time between the end of the sample
period and the time that all 12 data bits have been
clocked out must not exceed 1.2ms (effective clock frequency of 10kHz). Failure to meet this criterion may
induce linearity errors into the conversion outside the
rated specifications. It should be noted that during the
entire conversion cycle, the A/D Converter does not
require a constant clock speed or duty cycle, as long as
all timing specifications are met.
6.3
Buffering/Filtering the Analog Inputs
Layout Considerations
When laying out a printed circuit board for use with analog components, care should be taken to reduce noise
wherever possible. A bypass capacitor should always
be used with this device and should be placed as close
as possible to the device pin. A bypass capacitor value
of 1µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating return current paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D Converters, refer to AN688 “Layout Tips for 12-Bit A/D Converter Applications”.
If the signal source for the A/D Converter is not a low
impedance source, it will have to be buffered or inaccurate conversion results may occur. See Figure 4-2. It is
also recommended that a filter be used to eliminate any
signals that may be aliased back in to the conversion
results. This is illustrated in Figure 6-3 where an op
amp is used to drive the analog input of the
MCP3204/3208. This amplifier provides a low impedance source for the converter input and a low pass filter, which eliminates unwanted high frequency noise.
VDD
Connection
Device 4
Low pass (anti-aliasing) filters can be designed using
Microchip’s free interactive FilterLab™ software. FilterLab will calculate capacitor and resistors values, as
well as determine the number of poles that are required
for the application. For more information on filtering signals, see the application note AN699 “Anti-Aliasing
Analog Filters for Data Acquisition Systems.”
VDD
10µF
4.096V
Reference
0.1µF
1µF
Tant. 0.1µF
ADI
REF198
VREF
Device 1
Device 3
Device 2
FIGURE 6-4: VDD traces arranged in a ‘Star’
configuration in order to reduce errors caused by
current return paths.
1µF
IN+
MCP3204
R1
VIN
C1
MCP601
IN-
+
-
R2
C2
R3
R4
FIGURE 6-3: The MCP601 Operational Amplifier is
used to implement a 2nd order anti-aliasing filter for
the signal being converted by the MCP3204.
1999 Microchip Technology Inc.
FilterLab is a trademark of Microchip Technology Inc. in
the U.S.A and other countries. All rights reserved.
Preliminary
DS21298B-page 17
MCP3204/3208
6.5
Utilizing the Digital and Analog
Ground Pins
The MCP3204/3208 devices provide both digital and
analog ground connections to provide another means
of noise reduction. As shown in Figure 6-5, the analog
and digital circuitry is separated internal to the device.
This reduces noise from the digital portion of the device
being coupled into the analog portion of the device. The
two grounds are connected internally through the substrate which has a resistance of 5 -10 Ω.
If no ground plane is utilized, then both grounds must
be connected to VSS on the board. If a ground plane is
available, both digital and analog ground pins should
be connected to the analog ground plane. If both an
analog and a digital ground plane are available, both
the digital and the analog ground pins should be connected to the analog ground plane. Following these
steps will reduce the amount of digital noise from the
rest of the board being coupled into the A/D Converter.
VDD
Digital Side
Analog Side
-SPI Interface
-Sample Cap
-Shift Register
-Capacitor Array
-Control Logic
-Comparator
Substrate
5 - 10 Ω
Digital
Ground Pin
FIGURE 6-5:
Ground Pins.
Analog
Ground Pin
Separation of Analog and Digital
DS21298B-page 18
Preliminary
1999 Microchip Technology Inc.
MCP3204/3208
MCP3204 PRODUCT IDENTIFICATION SYSTEMS
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
MCP3204 - G
T
/P
Package:
Temperature
Range:
Performance
Grade:
Device:
P = PDIP (14 lead)
SL = SOIC (150 mil Body), 14 lead
ST = TSSOP, 14 lead (C Grade only)
I = –40°C to +85°C
B = ±1 LSB INL (TSSOP not available in this grade)
C = ±2 LSB INL
MCP3204 = 4-Channel 12-Bit Serial A/D Converter
MCP3204T = 4-Channel 12-Bit Serial A/D Converter on tape and reel
(SOIC and TSSOP packages only)
MCP3208 PRODUCT IDENTIFICATION SYSTEMS
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
MCP3208 - G
T
/P
Package:
Temperature
Range:
Performance
Grade:
Device:
P = PDIP (16 lead)
SL = SOIC (150 mil Body), 16 lead
I = –40°C to +85°C
B = ±1 LSB INL (TSSOP not available in this grade)
C = ±2 LSB INL
MCP3208 = 8-Channel 12-Bit Serial A/D Converter
MCP3208T = 8-Channel 12-Bit Serial A/D Converter on tape and reel
(SOIC packages only)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999, (480) 786-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 19
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
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Tel: 905-405-6279 Fax: 905-405-6253
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Atlanta
Microchip Asia Pacific
Unit 2101, Tower 2
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
ASIA/PACIFIC
Hong Kong
ASIA/PACIFIC (continued)
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Tel: 86-10-85282100 Fax: 86-10-85282104
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
India
Denmark
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Korea
Germany
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Shanghai
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Italy
11/15/99
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.