SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop Excellent VCO Frequency Linearity VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption Optimized Power-Supply Voltage Range From 3 V to 5.5 V Wide Operating Temperature Range . . . –40°C to 125°C Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D, DGV, NS, OR PW PACKAGE (TOP VIEW) PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC PC3OUT SIGIN PC2OUT R2 R1 DEMOUT VCOIN DESCRIPTION/ORDERING INFORMATION The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7. The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator. The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. ORDERING INFORMATION (1) TA PACKAGE SOP – NS –40°C to 125°C SOIC – D TSSOP – PW TVSOP – DGV (1) ORDERABLE PART NUMBER Tube of 50 SN74LV4046ANS Reel of 2000 SN74LV4046ANSR Tube of 40 SN74LV4046AD Reel of 2500 SN74LV4046ADR Tube of 90 SN74LV4046APW Reel of 2000 SN74LV4046APWR Reel of 2000 SN74LV4046ADGVR TOP-SIDE MARKING 74LV4046A LV4046A LW046A LW046A For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 PCPOUT Phase comparator pulse output 2 PC1OUT Phase comparator 1 output 3 COMPIN Comparator input 4 VCOOUT VCO output 5 INH Inhibit input 6 C1A Capacitor C1 connection A 7 C1B Capacitor C1 connection B 8 GND Ground (0 V) 9 VCOIN 10 DEMOUT 11 R1 Resistor R1 connection 12 R2 Resistor R2 connection 13 PC2OUT 14 SIGIN 15 PC3OUT 16 VCC VCO input Demodulator output Phase comparator 2 output Signal input Phase comparator 3 output Positive supply voltage Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC DC supply voltage range –0.5 7 V VI Input voltage range –0.5 VCC + 0.5 V VO Output voltage range –0.5 VCC + 0.5 IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output curent VO = 0 to VCC ±35 mA ICC DC VCC or ground current ±70 mA D package θJA Package thermal impedance (2) Tstg (1) (2) V 73 DGV package 120 NS package 64 PW package 108 Storage temperature range UNIT –65 °C/W °C 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions PARAMETER 2 TA Operating free-air temperature VCC Supply voltage VI, VO DC input or output voltage Submit Documentation Feedback MIN MAX UNIT –40 125 °C 3 5.5 V 0 VCC V SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 Electrical Specifications TEST CONDITIONS PARAMETER VI (V) IO (mA) VCC (V) MIN 3 to 3.6 VCC × 0.7 4.5 to 5.5 VCC × 0.7 TYP MAX UNIT VCO VIH High-level input voltage INH VIL Low-level input voltage INH VOH High-level output voltage VCOOUT Low-level output voltage VOL VCOOUT CMOS VIL or VIH TTL –12 CMOS 0.05 VIL or VIH TTL C1A, C1B (test purposes only) II Input leakage current –0.05 INH, VCOIN 3 to 5.5 VCC × 0.3 4.5 to 5.5 VCC × 0.3 3 to 3.6 VCC – 0.1 4.5 to 5.5 VCC – 0.1 4.5 to 5.5 3.8 4.5 to 5.5 0.1 4.5 to 5.5 0.55 12 4.5 to 5.5 0.65 ±1 µA 50 kΩ 3 to 5.5 3 50 kΩ 3 to 3.6 40 4.5 to 5.5 40 No Limit pF 3 to 3.6 1.1 1.9 4.5 to 5.5 1.1 3.2 R2 range (1) C1 capacitance range Over the range specified for R1 for linearity (2) V 3 5.5 3 to 5.5 VCOIN 0.1 12 VCC or GND V V 3 to 3.6 R1 range (1) Operating voltage range V V Phase Comparator DC-coupled high-level input voltage SIGIN, COMPIN VIL DC-coupled low-level input voltage SIGIN, COMPIN VOH High-level output voltage VIH Low-level output voltage VOL 4.5 to 5.5 VCC × 0.7 3 to 3.6 VCC × 0.3 4.5 to 5.5 VCC × 0.3 3 to 5.5 VCC – 0.1 –6 3 to 3.6 2.48 TTL –12 4.5 to 5.5 3.8 CMOS 0.02 CMOS PCPOUT, PCNOUT VIL or VIH VIL or VIH 4 II Input leakage current SIGIN, COMPIN VCC or GND IOZ 3-state off-state current PC2OUT VIL or VIH Input resistance VCC × 0.7 –0.05 PCPOUT, PCNOUT TTL RI 3 to 3.6 SIGIN, COMPIN VI at self-bias operating point, VI = 0.5 V V V 3 to 3.6 0.1 4.5 to 5.5 0.1 4.5 to 5.5 0.4 3 to 3.6 ±11 4.5 to 5.5 ±29 ±5 3 to 5.5 3 800 4.5 250 V µA µA kΩ Demodulator RS Resistor range RS > 300 kΩ, Leakage current can influence VDEMOUT VOFF Offset voltage VCOIN to VDEM VI = VVCOIN = VCC/2, Values taken over RS range ICC Quiescent device current (1) (2) Pins 3, 5, and 14 at VCC, Pin 9 at GND, II at pins 3 and 14 to be excluded 3 to 3.6 50 300 4.5 to 5.5 50 300 3 to 3.6 ±30 4.5 to 5.5 ±20 5.5 kΩ mV 50 µA The value for R1 and R2 in parallel should exceed 2.7 kΩ. The maximum operating voltage can be as high as VCC – 0.9 V; however, this may result in an increased offset voltage. Submit Documentation Feedback 3 SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 Switching Specifications CL = 50 pF, Input tr, tf = 6 ns PARAMETER TEST CONDITIONS VCC (V) MIN TYP MAX UNIT Phase Comparator 3 to 3.6 135 4.5 to 5.5 50 3 to 3.6 300 4.5 to 5.5 60 3 to 3.6 200 4.5 to 5.5 50 tPLH, tPHL Propagation delay SIGIN, COMPIN to PC1OUT tPLH, tPHL Propagation delay SIGIN, COMPIN to PCPOUT tPLH, tPHL Propagation delay SIGIN, COMPIN to PC3OUT tTHL, tTLH Output transition time 3 to 3.6 75 4.5 to 5.5 15 tPZH, tPZL 3-state output enable time SIGIN, COMPIN to PC2OUT 3 to 3.6 270 4.5 to 5.5 54 tPHZ, tPLZ 3-state output disable time SIGIN, COMPIN to PC2OUT 3 to 3.6 320 4.5 to 5.5 65 AC-coupled input sensitivity (P-P) at SIGIN or COMPIN VI(P-P) 3 to 3.6 11 4.5 to 5.5 15 ns ns ns ns ns ns mV VCO ∆f/∆T fMAX Frequency stability with temperature change Maximum frequency Center frequency (duty 50%) ∆fVCO VI = VCOIN = 1/2 VCC, R1 = 100 kΩ, R2 = ∞, C1 = 100 pF C1 = 50 pF, R1 = 3.5 kΩ, R2 = ∞ C1 = 0 pF, R1 = 9.1 kΩ, R2 = ∞ C1 = 40 pF, R1 = 3 kΩ, R2 = ∞, VCOIN = VCC/2 3 to 3.6 0.11 4.5 to 5.5 0.11 3 to 3.6 24 4.5 to 5.5 24 3 to 3.6 38 4.5 to 5.5 38 3 to 3.6 7 10 4.5 to 5.5 12 17 4.5 (1) 15 (1) %/°C MHz MHz 17.5 (1) C1 = 100 pF, R1 = 100 kΩ, R2 = ∞ 3 to 3.6 0.4 Frequency linearity 4.5 to 5.5 0.4 Offset frequency C1 = 1 nF, R2 = 220 kΩ 3 to 3.6 400 4.5 to 5.5 400 % kHz Demodulator VOUT vs fIN (1) 4 C1 = 100 pF, C2 = 100 pF, R1 = 100 kΩ, R2 = ∞, R3 = 100 kΩ Data is specified at 25°C Submit Documentation Feedback 3 4.5 8 330 mV/kHz SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 APPLICATION INFORMATION AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE V CC VCC V DEMOUT (AV) VDEMOUT (AV) 1/2 V CC 1/2 V CC 0 –3605 0 05 905 φDEMOUT 1805 Figure 1. Phase Comparator 1: VDEMOUT = VPC1OUT = (VCC/π) (SIGIN – COMPIN); DEMOUT = (SIGIN – COMPIN) φ DEMOUT 3605 Figure 2. Phase Comparator 2: VDEMOUT = VPC2OUT = (VCC/4) (SIGIN – COMPIN); DEMOUT = (SIGIN – COMPIN) SIGIN SIGIN COMPIN COMPIN VCOOUT VCOOUT 05 VCC GND PC2 OUT PC1OUT High-Impedance Off State VCC VCO IN VCOIN GND PCPOUT Figure 3. Typical Waveforms for PLL Using Phase Comparator 1, Loop Locked at fo Figure 4. Typical Waveforms for PLL Using Phase Comparator 2, Loop Locked at fo AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE VCC SIGIN VDEMOUT(AV) COMPIN VCOOUT 1/2 VCC PC3OUT VCC VCOIN GND 0 05 1805 fDEMOUT 3605 Figure 5. Phase Comparator 3: VDEMOUT = VPC3OUT = (VCC/2π) (SIGIN – COMPIN); DEMOUT = (SIGIN – COMPIN) Figure 6. Typical Waveforms for PLL Using Phase Comparator 3, Loop Locked at fo Submit Documentation Feedback 5 SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) SIGIN, COMPIN Inputs SIGIN Inputs VS tPHL tPLH PCPOUT, PC1OUT, PC3OUT Outputs VS COMPIN Inputs VS tPHZ VS tPZL tPZH tTHL PC2OUT Output tTLH tPLZ 90% VS 10% Figure 7. Input-to-Output Propagation Delays and Output Transition Times Figure 8. 3-State Enable and Disable Times for PC2OUT CPD (1) CHIP SECTION 120 VCO 120 (1) 6 CPD Comparator 1 R1 between 3 kΩ and 50 kΩ R2 between 3 kΩ and 50 kΩ R1 + R2 parallel value > 2.7 kΩ C1 > 40 pF Submit Documentation Feedback UNIT pF PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV4046AD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046ADG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LV4046ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LV4046ANS ACTIVE SO NS 16 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046ANSG4 ACTIVE SO NS 16 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046APW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4046APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LV4046ADGVR TVSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 12.0 Q1 DGV 16 2000 330.0 12.4 6.8 4.0 1.6 W Pin1 (mm) Quadrant SN74LV4046ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV4046ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV4046APWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV4046ADGVR TVSOP DGV 16 2000 346.0 346.0 29.0 SN74LV4046ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV4046ANSR SO NS 16 2000 346.0 346.0 33.0 SN74LV4046APWR TSSOP PW 16 2000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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