STMICROELECTRONICS 54VCXH162245_11

54VCXH162245
Rad hard low voltage CMOS 16-bit bus buffer transceiver
(3-state) with 3.6 V tolerant inputs and outputs
Features
■
1.65 to 3.6 V inputs and outputs
■
High speed A outputs:
– tPD = 3.4 ns at VCC = 3.0 to 3.6 V
– tPD = 4.3 ns at VCC = 2.3 to 2.7 V
■
Symmetrical impedance A output:
– |IOH| = IOL = 12 mA (Min.) at VCC = 3.0 V
– |IOH| = IOL = 8 mA (Min.) at VCC = 2.3 V
■
High speed B outputs:
– tPD = 2.5 ns (Max.) at VCC = 3.0 to 3.6 V
– tPD = 3.2 ns (Max.) at VCC = 2.3 to 2.7 V
■
Symmetrical impedance A output:
– |IOH| = IOL = 24 mA (Min.) at VCC = 3.0 V
– |IOH| = IOL = 18 mA (Min.) at VCC = 2.3 V
■
Power down protection on inputs and outputs
■
26 Ω serie resistors in A port output
■
Operating voltage range:
– VCC(Opr) = 1.65 V to 3.6 V
■
Pin and function compatible with 54 series
H162245
■
Bus hold provided on both sides
■
Cold spare function
■
Latch-up performance exceeds
300 mA (JESD 17)
■
ESD performance:
– HBM > 2000 V
(MIL STD 883 method 3015); MM > 200 V
■
300 krad Mil1019.6 condition A, (RHA QML
qualification extension undergone)
■
No SEL, no SEU and no SET under 110
Mev/cm2/mg LET heavy ions irradiation
■
QML qualified product
■
Device fully compliant with
DSCC SMD 5962-02508
■
100 mV typical Input hysteresis
July 2011
Flat-48
The upper metallic lid is not electrically connected to any
pins, nor to the IC die inside the package.
Description
The 54VCXH162245 is a low voltage CMOS 16
bit bus transceiver (3-state) fabricated with submicron silicon gate and five-layer metal wiring
C²MOS technology. It is ideal for low power and
very high speed 1.65 to 3.6 V applications; it can
be interfaced to 3.6 V signal environment for both
inputs and outputs. This IC is intended for twoway asynchronous communication between data
buses; the direction of data transmission is
determined by DIR input. The two enable inputs
nG can be used to disable the device so that the
buses are effectively isolated. The device circuits
is including 26 Ω series resistance in the A port
outputs. These resistors permit to reduce line
noise in high speed applications. Bus hold on
data inputs is provided in order to eliminate the
need for external pull-up or pull-down resistor. All
inputs and outputs are equipped with protection
circuits against static discharge, giving them 2 kV
ESD immunity and transient excess voltage. All
floating bus terminals during high Z state must be
held HIGH or LOW.
Doc ID 10632 Rev 9
1/19
www.st.com
19
Contents
54VCXH162245
Contents
1
Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
Doc ID 10632 Rev 9
54VCXH162245
1
Logic symbols and I/O equivalent circuit
Logic symbols and I/O equivalent circuit
Figure 1.
IEC logic symbols
Figure 2.
Input and output equivalent circuit
Doc ID 10632 Rev 9
3/19
Pin settings
54VCXH162245
2
Pin settings
2.1
Pin connection
Figure 3.
4/19
Pin connection (top through view)
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54VCXH162245
2.2
Pin settings
Pin description
Table 1.
2.3
Pin description
Pin n°
Symbol
1
1DIR
2, 3, 5, 6, 8, 9, 11, 12
1B1 to 1B8
Data inputs/outputs
13, 14, 16, 17, 19, 20, 22, 23
2B1 to 2B8
Data inputs/outputs
24
2DIR
25
2G
Output enable input
36, 35, 33, 32, 30, 29, 27, 26
2A1 to 2A8
Data inputs/outputs
47, 46, 44, 43, 41, 40, 38, 38
1A1 to 1A8
Data inputs/outputs
48
1G
Output enable input
4, 10, 15, 21, 28, 34, 39, 45
GND
Ground (0 V)
7, 18, 31, 42
VCC
Positive supply voltage
Directional control
Directional control
Truth table
Table 2.
Truth table
Inputs
Note:
Name and function
Function
Output
G
DIR
A bus
B bus
Yn
L
L
output
input
A=B
L
H
input
output
B=A
H
X
Z
Z
Z
X = Do not care; Z = High Impedance
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Maximum rating
3
54VCXH162245
Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 3.
Absolute maximum ratings
Symbol
Value
Unit
Supply voltage
-0.5 to +4.6
V
VI
DC input voltage
-0.5 to +4.6
V
VO
DC output voltage (OFF state)
-0.5 to +4.6
V
-0.5 to VCC + 0.5
V
VCC
Parameter
(1)
VO
DC output voltage (high or low state)
IIK
DC input diode current
- 50
mA
IOK
DC output diode current (2)
- 50
mA
IO
DC output current
± 50
mA
DC VCC or ground current per supply pin
± 100
mA
400
mW
-65 to +150
°C
260
°C
ICC or
IGND
PD
Power dissipation
Tstg
Storage temperature
TL
Lead temperature (10 sec)
1. IO absolute maximum rating must be observed
2. VO < GND, VO > VCC
6/19
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54VCXH162245
3.1
Maximum rating
Recommended operating conditions
Table 4.
Recommended operating conditions
Symbol
Value
Unit
Supply voltage
1.8 to 3.6
V
VI
Input voltage
-0.3 to 3.6
V
VO
Output voltage (OFF state)
0 to 3.6
V
VO
Output voltage (high or low state)
0 to VCC
V
VCC
Parameter
IOH, IOL
High or low level output current - A side (VCC = 3.0 to 3.6 V)
± 12
mA
IOH, IOL
High or low level output current - A side (VCC = 2.3 to 2.7 V)
±8
mA
IOH, IOL
High or low level output current - B side (VCC = 3.0 to 3.6 V)
± 24
mA
IOH, IOL
High or low level output current - B side (VCC = 2.3 to 2.7 V)
± 18
mA
-55 to 125
°C
0 to 10
ns/V
Top
dt/dv
Operating temperature
Input rise and fall time (1)
1. VIN from 0.8 V to 2 V at VCC = 3.0 V
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Electrical characteristics
4
54VCXH162245
Electrical characteristics
2.7 V < VCC < 3.6 V unless otherwise specified.
Table 5.
DC specifications
Test condition
Symbol
Parameter
High level input voltage
VIL
Low level input voltage
VOH
VOH
VOL
VOL
II
-55 to 125 °C
VCC
(V)
VIH
Min.
Unit
Max.
2.0
2.7 to 3.6
V
0.8
High level output
voltage
(A outputs)
2.7 to 3.6
IO=-100 μA
VCC-0.2
2.7
IO=-6 mA
2.2
IO=-8 mA
2.4
IO=-12 mA
2.2
2.7 to 3.6
IO=-100 μA
VCC-0.2
2.7
IO=-12 mA
2.2
IO=-18 mA
2.4
IO=-24 mA
2.2
3.0
High level output
voltage
(B outputs)
3.0
Low level output
voltage
(A outputs)
0.2
2.7
IO=6 mA
0.4
IO=8 mA
0.55
IO=12 mA
0.8
2.7 to 3.6
IO=100 μA
0.2
2.7
IO=12 mA
0.4
IO=18 mA
0.4
IO=24 mA
0.55
VI = 0 to 3.6 V
±5
3.0
Input leakage current
V
IO=100 μA
3.0
Low level output
voltage
(B outputs)
V
2.7 to 3.6
2.7 to 3.6
3.0
II(HOLD) Input hold current
8/19
Value
V
V
VI = 0.8 V
75
VI = 2 V
-75
μA
μA
3.6
VI = 0 to 3.6 V
± 500
0
VI or VO = 0 to 3.6 V
10
μA
VI = VIH or VIL
VO = 0 to 3.6 V
± 10
μA
VI = VCC or GND
20
VI or VO = VCC to 3.6 V
± 20
VIH = VCC - 0.6 V
750
Ioff
Power off leakage
current
IOZ
High impedance output
leakage current
2.7 to 3.6
ICC
Quiescent supply
current
2.7 to 3.6
ΔICC
ICC incr. per input
2.7 to 3.6
Doc ID 10632 Rev 9
μA
μA
54VCXH162245
Electrical characteristics
2.3 V < VCC < 2.7 V unless otherwise specified.
Table 6.
DC specifications
Test condition
Symbol
Parameter
-55 to 125 °C
VCC
(V)
VIH
High level input voltage
VIL
Low level input voltage
Min.
1.6
V
0.7
High level output voltage
2.3
II
II(HOLD) Input hold current
Ioff
Power off leakage
current
IOZ
ICC
IO=-4 mA
2.0
IO=-6 mA
1.8
IO=-8 mA
1.7
V
IO=6 mA
0.4
IO=8 mA
0.6
VI = VCC or GND
±5
2.3
2.3 to 2.7
VCC-0.2
0.2
Low level output voltage
Input leakage current
IO=-100 μA
IO=100 μA
2.3 to 2.7
VOL
Unit
Max.
2.3 to 2.7
2.3 to 2.7
VOH
Value
2.3
VI = 0.7 V
45
VI = 1.7 V
-45
V
μA
μA
0
VI or VO = 0 to 3.6 V
10
μA
High impedance output
leakage current
2.3 to 2.7
VI = VIH or VIL
VO = 0 to 3.6 V
± 10
μA
Quiescent supply
current
VI = VCC or GND
20
2.3 to 2.7
VI or VO = VCC to 3.6V
± 20
Doc ID 10632 Rev 9
μA
9/19
Electrical characteristics
54VCXH162245
TA = 25 °C, Input tr = tf = 2.0 ns, CL = 30 pF, RL = 500 Ω
Table 7.
Dynamic switching characteristics
Test condition
Symbol
Parameter
TA = 25 °C
VCC
(V)
VOLP
Dynamic peak low voltage
quiet output (1) (2) (A to B)
VOLP
Dynamic peak low voltage
quiet output (1) (2) (B to A)
VOLV
Dynamic valley low voltage
quiet output (1) (2) (A to B)
VOLV
Dynamic valley low voltage
quiet output (1) (2) (B to A)
VOHV
Dynamic valley high voltage
quiet output (2) (3) (A to B)
VOHV
Dynamic valley high voltage
quiet output (2) (3) (B to A)
2.5
3.3
2.5
3.3
2.5
3.3
2.5
3.3
2.5
3.3
2.5
3.3
Value
VIL = 0V
VIH = VCC
VIL = 0V
VIH = VCC
VIL = 0V
VIH = VCC
VIL = 0V
VIH = VCC
VIL = 0V
VIH = VCC
VIL = 0V
VIH = VCC
Unit
Min.
Typ.
Max.
-
0.6
-
-
0.8
-
-
0.25
-
-
0.35
-
-
-0.6
-
-
-0.8
-
-
-0.25
-
-
-0.35
-
-
1.9
-
-
2.2
-
-
2.05
-
-
2.65
-
V
V
V
V
V
V
1. Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH to LOW or LOW to
HIGH. The remaining output is measured in the LOW state.
2. Parameters guaranteed by design.
3. Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH to LOW or LOW to
HIGH. The remaining output is measured in the HIGH state.
10/19
Doc ID 10632 Rev 9
54VCXH162245
Electrical characteristics
CL = 30 pF, RL = 500 Ω, Input tr = tf = 2.0 ns
Table 8.
AC electrical characteristics
Test condition
Symbol
Parameter
VCC
(V)
Value
Unit
-55 to 125 °C
Min.
Max.
Propagation delay
time (A to B)
2.3 to 2.7
1.0
4.0
tPLH tPHL
3.0 to 3.6
0.8
3.6
Propagation delay
time (B to A)
2.3 to 2.7
1.0
4.9
tPLH tPHL
3.0 to 3.6
0.8
4.0
Output enable time
(A to B)
2.3 to 2.7
1.0
5.8
tPZL tPZH
3.0 to 3.6
0.8
4.3
Output enable time
(B to A)
2.3 to 2.7
1.0
6.8
tPZL tPZH
3.0 to 3.6
0.8
4.8
Output disable time
(A to B)
2.3 to 2.7
1.0
4.8
tPLZ tPHZ
3.0 to 3.6
0.8
5.6
Output disable time (B
to A)
2.3 to 2.7
1.0
5.7
tPLZ tPHZ
3.0 to 3.6
0.8
7.0
Output to output skew
time (1) (2)
2.3 to 2.7
0.5
tOSLH tOSHL
3.0 to 3.6
0.5
ns
ns
ns
ns
ns
ns
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|,
tOSHL = | tPHLm - tPHLn|)
2. Parameter guaranteed by design
Table 9.
Capacitive characteristics
Test condition
Symbol
CIN
Parameter
Value
TA = 25 °C
VCC
(V)
Unit
Min.
Typ.
Max.
Input capacitance
2.5 or 3.3
VIN = 0 or VCC
-
4
-
pF
COUT
Output capacitance
2.5 or 3.3
VIN = 0 or VCC
-
8
-
pF
CPD
Power dissipation
capacitance (1)
2.5 or 3.3
fIN = 10 MHz
VIN = 0 or VCC
-
28
-
pF
1. CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the
operating current consumption without load. (Refer to test circuit). Average operating current can be
obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit)
Doc ID 10632 Rev 9
11/19
Test circuit
5
54VCXH162245
Test circuit
Figure 4.
Test circuit
Table 10.
Test circuit
Test
tPLH, tPHL
Open
tPZL, tPLZ (VCC = 3.0 to 3.6 V)
6V
tPZL, tPLZ (VCC = 2.3 to 2.7 V)
2VCC
tPZH, tPHZ
GND
CL = 30 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500 Ω or equivalent
RT = ZOUT of pulse generator (typically 50 Ω)
12/19
Switch
Doc ID 10632 Rev 9
54VCXH162245
6
Waveforms
Waveforms
Table 11.
Waveform symbol value
VCC
Symbol
Figure 5.
3.0 to 3.6 V
2.3 to 2.7 V
VIH
2.7V
VCC
VM
1.5V
VCC/2
VX
VOL +0.3V
VOL +0.15V
VY
VOH -0.3V
VOH -0.15V
Waveform - propagation delay (f = 1 MHz; 50% duty cycle)
Doc ID 10632 Rev 9
13/19
Waveforms
54VCXH162245
Figure 6.
14/19
Waveform - output enable and disable time (f = 1 MHz; 50% duty cycle)
Doc ID 10632 Rev 9
54VCXH162245
7
Package mechanical data
Package mechanical data
54VCXH162245 Products are supplied into ceramic body / metal lid hermetic Flat 48-pin
space package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 12.
Flat-48 (MIL-STD-1835) mechanical data
mm
inch
Dim.
Min.
Typ.
Max.
Min.
Typ.
Max.
A
2.18
2.47
2.72
0.086
0.097
0.107
b
0.20
0.254
0.30
0.008
0.010
0.012
c
0.12
0.15
0.18
0.005
0.006
0.007
D
15.57
15.75
15.92
0.613
0.620
0.627
E
9.52
9.65
9.78
0.375
0.380
0.385
E2
6.22
6.35
6.48
0.245
0.250
0.255
E3
1.52
1.65
1.78
0.060
0.065
0.070
e
0.635
0.025
f
0.20
0.008
L
6.85
8.38
9.40
0.270
0.330
0.370
Q
0.66
0.79
0.92
0.026
0.031
0.036
S1
0.25
0.43
0.61
0.010
0.017
0.024
Doc ID 10632 Rev 9
15/19
Package mechanical data
Figure 7.
54VCXH162245
Package dimension
7330585B
Note:
16/19
The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the
package. Connecting unused pins or metal lid to ground or to the power supply will not affect
the electrical characteristics.
Doc ID 10632 Rev 9
54VCXH162245
Order codes
8
Order codes
Table 13.
Ordering information
Package
48-pin flat
Min op.
voltage
Lead
finish
Radiation
level
1.8 V
gold
plated
300 krad
Flight models
Engineering model
Packing
RHRXH162245K1
Conductive strip pack
QML-V
RHFXH162245K03V
Doc ID 10632 Rev 9
17/19
Revision history
9
54VCXH162245
Revision history
Table 14.
18/19
Document revision history
Date
Revision
Changes
06-Jul-2004
1
First release
19-Jul-2004
2
Data on range -40 to 85°C removed on Tables 6, 7, 8, 9
17-May-2005
3
Mechanical data has been updated
19-Jun-2006
4
300 Krad bullet updated, new template, mechanical data updated
11-Apr-2007
5
Updated coverpage features
27-Jul-2007
6
Typo in Table 12 on page 15
17-Sep-2008
7
Updated cover page
23-Sep-2009
8
Updated Table 13 on page 17
29-Jul-2011
9
Added Note: on page 16 and in the "Pin connections" diagram on the
coverpage
Doc ID 10632 Rev 9
54VCXH162245
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Doc ID 10632 Rev 9
19/19