Freescale Semiconductor, Inc. DATA SHEET MOTOROLA Order number: XC9850 Rev 0, 07/2004 SEMICONDUCTOR TECHNICAL DATA XC9850 Clock Generator for PowerQUICC III Clock Generator for PowerQUICC III Freescale Semiconductor, Inc... The XC9850 is a PLL based clock generator specifically designed for Motorola Microprocessor And Microcontroller applications including the PowerQUICC III. This device generates a microprocessor input clock plus the 500 MHz Rapid I/O clock. The microprocessor clock is selectable in output frequency to any of the commonly used microprocessor input and bus frequencies. The Rapid I/O outputs are LVDS compatible. The device offers eight low skew clock outputs organized into two output banks, each configurable to support different clock frequencies. The extended temperature range of the XC9850 supports telecommunication and networking requirements. Features • 8 LVCMOS outputs for processor and other circuitry • 2 differential LVDS outputs for Rapid I/O interface • Crystal oscillator or external reference input • 25 or 33 MHz Input reference frequency • Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33 or 16 MHz • Buffered reference clock output • Rapid I/O (LVDS) Output = 500, 250 or 125 MHz • Low cycle-to-cycle and period jitter • 100-lead PBGA package • 100-lead Pb-free Package Available • 3.3V supply with 3.3V or 2.5V output LVCMOS drive • Supports computing, networking, telecommunications applications • Ambient temperature range –40°C to +85°C MICROPROCESSOR CLOCK GENERATOR SCALE 2:1 VF SUFFIX VM SUFFIX (Pb-FREE) 100 MAPBGA PACKAGE CASE 1462-01 Functional Description The XC9850 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83 66 50 33 or 16 MHz. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use in driving a microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency is also divided to produce a 125, 250 or 500 MHz clock output for Rapid I/O applications such as found on the PowerQUICC III communications processor. The input reference, either crystal or external input is also buffered to a separate output that my be used as the clock source for a Gigabit Ethernet PHY if desired. The reference clock may be provided by either an external clock input of 25 MHz or 33 MHz. An internal oscillator requiring a 25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33MHz configuration pins is used to select between a 33 and 25 MHz input frequency. The XC9850 is packaged in a 100 lead MAPBGA package to optimize both performance and board density. IDT™ Clock Generator for PowerQUICC III Foracquired More Information On This Product, © Motorola, 2004 Organization has been Freescale Timing Inc. Solutions by Integrated Device Technology, Inc Go to: www.freescale.com 1 XC9850 XC9850 Clock Generator for PowerQUICC III NETCOM Freescale Semiconductor, Inc. XC9850 CLK 0 PCLK PCLK 1 XTAL_OUT ÷N Ref 1 REF_CLK_SEL XTAL_IN 1 0 QA0 0 QA1 PLL 2000 MHz QA2 OSC QA3 REF_SEL ÷N QB0 PLL_BYPASS QB1 Freescale Semiconductor, Inc... REF_33MHz QB2 QB3 ÷4, 8, 16, 40 QC0 QC0 CLK_A[0:5] CLK_B[0:5] RIO_C[0:1] QC1 QC1 MR REF_OUT Figure 1. XC9850 Logic Diagram Table 1. Pin Configurations CLK Pin I/O Input Type Function LVCMOS PLL Reference Clock Input (pull-down) Supply VDD PCLK, PCLK Input LVPECL VDD QA0, QA1, QA2, QA3 Output PLL Reference Clock Input (PCLK - pull-down, PCLK - pull-up and pull-down) LVCMOS Bank A Outputs QB0, QB1, QB2, QB3 Output LVCMOS Bank B Outputs VDDOB QC0, QC1, QC0, QC1 Output LVDS VDDOC REF_OUT Output LVCMOS Reference Output (25 MHz or 33 MHz) VDD XTAL_IN Input LVCMOS Crystal Oscillator Input Pin VDD Bank C Outputs Active/State VDDOA XTAL_OUT Output LVCMOS Crystal Oscillator Output Pin VDD REF_CLK_SEL Input LVCMOS Select between CLK and PCLK Input (pull-down) VDD High REF_SEL Input LVCMOS Select between External Input and Crystal Oscillator Input (pull-down) VDD High REF_33MHz Input LVCMOS Selects 33 MHz Input (pull-down) VDD High MR Input LVCMOS Master Reset (pull-up) VDD Low PLL_BYPASS Input LVCMOS Select PLL or static test mode (pull-down) VDD High 1 Input LVCMOS Configures Bank A clock output frequency (pull-up) VDD High 2 Input LVCMOS Configures Bank B clock output frequency (pull-up) VDD High Input LVCMOS Configures Bank C clock output frequency (pull-down) VDD CLK_A[0:5] CLK_B[0:5] RIO_C [0:1] VDD 3.3 V Supply VDDA Analog Supply VDDOA Supply for Output Bank A VDDOB Supply for Output Bank B GND Ground 1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) 2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) PowerPC bit ordering (bit 0 = msb, bit 1 = lsb) IDT™ Clock Generator for PowerQUICC III TIMING SOLUTIONS 2 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 2 XC9850 MOTOROLA XC9850 Clock Generator for PowerQUICC III XC9850 NETCOM Freescale Semiconductor, Inc. Table 2. Function Table Control Default 0 1 REF_CLK_SEL 0 CLK PCLK REF_SEL 0 CLK or PCLK XTAL PLL_BYPASS 0 Normal Bypass REF_33MHz 0 Selects 25 MHz Reference Selects 33 MHz Reference MR 1 Reset Normal CLK_A, CLK_B, and RIO_C control output frequencies. See Table 3 and Table 4 for specific device configuration Freescale Semiconductor, Inc... Table 3. Output Configurations (Banks A & B) CLK_x[0:5]1 CLK_x[0] (msb) CLK_x[1] CLK_x[2] CLK_x[3] CLK_x[4] CLK_x[5] (lsb) N Frequency (MHz) 111111 1 1 1 1 1 1 126 15.87 111100 1 1 1 1 0 0 120 16.67 101000 1 0 1 0 0 0 80 25.00 011110 0 1 1 1 1 0 60 33.33 010100 0 1 0 1 0 0 40 50.00 001111 0 0 1 1 1 1 30 66.67 001100 0 0 1 1 0 0 24 83.33 001010 0 0 1 0 1 0 20 100.00 001001 0 0 1 0 0 1 18 111.11 001000 0 0 1 0 0 0 16 125.00 000111 0 0 0 1 1 1 15 133.33 000110 0 0 0 1 1 0 12 166.67 000101 0 0 0 1 0 1 10 200.00 000100 0 0 0 1 0 0 82 250 1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) 2. Minimum value for N Table 4. Output Configurations (Bank C) RIO_C[0:1] Frequency (MHz) 00 50 (test output) 01 125 10 250 11 500 IDT™ Clock Generator for PowerQUICC III MOTOROLA 3 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 3 XC9850 TIMING SOLUTIONS XC9850 Clock Generator for PowerQUICC III NETCOM Freescale Semiconductor, Inc. XC9850 OPERATION INFORMATION Output Frequency Configuration The XC9850 was designed to provide the commonly used frequencies in PowerQUICC, PowerPC and other microprocessor systems. Table 3 lists the configuration values that will generate those common frequencies. The XC9850 can generate numerous other frequencies that may be useful in specific applications. The output frequency (fout) of either Bank A or Bank B may be calculated by the following equation. fout = 2000 / N where fout is in MHz and N = 2 * CLK_x[0:5] Freescale Semiconductor, Inc... This calculation is valid for all values of N from 8 to 126. Note that N = 15 is a modified case of the configuration inputs CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to 00111 or 7. Crystal Input Operation TBD Power-Up and MR Operation Figure 2 defines the release time and the minimum pulse length for MR pin. The MR release time is based upon the power supply being stable and within VDD specifications. See Table 11 for actual parameter values. The XC9850 may be configured after release of reset and the outputs will be stable for use after lock indication is obtained. VDD MR treset_rel treset_pulse Figure 2. MR Operation Power Supply Bypassing The XC9850 is a mixed analog/digital product. The architecture of the XC9850 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VDD pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VDD VDD 22 µF 0.1 µF XC9850 15 Ω VDDA 0.1 µF Figure 3. VCC Power Supply Bypass IDT™ Clock Generator for PowerQUICC III TIMING SOLUTIONS 4 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 4 XC9850 MOTOROLA XC9850 Clock Generator for PowerQUICC III XC9850 NETCOM Freescale Semiconductor, Inc. Table 5. Absolute Maximum Ratings1 Symbol Min Max Unit VDD Supply Voltage (core) –0.3 3.8 V VDDA Supply Voltage (Analog Supply Voltage) –0.3 VDD V VDDOx Supply Voltage (LVCMOS output for Bank A or B) –0.3 VDD V DC Input Voltage –0.3 VDD+0.3 V DC Output Voltage2 –0.3 VDDx+0.3 V DC Input Current ±20 mA DC Output Current ±50 mA 125 °C VIN VOUT IIN IOUT Freescale Semiconductor, Inc... TS Characteristics Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 2. VDDx references power supply pin associated with specific output pin. Table 6. General Specifications Symbol Characteristics Min Typ Max VDD ÷ 2 Unit VTT Output Termination Voltage MM ESD Protection (Machine Model) 125 HBM ESD Protection (Human Body Model) 2000 V CDM ESD Protection (Charged Device Model) 500 V LU Latch-Up Immunity 100 mA Condition V V CIN Input Capacitance 4 pF Inputs CPD Power Dissipation Capacitance 10 pF Per Output θJA Thermal Resistance (junction-to-ambient) 54.5 °C/W Air flow = 0 TA Ambient Temperature –40 85 °C Table 7. DC Characteristics (TA = –40°C to 85°C) Symbol Characteristics Min Typ Max Unit Condition 200 mA VDD + VDDA pins Maximum Quiescent Supply Current (Analog Supply) 15 mA VDDIN pins Maximum Bank A and B Supply Current 175 mA VDDOA and VDDOB pins 200 mA VDD + VDDA pins Maximum Quiescent Supply Current (Analog Supply) 15 mA VDDIN pins Maximum Bank A and B Supply Current 100 mA VDDOA and VDDOB pins Supply Current for VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5 and VDDOB = 3.3 V ± 5% IDD + IDDA Maximum Quiescent Supply Current (Core) IDDA IDDOA, IDDOB Supply Current for VDD = 3.3 V ± 5%, VDDOA = 2.5 V ± 5% and VDDOB= 2.5 V ± 5% IDD + IDDA Maximum Quiescent Supply Current (Core) IDDA IDDOA, IDDOB IDT™ Clock Generator for PowerQUICC III MOTOROLA 5 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 5 XC9850 TIMING SOLUTIONS XC9850 Clock Generator for PowerQUICC III NETCOM Freescale Semiconductor, Inc. XC9850 Table 8. LVDS DC Characteristics (TA = –40°C to 85°C) Symbol Characteristics Min Typ Max Unit Condition Differential LVDS Clock Outputs (QC0, QC0 and QC1, QC1) for VDD = 3.3 V ± 5% VPP Output Differential Voltage1 (peak-to-peak) (LVDS) 100 400 mV VOS Output Offset Voltage (LVDS) 1050 1600 mV 1. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. Table 9. LVPECL DC Characteristics (TA = –40°C to 85°C)1 Symbol Characteristics Min Typ Max Unit Condition Differential LVPECL Clock Inputs (CLK1, CLK1) for VDD = 3.3 V ± 0.5% Freescale Semiconductor, Inc... VPP VCMR Differential Voltage2 (peak-to-peak) (LVPECL) 250 Differential Input Crosspoint Voltage3 (LVPECL) 1.0 mV VDD – 0.6 V 1. AC characteristics are design targets and pending characterization. 2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. Table 10. LVCMOS I/O DC Characteristics (TA = –40°C to 85°C) Symbol Characteristics Min Typ Max Unit Condition VDD + 0.3 V LVCMOS 0.8 V LVCMOS ± 200 µA VIN = VDDL or GND V IOH = –24 mA V IOL = 24 mA LVCMOS for VDD = 3.3 V ± 5% VIH Input High Voltage VIL Input Low Voltage IIN Input Current 2.0 1 LVCMOS for VDD = 3.3 V ±5%, VDDOA = 3.3 V ± 5 and VDDOB = 3.3 V ± 5% VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance 2.4 0.5 Ω 14 – 17 LVCMOS for VDD = 3.3 V ±5%, VDDOA = 2.5 V ± 5% and VDDOB= 2.5 V ± 5% VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance 1.9 0.4 18 – 22 V IOH = –15 mA V IOL = 15 mA Ω 1. Inputs have pull-down resistors affecting the input current. IDT™ Clock Generator for PowerQUICC III TIMING SOLUTIONS 6 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 6 XC9850 MOTOROLA XC9850 Clock Generator for PowerQUICC III XC9850 NETCOM Freescale Semiconductor, Inc. Table 11. AC Characteristics (VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5%,VDDOB = 3.3 V ± 5%, TA= –40°C to +85°C)1 2 Symbol Characteristics Min Typ Max Unit 250 MHz MHz MHz MHz Condition Input and Output Timing Specification fref Input Reference Frequency (25 MHz input) Input Reference Frequency (33 MHz input) XTAL Input 25 33 25 Freescale Semiconductor, Inc... Input Reference Frequency in PLL Bypass Mode3 fVCO VCO Frequency Range4 fMCX Output Frequency frefPW Reference Input Pulse Width frefCcc Input Frequency Accuracy 2000 Bank A output Bank B output Bank C output MHz 15.87 15.87 50 Output Rise/Fall Time 150 DC Output Duty Cycle 43 47 PLL locked 200 200 500 MHz MHz MHz 100 ppm 500 ns 20% to 80% 57 53 % Bank A and B Bank C 10 ms 2 tr, tf PLL bypass ns 50 50 PLL Specifications tLOCK treset_ref treset_pulse Maximum PLL Lock Time MR Hold Time on Power Up 10 ns MR Hold Time 10 ns Skew and Jitter Specifications tsk(O) Output-to-Output Skew (within a bank) 50 ps tsk(O) Output-to-Output Skew (across banks A and B) 400 ps VDDOA = 3.3 V VDDOB = 3.3 V tJIT(CC) Cycle-to-Cycle Jitter 200 150 ps ps Bank A and B Bank C tJIT(PER) Period Jitter tJIT(∅) 1. 2. 3. 4. RMS (1 σ) I/O Phase Jitter 200 ps Bank A and C 50 ps Bank A and C AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50Ω to VTT. In bypass mode, the XC9850 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = (fVCO ÷ M) ⋅ N. Pulse Generator Z = 50Ω ZO = 50Ω ZO = 50Ω RT = 100Ω RT = 50Ω DUT XC9850 VTT Figure 4. XC9850 AC Test Reference (LVDS Outputs) Pulse Generator Z = 50Ω ZO = 50Ω RT = 50Ω ZO = 50Ω DUT XC9850 RT = 50Ω VTT VTT Figure 5. XC9850 AC Test Reference (LVCMOS Outputs) IDT™ Clock Generator for PowerQUICC III MOTOROLA 7 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 7 XC9850 TIMING SOLUTIONS XC9850 Clock Generator for PowerQUICC III NETCOM Freescale Semiconductor, Inc. XC9850 Freescale Semiconductor, Inc... Table 12. XC9850 Pin Diagram (Top View) 1 2 3 4 5 6 7 8 9 10 A VDDOB VDDOB CLKA[1] CLKA[3] CLKA[5] VDD QA1 QA2 VDDOB VDDOB B VDDOB VDDOB CLKA[0] CLKA[2] CLKA[4] QA0 VDD QA3 VDDOB VDDOB C RSVD RSVD VDD VDD VDD VDD VDD VDD VDD REF_OUT D VDDA VDDA VDD GND GND GND GND VDD QC0 QC0 E REF_SEL CLK VDD GND GND GND GND VDD VDD GND F PCLK PCLK VDD GND GND GND GND VDD QC1 QC1 G REF_CLK_SEL REF_33MHz VDD GND GND GND GND VDD PLL_BYPASS MR H XTAL_IN XTAL_OUT VDD VDD VDD VDD VDD VDD RIO_C[1] RIO_C[0] J VDDOB VDDOB CLKB[0] CLKB[2] CLKB[4] QB0 VDDOB QB3 VDDOB VDDOB K VDDOB VDDOB CLKB[1] CLKB[3] CLKB[5] VDDOB QB1 QB2 VDDOB VDDOB Table 13. XC9850 Pin List Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA VDDOB A1 RSVD C1 REF_SEL E1 REF_CLK_SEL G1 VDDOB J1 VDDOB A2 RSVD C2 CLK E2 REF_33MHz G2 VDDOB J2 CLKA[1] A3 VDD C3 VDD E3 VDD G3 CLKB[0] J3 CLKA[3] A4 VDD C4 GND E4 GND G4 CLKB[2] J4 CLKA[5] A5 VDD C5 GND E5 GND G5 CLKB[4] J5 VDD A6 VDD C6 GND E6 GND G6 QB0 J6 QA1 A7 VDD C7 GND E7 GND G7 VDDOB J7 QA2 A8 VDD C8 VDD E8 VDD G8 QB3 J8 VDDOB A9 VDD C9 VDD E9 PLL_BYPASS G9 VDDOB J9 VDDOB A10 REF_OUT C10 GND E10 MR G10 VDDOB J10 VDDOB B1 VDDA D1 PCLK F1 XTAL_IN H1 VDDOB K1 VDDOB B2 VDDA D2 PCLK F2 XTAL_OUT H2 VDDOB K2 CLKA[0] B3 VDD D3 VDD F3 VDD H3 CLKB[1] K3 CLKA[2] B4 GND D4 GND F4 VDD H4 CLKB[3] K4 CLKA[4] B5 GND D5 GND F5 VDD H5 CLKB[5] K5 QA0 B6 GND D6 GND F6 VDD H6 VDD K6 VDDOA B7 GND D7 GND F7 VDD H7 QB1 K7 QA3 B8 VDD D8 VDD F8 VDD H8 QB2 K8 VDDOB B9 QC0 D9 QC1 F9 RIO_C[1] H9 VDDOB K9 VDDOB B10 QC0 D10 QC1 F10 RIO_C[0] H10 VDDOB K10 IDT™ Clock Generator for PowerQUICC III TIMING SOLUTIONS 8 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 8 XC9850 MOTOROLA XC9850 Clock Generator for PowerQUICC III NETCOM Freescale Semiconductor, Inc. XC9850 OUTLINE DIMENSIONS VF SUFFIX 100 MAP PBGA PACKAGE CASE 1462-01 ISSUE O B C 11 A1 INDEX AREA K NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGING. Freescale Semiconductor, Inc... 11 9X 0.2 4X TOP VIEW SIDE VIEW 1 0.5 5 0.35 A K J H 9X 1 1.7 MAX (1.18) G F 0.43 0.29 E D C 4 A SEATING PLANE 100X 0.12 A 0.5 B A 100X 1 2 A1 INDEX AREA 3 4 5 6 7 8 9 10 0.55 0.45 0.25 M A B C 0.10 M A 3 DETAIL K ROTATED 90˚ CLOCKWISE BOTTOM VIEW CASE 1462-01 ISSUE O IDT™ Clock Generator for PowerQUICC III TIMING SOLUTIONS 9 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 9 DATE 11/26/02 XC9850 MOTOROLA XC9850 MPC92459 PART NUMBERS 900 Clock MHz Generator Low Voltage forNAME PowerQUICC LVDS Clock III Synthesizer INSERT PRODUCT AND DOCUMENT TITLE NETCOM NETCOM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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