MOTOROLA MPC9855

Freescale Semiconductor
Technical Data
MPC9855
Rev 2, 1/2005
Preliminary Information
MPC9855
Clock Generator for PowerQUICC
and PowerPC Microprocessors
The MPC9855 is a PLL based clock generator specifically designed for
Freescale Microprocessor and Microcontroller applications including the
PowerPC and PowerQUICC. This device generates a microprocessor input
clock. The microprocessor clock is selectable in output frequency to any of the
commonly used microprocessor input and bus frequencies. The device offers
eight low skew clock outputs in two banks, each configurable to support different
clock frequencies. The extended temperature range of the MPC9855 supports
telecommunication and networking requirements.
Features
• 8 LVCMOS outputs for processor and other circuitry
• Crystal oscillator or external reference input
• 25 or 33 MHz Input reference frequency
• Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66,
50, 33, or 16 MHz
• Buffered reference clock output (2 copies)
• Low cycle-to-cycle and period jitter
• 100-lead PBGA package
• 100-lead Pb-free Package Available
• 3.3 V supply with 3.3 V or 2.5 V LVCMOS output supplies
• Supports computing, networking, telecommunications applications
• Ambient temperature range –40°C to +85°C
• 100-lead PBGA package
• 100-lead Pb-free Package Available
MICROPROCESSOR
CLOCK GENERATOR
VF SUFFIX
VM SUFFIX (Pb-FREE)
100 MAPBGA PACKAGE
CASE 1462-01
Functional Description
The MPC9855 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency
is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers,
divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60, or 120 to produce output frequencies of 200, 166, 133, 125, 111,
100, 83, 66, 50, 33, or 16 MHz. The single-ended LVCMOS outputs provide 8 low skew outputs for use in driving a microprocessor
or microcontroller clock input as well as other system components. The input reference, either crystal or external input is also
buffered to a separate dual outputs that my be used as the clock source for a Ethernet PHY if desired.
The reference clock may be provided by either an external clock input of 25 or 33 MHz. An internal oscillator requiring a 25
MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and
selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal
oscillator or external clock input is selected via the input pin of XTAL_SEL. Other than the crystal, no external components are
required for crystal oscillator operation. The REF_33 MHz configuration pin is used to select between a 33 and 25 MHz input
frequency.
The MPC9855 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.
ORDERING INFORMATION
Device
Temp. Range
Case No.
Package
MPC9855
–40°C to +85°C
1462-01
100 lead MAPBGA
© Freescale Semiconductor, Inc., 2005. All rights reserved.
CLK
PCLK
PCLK
0
1
÷N
Ref
QA1
PLL
OSC
QA0
0
1
CLK_SEL
XTAL_IN
1
0
2000 MHz
QA2
XTAL_OUT
QA3
XTAL_SEL
÷N
QB0
PLL_BYPASS
QB1
REF_33 MHz
QB2
QB3
CLK_A[0:5]
CLK_B[0:5]
REF_OUT0
MR
REF_OUT1
REF_OUT1_E
Figure 1. MPC9855 Logic Diagram
MPC9855
2
Timing Solutions
Freescale Semiconductor
Table 1. Pin Configurations
Pin
I/O
Type
Function
Supply
Active/State
CLK
Input
LVCMOS PLL reference clock input (pull-down)
VDD
—
PCLK, PCLK
Input
LVPECL PLL reference clock input
(PCLK — pull-down, PCLK — pull-up and pull-down)
VDD
—
VDDOA
—
QA0, QA1,
QA2, QA3
QB0, QB1,
QB2, QB3
Output
LVCMOS Clock Outputs
REF_OUT0
REF_OUT1
Output
LVCMOS Reference Output (25 MHz or 33 MHz)
VDD
—
LVCMOS Crystal Oscillator Input Pin
VDD
—
LVCMOS Crystal Oscillator Output Pin
VDD
—
XTAL_IN
Input
XTAL_OUT
Output
CLK_SEL
Input
LVCMOS Select between CLK and PCLK input (pull-down)
VDD
High
XTAL_SEL
Input
LVCMOS Select between External Input and Crystal Oscillator Input
(pull-down)
VDD
High
REF_33 MHz
Input
LVCMOS Selects 33MHz input (pull-down)
VDD
High
REF_OUT1_E
Input
LVCMOS Enables REF_OUT! output (pull-down)
VDD
High
MR
Input
LVCMOS Master Reset (pull-up)
VDD
Low
PLL_BYPASS
Input
LVCMOS Select PLL or static test mode (pull-up)
VDD
High
CLK_A[0:5](1)
Input
LVCMOS Configures Bank A clock output frequency (pull-up)
VDD
—
CLK_B[0:5]1
Input
LVCMOS Configures Bank B clock output frequency (pull-up)
VDD
—
VDD
—
—
3.3 V Supply
—
—
VDDA
—
—
Analog Supply
—
—
VDDOA
—
—
Output Supply — Bank A
—
—
VDDOB
—
—
Output Supply — Bank B
—
—
GND
—
—
Ground
—
—
1. Power PC bit ordering (bit 0 = msb, bit 5 = lsb).
Table 2. Function Table
Control
Default
0
1
CLK_SEL
0
CLK
PCLK
XTAL_SEL
0
CLKx
XTAL
PLL_BYPASS
0
Normal
Bypass
REF_OUT1_E
0
Disables REF_OUT1
Enables REF_OUT1
REF_33 MHz
0
Selects 25 MHz Reference
Selects 33 MHz Reference
MR
1
Reset
Normal
CLK_A and CLK_B control output frequencies. Refer to Table 3 for specific device configuration
MPC9855
Timing Solutions
Freescale Semiconductor
3
Table 3. Output Configurations (Banks A & B)
CLK_x[0:5](1)
CLK_x[0]
(msb)
CLK_x[1]
CLK_x[2]
CLK_x[3]
CLK_x[4]
CLK_x[5]
(lsb)
N
Frequency
(MHz)
111111
1
1
1
1
1
1
126
15.87
111100
1
1
1
1
0
0
120
16.67
101000
1
0
1
0
0
0
80
25.00
011110
0
1
1
1
1
0
60
33.33
010100
0
1
0
1
0
0
40
50.00
001111
0
0
1
1
1
1
30
66.67
001100
0
0
1
1
0
0
24
83.33
001010
0
0
1
0
1
0
20
100.00
001001
0
0
1
0
0
1
18
111.11
001000
0
0
1
0
0
0
16
125.00
000111
0
0
0
1
1
1
15
133.33
000110
0
0
0
1
1
0
12
166.67
000101
0
0
0
1
0
1
10
200.00
000100
0
0
0
1
0
0
8(2)
250
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
2. Minimum value for N.
MPC9855
4
Timing Solutions
Freescale Semiconductor
OPERATION INFORMATION
Output Frequency Configuration
The MPC9855 was designed to provide the commonly
used frequencies in PowerQUICC, PowerPC and other microprocessor systems. Table 3 lists the configuration values
that will generate those common frequencies. The MPC9855
can generate numerous other frequencies that may be useful
in specific applications. The output frequency (fout) may be
calculated by the following equation.
fout = 2000 / N
where fout is in MHz and N = 2 * CLK_x[0:5]
This calculation is valid for all values of N from 8 to 126.
Note that N = 15 is a modified case of the configuration inputs
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
00111 or 7.
Crystal Input Operation
The MPC9855 features a fully integrated Pierce oscillator
to minimize system implementation costs. Other than the
addition of a crystal no external components are required
The crystal selection should be 25 MHz, parallel resonant
type with a load specification of CL = 10 pF.
The crystal should be located as close to the MPC92469
XTAL_IN and XTAL_OUT pins as possible to avoid any board
level parasitic.
Power-Up and MR Operation
Figure 2 defines the release time and the minimum pulse
length for MR pin. The MR release time is based upon the
power supply being stable and within VDD specifications. See
Table 10 for actual parameter values. The MPC9855 may be
configured after release of reset and the outputs will be stable
for use after lock indication is obtained.
VDD
MR
treset_rel
treset_pulse
Figure 2. MR Operation
Power Supply Bypassing
The MPC9855 is a mixed analog/digital product. The
architecture of the XC9855 supports low noise signal
operation at high frequencies. In order to maintain its superior
signal quality, all VDD pins should be bypassed by
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
VDD
VDD
22 µF
0.1 µF
MPC9855
15 Ω
VDDA
0.1 µF
Figure 3. VCC Power Supply Bypass
Power Consumption
The total power consumption of the MPC9855 may be
calculated by the following formula:
P = VDD * (IDD + IDDA + IDDOC) +
(CPD * frequency * * 4 * VDDOA**2) +
(CPD * frequency * 4 * VDDOB**2)
where frequency is the programmed output frequency for
bank A and bank B.
MPC9855
Timing Solutions
Freescale Semiconductor
5
Table 4. Absolute Maximum Ratings(1)
Symbol
Min
Max
Unit
VDD
Supply Voltage (core)
–0.3
3.8
V
VDDA
Supply Voltage (Analog Supply Voltage)
–0.3
VDD
V
VDDOA
Supply Voltage (LVCMOS output for Bank A)
–0.3
VDD
V
VDDOB
Supply Voltage (LVCMOS output for Bank B)
–0.3
VDD
DC Input Voltage
–0.3
VDD+0.3
V
DC Output Voltage(2)
–0.3
VDDx+0.3
V
DC Input Current
±20
mA
DC Output Current
±50
mA
125
°C
VIN
VOUT
IIN
IOUT
TS
Characteristics
Storage Temperature
–65
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
2. VDDx references power supply pin associated with specific output pin.
Table 5. General Specifications
Symbol
Characteristics
Min
Typ
Max
VDD ÷ 2
Unit
VTT
Output Termination Voltage
MM
ESD Protection (Machine Model)
200
HBM
ESD Protection (Human Body Model)
2000
V
CDM
ESD Protection (Charged Device Model)
500
V
200
Condition
V
V
LU
Latch-Up Immunity
CIN
Input Capacitance
4
mA
pF
Inputs
CPD
Power Dissipation Capacitance
6
pF
Per Output
θJC
Thermal Resistance (junction-to-ambient)
TA
Ambient Temperature
°C/W Air Flow = 0
54.5
–40
85
°C
Table 6. DC Characteristics (TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
160
mA
VDD + VDDA +
VDDOC pins
15
mA
VDDIN pins
140
mA
VDD + VDDA +
VDDOC pins
15
mA
VDDIN pins
Supply Current for VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5%, = VDDOB = 3.3 V ± 5%
IDD + IDDA Maximum Quiescent Supply Current (Core)
+ IDDOC
IDDA
Maximum Quiescent Supply Current (Analog Supply)
Supply Current for VDD = 3.3 V ± 5%, VDDOA = 2.5 V ± 5%, VDDOB = 2.5 V ± 5%
IDD + IDDA Maximum Quiescent Supply Current (Core)
+ IDDOC
IDDA
Maximum Quiescent Supply Current (Analog Supply)
MPC9855
6
Timing Solutions
Freescale Semiconductor
Table 7. LVPECL DC Characteristics (TA = –40°C to 85°C)(1)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential LVPECL clock inputs (CLK1, CLK1) for VDD = 3.3 V ± 0.5%
VPP
VCMR
Differential Voltage(2) (peak-to-peak)
(LVPECL)
250
Differential Input Crosspoint Voltage(3)
(LVPECL)
1.0
mV
VDD – 0.6
V
1. AC characteristics are design targets and pending characterization.
2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay,
device and part-to-part skew.
Table 8. LVCMOS I/O DC Characteristics (TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
VDD + 0.3
V
Condition
LVCMOS for VDD = 3.3 V ± 5%
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
2.0
(1)
LVCMOS
0.8
V
LVCMOS
200
µA
VIN = VDDL or GND
V
IOH = –12 mA
V
IOL = 12 mA
LVCMOS for VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5%, VDDOB = 3.3 V ± 5%
VOH
Output High Voltage
VOL
Output Low Voltage
ZOUT
Output Impedance
2.4
0.4
Ω
14 – 17
LVCMOS for VDD = 3.3 V ± 5%, VDDOA = 2.5 V ± 5%, VDDOB = 2.5 V ± 5%
VOH
Output High Voltage
VOL
Output Low Voltage
ZOUT
Output Impedance
1.9
0.4
18 – 22
V
IOH = –10 mA
V
IOL = 10 mA
Ω
1. Inputs have pull-down resistors affecting the input current.
MPC9855
Timing Solutions
Freescale Semiconductor
7
Table 9. AC Characteristics (VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5%, VDDOB = 3.3 V ± 5%, TA = –40°C to +85°C)(1) (2)
Symbol
Characteristics
Min
Typ
Max
Unit
250
MHz
MHz
MHz
MHz
Condition
Input and Output Timing Specification
fref
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
25
33
25
Input Reference Frequency in PLL Bypass Mode(3)
fVCO
VCO Frequency Range(4)
fMCX
Output Frequency
frefPW
Reference Input Pulse Width
frefCcc
Input Frequency Accuracy
2000
Bank A output
Bank B output
Bank C output
MHz
MHz
MHz
MHz
200
200
500
15.87
15.87
50
PLL bypass
2
PLL locked
ns
100
ppm
500
ns
20% to 80%
52.5
55
%
3.3 V operation
2.5 V operation
PLL Closed Loop Bandwidth(5)
1
MHz
Maximum PLL Lock Time
10
ms
tr, tf
Output Rise/Fall Time
DC
Output Duty Cycle
80
47.5
45
50
50
PLL Specifications
BW
tLOCK
treset_ref
treset_pulse
MR Hold Time on Power Up
10
ns
MR Hold Time
10
ns
Skew and Jitter Specifications
tsk(O)
Output-to-Output Skew (within a bank)
50
ps
tsk(O)
Output-to-Output Skew (across banks A and B)
100
ps
VDDOA = 3.3 V
VDDOB = 3.3 V
tJIT(CC)
Cycle-to-cycle jitter
150
80
ps
Bank A and B
Back C
tJIT(PER)
Period Jitter
150
80
ps
Bank A and B
Back C
15
15
ps
Bank A and B
Back C
tJIT(∅)
RMS (1 σ)
I/O Phase Jitter
1.
2.
3.
4.
AC characteristics are design targets and pending characterization.
AC characteristics apply for parallel output termination of 50 Ω to VTT.
In bypass mode, the MPC9855 divides the input reference clock.
The input reference frequency must match the VCO lock range divided by the total feedback divider ratio:
fref = (fVCO ÷ M) ⋅ N.
5. –3 dB point of PLL transfer characteristics.
Pulse
Generator
Z = 50Ω
ZO = 50Ω
RT = 50Ω
ZO = 50Ω
DUT MPC9855
RT = 50Ω
VTT
VTT
Figure 4. MPC9855 AC Test Reference (LVCMOS Outputs)
MPC9855
8
Timing Solutions
Freescale Semiconductor
Table 10. MPC9855 Pin Diagram (Top View)
1
2
3
4
5
6
7
8
9
10
A
VDDOA
VDDOA
CLKA[1]
CLKA[3]
CLKA[5]
VDD
QA1
QA2
VDDOA
VDDOA
B
VDDOA
VDDOA
CLKA[0]
CLKA[2]
CLKA[4]
QA0
VDDOA
QA3
VDDOA
VDDOA
C
RSVD
RSVD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
REF_OUT[0]
D
VDDA
VDDA
VDD
GND
GND
GND
GND
VDD
RSVD
REF_OUT[1]
E
XTAL_SEL
CLK
VDD
GND
GND
GND
GND
VDD
VDD
GND
F
PCLK
PCLK
VDD
GND
GND
GND
GND
VDD
RSVD
RSVD
G
CLK_SEL
REF_33MHz
VDD
GND
GND
GND
GND
VDD
PLL_BYPASS
MR
H
XTAL_IN
XTAL_OUT
VDD
VDD
VDD
VDD
VDD
VDD
RSVD
REF_OUT1E
J
VDDOB
VDDOB
CLKB[0]
CLKB[2]
CLKB[4]
QB0
VDDOB
QB3
VDDOB
VDDOB
K
VDDOB
VDDOB
CLKB[1]
CLKB[3]
CLKB[5]
VDD
QB1
QB2
VDDOB
VDDOB
Table 11. MPC9855 Pin List
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
VDDOA
A1
RSVD
C1
XTAL_SEL
E1
CLK_SEL
G1
VDDOB
J1
VDDOA
A2
RSVD
C2
CLK
E2
REF_33MHz
G2
VDDOB
J2
CLKA[1]
A3
VDD
C3
VDD
E3
VDD
G3
CLKB[0]
J3
CLKA[3]
A4
VDD
C4
GND
E4
GND
G4
CLKB[2]
J4
CLKA[5]
A5
VDD
C5
GND
E5
GND
G5
CLKB[4]
J5
VDD
A6
VDD
C6
GND
E6
GND
G6
QB0
J6
QA1
A7
VDD
C7
GND
E7
GND
G7
VDDOB
J7
QA2
A8
VDD
C8
VDD
E8
VDD
G8
QB3
J8
VDDOA
A9
VDD
C9
VDD
E9
PLL_BYPASS
G9
VDDOB
J9
VDDOA
A10
REF_OUT[0]
C10
GND
E10
MR
G10
VDDOB
J10
VDDOA
B1
VDDA
D1
PCLK
F1
XTAL_IN
H1
VDDOB
K1
VDDOA
B2
VDDA
D2
PCLK
F2
XTAL_OUT
H2
VDDOB
K2
CLKA[0]
B3
VDD
D3
VDD
F3
VDD
H3
CLKB[1]
K3
CLKA[2]
B4
GND
D4
GND
F4
VDD
H4
CLKB[3]
K4
CLKA[4]
B5
GND
D5
GND
F5
VDD
H5
CLKB[5]
K5
QA0
B6
GND
D6
GND
F6
VDD
H6
VDD
K6
VDDOA
B7
GND
D7
GND
F7
VDD
H7
QB1
K7
QA3
B8
VDD
D8
VDD
F8
VDD
H8
QB2
K8
VDDOA
B9
RSVD
D9
RSVD
F9
RSVD
H9
VDDOB
K9
VDDOA
B10
REF_OUT[1]
D10
RSVD
F10
REF_OUT1E
H10
VDDOB
K10
MPC9855
Timing Solutions
Freescale Semiconductor
9
PACKAGE DIMENSIONS
B
C
11
A1 INDEX
AREA
K
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED
PARALLEL TO DATUM A.
4. DATUM A, SEATING PLANE, IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGING.
11
9X
0.2
4X
TOP VIEW
SIDE VIEW
1
0.5
5
0.35 A
K
J
H
9X
1
1.7 MAX
(1.18)
G
F
0.43
0.29
E
D
C
4
A
SEATING
PLANE
100X
0.12 A
0.5
B
A
100X
1
2
A1 INDEX
AREA
3
4
5
6
7
8
9
10
0.55
0.45
0.25
M
A B C
0.10
M
A
3
DETAIL K
ROTATED 90˚ CLOCKWISE
BOTTOM VIEW
VA SUFFIX
VM SUFFIX (Pb-FREE)
100 MAPBGA PACKAGE
CASE 1462-01
ISSUE O
MPC9855
10
Timing Solutions
Freescale Semiconductor
NOTES
MPC9855
Timing Solutions
Freescale Semiconductor
11
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
[email protected]
MPC9855
Rev. 2
1/2005
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2005. All rights reserved.