TAS3308 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE www.ti.com SLES215A – FEBRUARY 2008 – REVISED MARCH 2008 FEATURES 1 • Audio Input/Output – Up to Three Synchronous Serial Audio Inputs (6 Channels) – Up to Two Synchronous Serial Audio Outputs (4 Channels) – Left, RIght and I2S Input Data Formats: 16-, 20-, or 24-Bit Data – Left, Right and I2S Output Data Formats: 16-, 20-, or 24-Bit Data – 64 × Fs Bit Clock Rate – 24.576-MHz XTAL Input for Master Clock Modes and Clock Auto Detection – Slave Mode 256, 384, or 512 × Fs MCLKIN With Automatic Clock Rate Detection – Slave Mode 32-, 44.1-, and 48-kHz Fs With Auto Sample Rate Detection – Master Mode – 48-kHz Fs 10 Multiplexed Stereo Analog Inputs Selectable Into One Stereo ADC. ADC Maximum Input Level: 1 Vrms SE – Three Stereo Differential PWM Outputs – High-Quality DNR 100-dBA (Typical) ADC Channel Performance (2 Channels) With Master Mode Clock – High-Quality DNR 105-dBA (Typical) PWM Channel Performance (6 Channels) – One Single-Ended Analog Stereo Line Driver Output With 1 of 10 Selectable Inputs, 10-kΩ, 100=pF Drive Capability (Maximum Output Level: 1 Vrms) – Line-Out Supports Left/Right, Left/Left, and Right/Right Combinations 2 • • • Audio Digital Signal Processor – Programmable Functionality – 135-MHz Operation – 48-Bit Datapath With 76-Bit Accumulator – Hardware Single Cycle Multiplier (28 × 48) – Two Memory Loads and One Memory Store Per Cycle – Usable 1K Words Data RAM (48 Bit) and Usable 1K Coefficient RAM (28 Bit) – 3.25K Words Instruction Program RAM (2.8K Words Available) – 360 mS at 48 KHz, 17,408 Words 24-Bit Delay Memory PWM Features – Proven PurePath Digital™ Technology – Fourth-Order Chaotic Noise Shaper With Non-Linear Correction – High-Quality DNR 105 dBA (Typical) PWM Performance – Click and Pop Minimizing at Power Up/Down Using TI Patented Technology General Features – Easy-to-Use Control Interface – I2C Serial Control Master and Slave Interface – Control Interface Operational Without External MCLK Input – Single 3.3-V Power Supply – Integrated Regulators – 100-Pin TQFP Package – M8051 Device Controller – Auto Clock and Serial Data Rate Detection and Automatic Device Configuration Without Audible Artifacts 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Digital is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TAS3308 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE www.ti.com SLES215A – FEBRUARY 2008 – REVISED MARCH 2008 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DVSS_PWM2 PWM2_Li PWM2_LO PWM1_RI PWM1_RO DVDD_PWM1 DVSS_PWM1 PWM1_LI PWM1_LD VR_DIG1 DVSS1 DVDD1 VR_ANA AVSS_OSC XTAL_OUT XTAL_IN AVDD_OSC VR_ANA2 AVSS_PLL PLL_FLTM PLL_FLTP AVDD_PLL AVSS_LO LINEOUT1R LINEOUT1R PZT PACKAGE (TOP VIEW) DVDD_PWM2 PWM2_RD PWM2_RI PWM3_LD PWM3_LI DVSS_PWM3 DVDD_PWM3 PWM3_RD PWM3_RI VALID/SYNC DVDD2 DVSS2 VREG_EN RSVD MCLKOUT LRCLKOUT SCLKOUT SDOUT1 SDOUT2/SPDIF_OUT SPDIF_IN SDIN3 SDIN2 SDIN1 LRCLKIN SCLKIN 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AVDD_LO AVDD_REF V1P5_REF BG_REF BIAS_REF LINEIN10R LINEIN10L AVSS_LI3 LINEIN9R LINEIN9L AVDD_LI3 LINEIN8R LINEIN8L AVDD_ADC LINEIN7R LINEIN7L AVSS_ADC/REF LINEIN6R LINEIN6L AVSS_LI2 LINEIN5R LINEIN5L AVDD_LI2 LINEIN4R LINEIN4L MCLKIN DVSS_DPLL VR_DIG2 DVDD3 DVSS3 I2C_SDA2 I2C_SCL2 I2C_SDA1 I2C_SCL1 CS GPIO1 GPIO2 MUTE RESET DVSS4 VR_DIG3 DVDD4 LINEIN1L LINEIN1R AVSS_LI1 LINEIN2L LINEIN2R AVDD_LI1 LINEIN3L LINEIN3R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DESCRIPTION/ORDERING INFORMATION TAS3308 is an audio system-on-a-chip (SOC) designed for digital TV audio systems and mini/micro component applications. It includes analog and digital audio interface. For analog input and output the TAS3308 has ten multiplexed stereo inputs with one stereo ADC and three stereo PWM outputs. For digital input and output the TAS3308 has three I2S inputs and two I2S outputs. One I2S output can also be configured to be S/PDIF encoded PCM data. TAS3308 has a programmable audio DSP that preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single cycle 28 × 48-bit multiplier. The programmability feature allows users to customize features in the DSP RAM. ORDERING INFORMATION TA 0°C to 70°C (1) 2 PACKAGE TQFP – PZT (1) ORDERABLE PART NUMBER Tray TAS3308PZT Tape and reel TAS3308PZTR TOP-SIDE MARKING For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3308 TAS3308 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE www.ti.com SLES215A – FEBRUARY 2008 – REVISED MARCH 2008 The TAS3308 comprises nine functional blocks. • Analog input/MUX/stereo ADC • Three stereo PWM output for speaker/headphone/stereo • Line driver outputs • Clock, digital PLL, analog PLL, serial data interface, and auto-detect system • Serial control interface/device control • Audio DSP – digital audio processing • 8051 device controller • Power supply • Internal references RESET CS0 I2C_2 I2C_1 GPIO1–2 PLL FILTER MUTE BLOCK DIAGRAM MCLK APLL 2 PWMCLK, ADCCLK IC RESET POWER AutoDetect XTAL SDIN1–3, LRCLKI, SCLKI OSC %2 DPLL DIGCLK Input Serial Audio Port 1–3 REFERENCE 8051 Device Micro-Controller 1024 W DATA RAM Output Serial Audio Port 1024 W COEF RAM LRCLKO, SCLKO, MCLKO SDOUT1 360 MS DELAY RAM SPDIF Digital Audio Processor SPDOUT/SDOUT2 SPDIN 10 STEREO ANALOG IN Stereo ADC Sync Decimation Decimation FW Interpolation PWM 1–3 VALID PWM1L(I+D),R(I+D) PWM2L(I+D),R(I+D) PWM3L(I+D),R(I+D) LINEOUT1(L+R) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3308 3 TAS3308 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE www.ti.com SLES215A – FEBRUARY 2008 – REVISED MARCH 2008 APPLICATION INFORMATION 3.3V TAS3308 DVDD1 0.1 u 10p (TBD) DVSS1 MCLK_IN 3.3V XTAL_OUT 1M SCLK_IN DVDD2 0.1 u 24.576M XTAL_IN LRCLK_IN 10p (TBD) DVSS2 SDIN_1 SDIN_2 3.3V DVDD3 0.1 u DVSS3 VR_ANA2 SDIN_3 AVDD_PLL GPIO_1 AVSS_PLL 3.3V 0.1u 4.7u 0.01u 0.1u GPIO_2 3.3V DVDD4 0.1 u DVSS4 MUTE PLL_FLTM RSVD PLL_FLTP RESET VREG_EN 220 220 0.01u 0.1u I2C_SCL1 I2C_SDA1I 3.3V AVDD_LI1 VR_ANA1 AVSS_SOC VR_ANA2 AVSS_PLL VR_DIG1 DVSS1 VR_DIG2 DVSS_DPLL VR_DIG3 DVSS4 4. 7u 0.1u AVSS_LI1 4.7 u 3.3V AVDD_LI2 4.7 u AVSS_LI2 4.7 u 0.1u 3.3V 4.7 u AVDD_LI3 0.1u CS MCLKOUT SCLKOUT LRCLKOUT SDOUT1 SPDIFOUT/SDOUT2 47K AVSS_LI3 I2C_SCL2 I2C_SDA2 LINEIN1L SPDIFIN 47K LINEIN2L 3.3V PWM1LI 47K AVDD_OSC LINEIN3L 0.1u 47K AVSS_OSC 47K 3.3V 47K AVDD_REF 47K 0.1u 47K 3.3V LINEIN4L LINEIN5L PWM1RI LINEIN7L 47K PWM2LI PWM2RI 47K AVSS_LO LINEIN10L LPF PWM2LD LINEIN9L 0.1u LPF PWM1RD LINEIN6L LINEIN8L AVDD_LO LPF PWM1LD LPF PWM2RD 3.3V 47K AVDD_ADC LINEIN1R 47K 0.1u AVSS_ADC/REF 47K 47K 47K 22 DVDD_PWM1 47K LINEIN3R PWM3LD LINEIN5R LINEIN7R 47K 22 LINEIN8R DVDD_PWM2 47K LINEIN9R 10u 47K LINEIN10R DVSS_PWM2 22 DVDD_PWM3 10u DVSS_PWM3 BIAS_REF 24 K <5% LPF PWM3RI VALID/SYNC 47K DVSS_PWM1 LPF PWM3LI LINEIN4R LINEIN6R 10u PWM3RD LINEIN2R 47 2. 2u 47 2. 2u LINEOUT1L LINEOUT1R V1P5_REF VREG_EN BG_REF STEST 1u 10k 10k 1u Figure 1. Peripheral Connections 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3308 TAS3308 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE www.ti.com SLES215A – FEBRUARY 2008 – REVISED MARCH 2008 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) DVDD AVDD Supply voltage range DVDD_PWM VI Input voltage range VO Output voltage range MIN MAX –0.5 3.8 –0.5 3.8 –0.5 3.8 3.3 V TTL –0.5 VDDS + 0.5 3.3 V LVCMOS –0.5 VDDS + 0.5 3.3 V analog –0.5 AVDDS + 0.5 1.8 V LVCMOS –0.5 AVDD (2) + 0.5 3.3 V TTL –0.5 VDDS + 0.5 3.3 V LVCMOS –0.5 VDDS + 0.5 3.3 V analog –0.5 AVDDS + 0.5 –0.5 DVDD (3) + 0.5 –0.5 AVDD (4) + 0.5 1.8 V LVCMOS UNIT V V V IIK Input clamp current VI < 0 or VI > DVDD ±20 mA IOK Output clamp current VO < 0 or VO > DVDD ±20 mA Tstg Storage temperature range 150 °C 260 °C –65 Lead temperature 1.6 mm (1/16) inch from case for 10 seconds (1) (2) (3) (4) Stresses beyond those listed under “absolute ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operation conditions” is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability. AVDD is an internal 1.8-V supply derived from a regulator in the TAS3308 chip. Pin XTALI is the only TAS3308 input that is referenced to this 1.8-V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALI. DVDD is an internal 1.8-V supply derived from regulators in the TAS3308 chip. DVDD is routed to DVDD_BYPASS_CAP to provide access to external filter capacitors, but should not be used to source power to external devices. Pin XTALO is the only TAS3308 output that is derived from the internal 1.8-V logic supply AVDD. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALO. AVDD is also routed to AVDD_BYPASS_CAP to provide access to external filter capacitors, but should not be used to source power to external devices. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER DVDD Digital supply voltage AVDD Analog supply voltage DVDD_PWM PWM supply voltage VIH High-level input voltage MEASUREMENTS MIN NOM MAX 3 3.3 3.6 V 3.3 V analog 3 3.3 3.6 V 3.3 V PWM 3 3.3 3.6 V 3.3 V TTL 2 3.3 V LVCMOS (I2C) 1.8 V LVCMOS (XTL_IN) 0.7 × VDDS V 1.26 3.3 V TTL VIL Low-level input voltage 3.3 V LVCMOS (I2C) 0.8 0.3 × VDDS 0 1.8 V LVCMOS (XTL_IN) TA Operating ambient air temperature range (specifying parametrics) (specifying functions) Product Folder Link(s): TAS3308 V 0.54 0 25 70 –20 25 70 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated UNIT °C 5 TAS3308 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE www.ti.com SLES215A – FEBRUARY 2008 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER VOH High-level output voltage MEASUREMENT IOH = –4 mA 3.3 V LVCMOS (I2C) IOH = –0.10 mA 1.8 V LVCMOS (XTL_OUT) IOH = –0.6 mA 3.3 V TTL Low-level output voltage High-impedance output current IOZ IIL (1) IIH (2) IDVDD Low-level input current High-level input current MIN MAX UNITS 2.4 V VDDS – 0.2 V 1.197 V IOL = 4 mA 0.5 V 3.3 V LVCMOS (I C) IOL = 0.10 mA 0.2 V 1.8 V LVCMOS (XTL_OUT) IOL = 1.8 mA 0.585 V ±20 µA 2 VOL TEST CONDITIONS 3.3 V TTL 3.3 V TTL 3.3 V LVCMOS (I C) Driver only, driver disable ±20 µA 3.3 V TTL VI = VIL ±1 µA 3.3 V LVCMOS (I2C) VI = VIL, Receiver only ±1 µA 1.8 V LVCMOS (XTL_IN) VI = VIL ±1 µA 1.8 V LVCMOS (XTL_IN) VI = VIH ±1 µA 3.3 V LVCMOS (I2C) VI = VIH, Receiver only ±1 µA 3.3 V TTL VI = VIH ±1 µA DSP clock = 135 MHz LRCLKIN/LRCLKOUT = 48 KHz, XTALI = 24.576 MHz 160 mA DSP clock = 135 MHz LRCLKIN/LRCLKOUT = 48 KHz, XTALI = 24.576 MHz 40 mA 2 Digital supply current Analog supply current IAVDD IDVDD Digital supply current RESET = LOW 100 mA IAVDD Analog supply current RESET = LOW 10 mA (1) (2) 6 Value given is for those input pins that connect to an internal pullup resistor as well as an input buffer. For inputs that have a pulldown resistor or no resistor, IIL is ±1 µa. Value given is for those input pins that connect to an internal pulldown resistor as well as an input buffer. For inputs that have a pullup resistor or no resistor, IIH is ±1 µa. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3308 PACKAGE OPTION ADDENDUM www.ti.com 6-Mar-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TAS3308PZT ACTIVE TQFP PZT 100 TAS3308PZTR ACTIVE TQFP PZT 100 90 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS3308PZTR Package Package Pins Type Drawing TQFP PZT 100 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 17.0 17.0 1.5 20.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS3308PZTR TQFP PZT 100 1000 346.0 346.0 41.0 Pack Materials-Page 2 MECHANICAL DATA MTQF012B – OCTOBER 1994 – REVISED DECEMBER 1996 PZT (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 0,13 NOM 25 1 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 1,20 MAX 0,08 4073179 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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