ETC UPD17107

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD17107(A1)
4 BIT SINGLE-CHIP MICROCONTROLLER
The µPD17107(A1) is a tiny microcontroller consisting of 1K-byte (512 × 16 bits) ROM, 16 × 4 bit RAM, and 11
input/output ports.
The 17K architecture, which uses general registers to directly manipulate data memory, is employed for effective
programming. Every instruction is 1 word long, consisting of 16 bits.
FEATURES
• Program memory (ROM)
: 1K bytes (512 × 16 bits)
• Data memory (RAM)
: 16 × 4 bits
• Input/output ports
: 11 ports (including three
• Data memory can retain data on low voltage
(2.0 V at minimum).
• An RC oscillatorNote for the system clock:
With a built-in capacitor (only a resistor is
N-ch open-drain outputs)
• Instruction execution time
: 128 µs (at fCC = 62.5 KHz) to
8 µs (at fCC = 1 MHz)
• Stack level
required to be connected.)
• Supply voltage: VDD = 2.5 to 6.0 V (at fCC = 250 kHz)
VDD = 4.5 to 6.0 V (at fCC = 1 MHz)
: 1
• Operating ambient temperature: TA = –40 to +110 ˚C
• A standby function
(with the HALT and STOP modes)
Note The capacitor for RC oscillator is contained in the µPD17107(A1).
APPLICATIONS
Electronic units for automobiles, and suchlike
ORDERING INFORMATION
Part number
Package
Quality grade
µPD17107CX(A1)-×××
16-pin plastic DIP
(300 mil)
Special
µPD17107GS(A1)-×××
16-pin plastic SOP (300 mil)
Special
Remark
××× : ROM code number
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Each device has a different capacity of a built-in capacitor for system clock oscillation of the µPD17107(A1). This causes
the frequency deviation within about 30% even though the connected resistors have the same value.
Use the µ PD17103(A1) (ceramic based oscillation) when the deviation is a critical problem.
The information in this document is subject to change without notice.
Document No. U10915EJ1V0DS00 (1st edition)
Date Published January 1996 P
Printed in Japan
©
1996
µPD17107(A1)
FUNCTIONS
Item
Function
ROM
1K byte (512 × 16 bits)
RAM
16 × 4 bits
Stack
1 level
Number of I/O ports
11 (N-ch open-drain output ports: 3)
System clock (fCC)
RC oscillation
Instruction execution
time
128 µs (fCC = 62.5 kHz) to 8 µs (fCC = 1 MHz)
Standby function
HALT/STOP
Operating supply
voltage
2.5 to 6.0 V (at fCC = 62.5 kHz to 250 kHz)
4.5 to 6.0 V (at fCC = 62.5 kHz to 1 MHz)
Package
16-pin plastic DIP (300 mil)
16-pin plastic SOP (300 mil)
One-time PROM
µPD17P107
The quality grade is "Standard," not "A1."
Operating ambient temperature: TA = –40 to
+85 °C
Caution Although a PROM product is highly compatible with a masked ROM product in respect of
functions, they differ in internal ROM circuits and part of electrical characteristics. Before
changing the PROM product to the masked ROM product in an application system, evaluate the
system carefully using the masked ROM product.
PIN CONFIGURATION (TOP VIEW)
16-pin plastic DIP
16-pin plastic SOP
1
16
GND
OSC0
2
15
P0B2
RESET
3
14
P0B1/RLSSTOP
P0D0
4
13
P0B0/RLSHALT
P0D1
5
12
P0C3
P0D2
6
11
P0C2
P0D3
7
10
P0C1
VDD
8
9
P0C0
µ PD17107CX (A1)- × × ×
µ PD17107GS (A1)- × × ×
2
OSC1
µPD17107(A1)
BLOCK DIAGRAM
System clock
generator
CPU CLK
N-ch open drain
P0B0/RLSHALT
P0B1/RLSSTOP
P0B2
OSC0
OSC1
CLK STOP
RAM
16 × 4 bits
P0B
CMOS
P0C0
P0C1
P0C2
P0C3
ALU
P0C
CMOS
P0D0
P0D1
P0D2
P0D3
RESET
P0D
ROM
512 × 16 bits
Instruction
decoder
Program counter
VDD
GND
Stack1 × 9 bits
3
µPD17107(A1)
PIN FUNCTIONS
Pin functions
• Port pins
Pin
I/O
P0B0/RLSHALT
I/O
P0B1/RLSSTOP
Function
Reset
•
For releasing the HALT mode
For releasing the STOP mode
P0B2
•
•
•
N-ch open-drain 3-bit I/O port (port 0B)
A built-in pull-up resistor can be connected with a mask
option bit by bit.
This open-drain port has a withstand voltage of 9 V.
•
Open-drain:
High impedance
(input mode)
With pull-up resistor
selected:
High level (input mode)
P0C0-P0C3
I/O
CMOS (push-pull) 4-bit I/O port (port 0C)
High impedance (input mode)
P0D0-P0D3
I/O
CMOS (push-pull) 4-bit I/O port (port 0D)
High impedance (input mode)
• Non-port pins
I/O
RESET
Input
VDD
–
Positive power supply pin
GND
–
GND pin
OSC0, OSC1
–
Pins to be connected to the resistor for system clock oscillation
I/O: Input/output
4
Function
Pin
•
•
Reset input pin
A built-in pull-up resistor can be connected with a mask option.
µPD17107(A1)
Equivalent input/output circuits
Below are simplified diagrams of the equivalent input/output circuits.
(1) P0C and P0D
V DD
Data
P-ch
IN / OUT
N-ch
Output
disable
V DD
P-ch
N-ch
(2) P0B0 and P0B1
V DD
Pull-up resistor
(mask option)
IN / OUT
Data
N-ch
Output
disable
Stand-by
release
V DD
P-ch
N-ch
5
µPD17107(A1)
(3) P0B2
V DD
Pull-up resistor
(mask option)
IN / OUT
Data
N-ch
Output
disable
V DD
P-ch
N-ch
(4) RESET
V DD
Pull-up resistor
(mask option)
IN
6
µPD17107(A1)
HANDLING UNUSED PINS
When connecting unused pins, the following conditions and handling are recommended:
Recommended conditions and handling
Pin
Internal
Port
Input
mode
—
P0C, P0D
P0B
External
Pull-up resistors that can be specified by
the mask option are not incorporated.
Pull-up resistors that can be specified with
the mask option are incorporated.
Output
mode
P0C, P0D
(CMOS port)
—
P0B
(N-ch opendrain port)
Outputs low level without pull-up resistors
that can be specified with the mask option.
Connect each pin to VDD or to ground
through a resistorNote.
Leave open.
Outputs high level with pull-up resistors that
can be specified with the mask option.
Note When a pin is pulled up (connected to VDD through a resistor) or pulled down (connected to ground through
a resistor) outside the chip, take the driving capacity and maximum current consumption of a port into
consideration. When using high-resistance pull-up or pull-down resistors, apply appropriate countermeasures to ensure that noise is not attracted by the resistors. Although the optimum pull-up or pull-down resistor
varies with the application circuit, in general a resistor of 10 to 100 kilohms is suitable.
Caution To fix the output level of a pin, it is recommended that the level be specified repeatedly within
a loop in a program.
NOTES ON USE OF THE RESET PIN
The RESET pin has the test mode selecting function for testing the internal operation of the µPD17107(A1)
(IC test), besides the functions shown in "PIN FUNCTIONS."
Applying a voltage exceeding VDD to the RESET pin causes the µPD17107(A1) to enter the test mode. When noise
exceeding VDD comes in during normal operation, the device is switched to the test mode.
For example, if the wiring from the RESET pin is too long, noise may be induced on the wiring, causing this mode
switching.
When installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. If noise
yet arises, use an external part to suppress it as shown below.
•
Connect a diode with low VF between the pin
•
Connect a capacitor between the pin and VDD.
and VDD.
VDD
Diode with
low VF
VDD
VDD
RESET
VDD
RESET
7
µPD17107(A1)
CONTENTS
1.
PROGRAM COUNTER (PC) ......................................................................................................
10
1.1
CONFIGURATION OF THE PROGRAM COUNTER (PC) ............................................................
10
1.2
FUNCTIONS OF THE PROGRAM COUNTER (PC) .....................................................................
10
2.
STACK .........................................................................................................................................
11
3.
PROGRAM MEMORY (ROM) .....................................................................................................
12
4.
DATA MEMORY (RAM) ..............................................................................................................
13
4.1
CONFIGURATION OF THE DATA MEMORY (RAM) ...................................................................
13
4.1.1
Functions of the General Data Memory ......................................................................
13
4.1.2
Functions of the General Register ..............................................................................
13
4.1.3
Functions of the Port Register ....................................................................................
13
4.1.4
Functions of the System Register ...............................................................................
14
ALU BLOCK ................................................................................................................................
17
5.1
ALU BLOCK CONFIGURATION ....................................................................................................
17
5.2
FUNCTIONS OF THE ALU BLOCK ...............................................................................................
17
5.
5.3
Functions of the ALU ....................................................................................................
17
Functions of Temporary Registers A and B ..............................................................
22
5.2.3
Functions of the Status Flip-Flop ................................................................................
22
5.2.4
Performing Operations in 4-Bit Binary .......................................................................
23
5.2.5
Performing Operations in BCD ....................................................................................
23
5.2.6
Performing Operations in the ALU Block ..................................................................
24
ARITHMETIC OPERATIONS (ADDITION AND SUBTRACTION IN 4-BIT BINARY AND BCD) .
25
5.3.1
Addition and Subtraction When CMP = 0 and BCD = 0 ...........................................
25
5.3.2
Addition and Subtraction When CMP = 1 and BCD = 0 ...........................................
25
5.3.3
Addition and Subtraction When CMP = 0 and BCD = 1 ...........................................
26
5.3.4
Addition and Subtraction When CMP = 1 and BCD = 1 ...........................................
26
5.3.5
Warnings Concerning Use of Arithmetic Operations ...............................................
27
5.4
LOGICAL OPERATIONS ................................................................................................................
27
5.5
BIT EVALUATIONS ........................................................................................................................
28
5.5.1
TRUE (1) Bit Evaluation ................................................................................................
28
5.5.2
FALSE (0) Bit Evaluation ..............................................................................................
29
5.6
5.7
8
5.2.1
5.2.2
COMPARISON EVALUATIONS .....................................................................................................
29
5.6.1
"Equal" Evaluation ........................................................................................................
30
5.6.2
"Not Equal" Evaluation .................................................................................................
30
5.6.3
"Greater Than or Equal" Evaluation ...........................................................................
31
5.6.4
"Less Than" Evaluation ................................................................................................
31
ROTATIONS ....................................................................................................................................
32
5.7.1
Rotation to the Right .....................................................................................................
32
5.7.2
Rotation to the Left ........................................................................................................
33
µPD17107(A1)
6.
7.
8.
9.
PORTS .........................................................................................................................................
34
6.1
PORT 0B (P0B0/RLSHALT, P0B1/RLSSTOP, P0B2) ..........................................................................
34
6.2
PORT 0C (P0C0 TO P0C3) ..............................................................................................................
34
6.3
PORT 0D (P0D0 TO P0D3) ..............................................................................................................
34
6.4
NOTES ON MANIPULATING PORT REGISTERS .......................................................................
36
STANDBY FUNCTIONS .............................................................................................................
37
7.1
HALT MODE ....................................................................................................................................
37
7.2
STOP MODE ....................................................................................................................................
37
7.3
SETTING AND RELEASING THE STANDBY MODES ................................................................
37
7.4
HARDWARE STATUSES IN STANDBY MODE ...........................................................................
38
7.5
TIMING FOR RELEASING THE STANDBY MODES ...................................................................
38
RESET FUNCTION .....................................................................................................................
40
8.1
RESET FUNCTION .........................................................................................................................
40
RESERVED WORDS USED IN ASSEMBLY LANGUAGE ......................................................
41
9.1
MASK-OPTION PSEUDO INSTRUCTIONS ..................................................................................
41
9.1.1
OPTION and ENDOP Pseudo Instructions .................................................................
41
9.1.2
Mask-Option Definition Pseudo Instructions ............................................................
41
RESERVED SYMBOLS ..................................................................................................................
43
10. INSTRUCTION SET ....................................................................................................................
44
9.2
10.1
INSTRUCTION SET LIST ...............................................................................................................
44
10.2
INSTRUCTIONS ..............................................................................................................................
45
10.3
ASSEMBLER (AS17K) BUILT-IN MACRO INSTRUCTIONS .......................................................
47
11. ELECTRICAL CHARACTERISTICS ..........................................................................................
48
12. CHARACTERISTIC CURVES (REFERENCE) ..........................................................................
52
13. PACKAGE DRAWINGS ..............................................................................................................
54
14. RECOMMENDED SOLDERING CONDITIONS .........................................................................
58
APPENDIX DEVELOPMENT TOOLS .............................................................................................
59
9
µPD17107(A1)
1. PROGRAM COUNTER (PC)
1.1
CONFIGURATION OF THE PROGRAM COUNTER (PC)
As shown in Fig. 1-1, the program counter is a 9-bit binary counter.
Fig. 1-1 Program Counter
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
9 bits
1.2
FUNCTIONS OF THE PROGRAM COUNTER (PC)
The program counter specifies the address of a program memory (ROM) or a program.
Usually, every time an instruction is executed, the program counter is incremented by one. When a branch
instruction (BR), a subroutine call instruction (CALL), or a return instruction (RET) is executed, the address specified
in the operand is loaded in the PC. Then the instruction in the address is executed. When a skip instruction is executed,
the address of the instruction next to the skip instruction is specified irrespective of the contents of the skip instruction.
If the skip conditions are satisfied, the instruction next to the skip instruction is regarded as a No Operation (NOP)
instruction. So, the NOP instruction is executed and the address of the next instruction is specified.
10
µPD17107(A1)
2. STACK
Stack of the µPD17107(A1) is a register in which the return address of a program is saved when a subroutine call
instruction is executed. One level of address stack is provided.
Fig. 2-1 shows the relationship between the PC, the stack, and the operand of BR and CALL instructions.
Fig. 2-1 Relationship between the PC, the Stack, and the Operand of BR and CALL Instructions
Instructions
PC
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
RET
RETSK
CALL
Stack
S8
S7
S6
S5
S4
S3
S2
S1
S0
BR, CALL
Operand of BR and
CALL instructions
AH0
AM3
AM2
AM1
AM0
AL3
AL2
AL1
AL0
In Fig. 2-1, AHn, AMn, and ALn (0 ≤ n ≤ 3) indicate bit positions in a 16-bit instruction as follows:
Fig. 2-2 Configuration of a 16-Bit Instruction
MSB
BR and CALL
FH
instructions
LSB
EH
DH
CH
Operation code
BH
AH
9H
8H
7H
6H
5H
4H
3H
2H
1H
0H
AH2 AH1 AH0 AM3 AM2 AM1 AM0 AL3 AL2 AL1 AL0
Operand
When the assembler is not used and a BR or CALL instruction is used, AH2 and AH1 must be set to 0.
Reset input clears all bits of the program counter to 0.
11
µPD17107(A1)
3. PROGRAM MEMORY (ROM)
Fig. 3-1 shows the program memory (ROM) configuration.
As shown in the figure, the program memory has 512 words by 16 bits.
The program memory has been addressed in units of 16 bits. The addresses 0000H to 01FFH are specified by
the program counter (PC).
Every instruction is a 1 word long, consisting of 16 bits. One instruction can therefore be stored at one address
in program memory.
Address 0000H is used as a reset start address.
Fig. 3-1 Program Memory Map
16 bits
0000H
512 words
01FFH
12
µPD17107(A1)
4. DATA MEMORY (RAM)
The data memory (RAM) stores data of arithmetic/logic and control operations. Data can be always written to or
read from it by means of instructions.
4.1
CONFIGURATION OF THE DATA MEMORY (RAM)
Fig. 4-1 shows the configuration of the data memory (RAM).
The data memory is configured in units of four bits, or “one nibble,” and an address is assigned to each four bits
of data. The high-order three bits are called the “row address,” and the low-order four bits are called the “column
address.”
According to its functions, the data memory is divided into three blocks as shown below: General data memory,
port register, and system register.
Fig. 4-1 Data Memory Map
Column address
0
1
2
3
Row
address 0
7
4.1.1
4
5
6
7
8
9
A
B
C
D
E
F
General data memory (general register)
Port register
System register
Functions of the General Data Memory
The general data memory is a part of the data memory from which the system register (SYSREG) and port register
are excluded. By executing a data memory manipulation instruction, a four-bit arithmetic operation and comparison,
evaluation, and transfer between data on data memory and any immediate data can be executed with a single
operation.
4.1.2
Functions of the General Register
The general register indicates any identical row address (16 nibbles) in the data memory specified in the register
pointer (RP) in the system register. Since the µPD17107(A1) register pointer is always set to 0, the general data
memory is also used as a general register. The general register can operate or transfer data to and from the data
memory.
4.1.3
Functions of the Port Register
The port register is used to set output data or to read the input data of input/output ports.
Once data is written to the port register corresponding to a port, the port is set to output mode and outputs the
data unless another data is rewritten (the output mode is maintained until the port register is reset). Whenever a read
instruction is executed for a port register, the read data indicates the states of the pins, not the value of the port register,
regardless of whether the pins are in the input or output mode.
13
µPD17107(A1)
4.1.4 Functions of the System Register
The system register controls the CPU. The program status word (PSWORD) is the only system register in the
µPD17107(A1).
Fig. 4-2 System Register Map
Address
Data
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
0
0
0
0
0
0
0
0
0
0
7EH
7FH
Addresses 74H to 7DH are always set to 0.
7EH
7FH
PSWORD
PSW
B
C
D
C
Y
Z
Bit 0
Bit 1
0
Bit 2
0
Bit 3
0
Bit 0
0
C
M
P
Bit 0 at address 7EH and all four bits at address 7FH (PSW) are assigned to the program status word.
The BCD flag is mapped in bit 0 at address 7EH, the CMP flag is mapped in bit 3 at address 7FH, the CY flag
is mapped in bit 2, and the Z flag is mapped in bit 1 at address 7FH.
The high-order three bits at address 7EH and bit 0 at address 7FH are always set to 0.
14
µPD17107(A1)
Fig. 4-3 Configuration of the Program Status Word
Address 7EH
Address 7FH
Bit 0
Bit 3
PSW
BCD
CMP
CY
Z
Bit 0
0
Zero flag (Z)
Set to 1 when:
• An arithmetic operation generates a result
of zero if CMP = 0.
• An arithmetic operation generates a result
of zero and Z = 1 if CMP = 1.
When the Z flag is already 0, it remains
unchanged.
Reset to 0 when:
• An arithmetic operation generates a result
other than zero.
Carry flag
(CY)
Set to 1 when:
• An addition produces a carry or a subtraction
produces a borrow.
• The LSB of the operand in the RORC
instruction is 1.
Reset to 0 when:
• Neither a carry nor borrow is produced.
• The LSB of the operand in the RORC
instruction is 0.
Compare
flag (CMP)
If this flag is set, the result of an arithmetic
operation is not stored in memory or
general registers. The flag is automatically
reset by executing the SKT or SKF instruction.
BCD flag
(BCD)
If this flag is set, arithmetic operations are
performed in decimal, and if this flag is reset,
arithmetic operations are performed in binary.
Comparison instructions (SKE, SKNE, SKGE, or SKLT) do not change the state of the CY flag, but an arithmetic
operation may affect the CY flag according to the result even if the CMP flag is set.
Each bit of the program status word is initialized to 0 when a reset signal is applied.
The Z flag in the program status word changes according to the set value of the CMP flag as listed in Table
4-1.
15
µPD17107(A1)
Table 4-1 Change in Z Flag
Conditions
CMP = 0
CMP = 1
When arithmetic operation results in 0
Z←1
Z flag does not change
When arithmetic operation results in a non-zero value
Z←0
Z←0
While CMP is 1, if an arithmetic operation results in 0H when the value of the Z flag is 1, the Z flag does not change.
If an arithmetic operation results in other than 0H, the Z flag is reset to 0 and remains intact even when a second
arithmetic operation results in 0H.
After the CMP and Z flags are set to 1, subtraction and comparison are performed several times. Then, if the Z
flag still indicates 1, all of the comparison operations showed a match, resulting in 0. If the Z flag is 0 after the
comparison operations, a mismatch occurred in at least one comparison operation.
Example of 12-bit data comparison
; Is the 12-bit data stored in M001, M002, and M003 equal to 456H?
CMP456:
16
SET2
CMP, Z
SUB
M001, #4 ; Stores the data in M001, M002, and M003.
SUB
M002, #5 ; Does not damaged the data.
SUB
M003, #6 ;
; CLR1
CMP
SKT1
Z
; Resets CMP automatically when the bit test instruction is executed.
BR
DIFFER
; ≠ 456H
BR
AGREE
; = 456H
µPD17107(A1)
5. ALU BLOCK
The ALU is used for performing arithmetic operations, logical operations, bit evaluations, comparison evaluations,
and rotations on 4-bit data.
5.1 ALU BLOCK CONFIGURATION
Fig. 5-1 shows the configuration of the ALU block.
As shown in Fig. 5-1, the ALU block consists of the main 4-bit data processor, temporary registers A and B, the
status flip-flop for controlling the status of the ALU, and the decimal conversion circuit for use during arithmetic
operations in BCD.
As shown in Fig. 5-1, the status flip-flop consists of the following flags: Zero flag flip-flop, carry flag flip-flop, compare
flag flip-flop, and the BCD flag flip-flop.
Each flag in the status flip-flop corresponds directly to a flag in the program status word (PSWORD: addresses
7EH, 7FH) located in the system register. The flags in the program status word are the following: Zero flag (Z), carry
flag (CY), compare flag (CMP), and the BCD flag (BCD).
5.2 FUNCTIONS OF THE ALU BLOCK
Arithmetic operations, logical operations, bit evaluations, comparison evaluations, and rotations are performed
using the instructions in the ALU block. Table 5-1 lists each arithmetic/logical instruction, evaluation instruction, and
rotation instruction.
By using the instructions listed in Table 5-1, 4-bit arithmetic/logical operations, evaluations and rotations can be
performed in a single instruction. Arithmetic operations in BCD can also be performed on one place in a single
instruction.
5.2.1 Functions of the ALU
The arithmetic operations consist of addition and subtraction. Arithmetic operations can be performed on the
contents of the general register and data memory or on immediate data and the contents of data memory. Operations
in binary are performed on four bits of data and operations in BCD are performed on one place.
Logical operations include ANDing, ORing, and XORing. Their operands can be general register contents and
data memory contents, or data memory contents and immediate data.
Bit evaluation is used to determine whether bits in 4-bit data in data memory are 0 or 1.
Comparison evaluation is used to compare contents of data memory with immediate data. It is used to determine
whether one value is equal to or greater than the other, less than the other, or if both values are equal or not equal.
Rotation is used to shift 4-bit data in the general register one bit in the direction of its least significant bit (rotation
to the right).
17
µPD17107(A1)
Fig. 5-1 Configuration of the ALU Block
Data bus
Temporary
register A
Temporary
register B
Status
flip-flop
ALU
• Arithmetic operations
• Logical operations
• Bit evaluations
• Comparison
evaluations
• Rotations
Decimal conversion circuit
Address
7EH
Name
Bit
Flag
7FH
Program status word
(PSWORD)
b0
b3
b2
b1
b0
BCD
CMP
CY
Z
0
Status flip-flop
BCD
flag
flip-flop
CMP
flag
flip-flop
CY
flag
flip-flop
Z
flag
flip-flop
Function outline
Indicates when the result of an arithmetic
operation is 0.
Stores the borrow or carry from an arithmetic
operation.
Used to indicate whether to store the result
of an arithmetic operation.
Used to indicate whether to perform
BCD correction for arithmetic operations.
18
µPD17107(A1)
[MEMO]
19
µPD17107(A1)
Table 5-1 List of ALU Instructions (1/2)
ALU function
Arithmetic
operations
Addition
Instruction
Operation
ADD r, m
(r) ← (r) + (m)
Adds contents of general register and data memory. Result
is stored in general register.
ADD m, #n4
(m) ← (m) + n4
Adds immediate data to contents of data memory. Result is
stored in data memory.
ADDC r, m
(r) ← (r) + (m) + CY
Adds contents of general register, data memory and carry
flag. Result is stored in general register.
ADDC m, #n4 (m) ← (m) + n4 + CY
Subtracts contents of data memory from contents of general
register. Result is stored in general register.
SUB m, #n4
(m) ← (m) – n4
Subtracts immediate data from data memory. Result is
stored in data memory.
SUBC r, m
(r) ← (r) – (m) – CY
Subtracts contents of data memory and carry flag from
contents of general register. Result is stored in general
register.
SUBC m, #n4 (m) ← (m) – n4 – CY
Logical
OR
Logical
AND
Logical
XOR
Adds immediate data, contents of data memory and carry
flag. Result is stored in data memory.
(r) ← (r) – (m)
SubSUB r, m
traction
Logical
operations
Explanation
∨ (m)
OR r, m
(r) ← (r)
OR m, #n4
(m) ← (m)
AND r, m
(r) ← (r)
AND m, #n4
(m) ← (m)
XOR r, m
(r) ← (r)
XOR m, #n4
(m) ← (m)
∧
Subtracts immediate data and carry flag from data memory.
Result is stored in data memory.
OR operation is performed on contents of general register
and data memory. Result is stored in general register.
∨ n4
OR operation is performed on immediate data and contents
of data memory. Result is stored in data memory.
AND operation is performed on contents of general
register and data memory. Result is stored in general
register.
(m)
∧ n4
∨ (m)
AND operation is performed on immediate data and
contents of data memory. Result is stored in data memory.
XOR operation is performed on contents of general register
and data memory. Result is stored in general register.
∨ n4
∧ n = n,
XOR operation is performed on immediate data and
contents of data memory. Result is stored in data memory.
Bit
evaluation
True
SKT m, #n
CMP←0, if (m)
then skip
False
SKF m, #n
CMP←0, if (m)
then skip
Comparison
evaluation
Equal
SKE m, #n4
(m) – n4, skip if zero
Not
equal
SKNE m, #n4 (m) – n4, skip if not
zero
Skips next instruction if immediate data is not equal to
contents of data memory. Result is not stored.
≥
SKGE m, #n4 (m) – n4, skip if not
borrow
Skips next instruction if contents of data memory is greater
than or equal to immediate data. Result is not stored.
<
SKLT m, #n4 (m) – n4, skip if borrow
Skips next instruction if contents of data memory is less
than immediate data. Result is not stored.
Rotate
to the
right
RORC r
Rotation
20
∧ n = 0,
(CY)→(r)b3→(r)b2→(r)b1→(r)b0
Skips next instruction if all bits in data memory specified by
n are TRUE (1). Result is not stored.
Skips next instruction if all bits in data memory specified by
n are FALSE (0). Result is not stored.
Skips next instruction if immediate data equals contents of
data memory. Result is not stored.
Rotate contents of the general register along with the CY
flag to the right. Result is stored in general register.
µPD17107(A1)
Table 5-1 List of ALU Instructions (2/2)
ALU function
Operation depending on the program status word (PSWORD)
Arithmetic
operation
Value in
BCD flag
Value in
CMP flag
0
0
0
1
1
0
1
Operation
CY flag
Z flag
Set (1)
when
carry or
Do not store
borrow
result of binary
is generoperation
ated,
Store result of
otherwise
decimal operation
reset (0).
Set (1) when result of operation
is 0000B, otherwise reset (0).
1
Do not store
result of decimal
operation
Status maintained when result
of operation is 0000B, otherwise
reset (0).
Don’t care
(maintained)
Don’t care
(maintained)
No change
Don’t care
(maintained)
Don’t care
(maintained)
Don’t care
(maintained)
Reset
No change
Don’t care
(maintained)
Don’t care
(maintained)
Don’t care
(maintained)
Don’t care
(maintained)
No change
Don’t care
(maintained)
Don’t care
(maintained)
Don’t care
(maintained)
Don’t care
(maintained)
No change
Value in b0
of the general register
Don’t care
(maintained)
Store result of
binary operation
Status maintained when result
of operation is 0000B, otherwise
reset (0).
Set (1) when result of operation
is 0000B, otherwise reset (0).
Logical
operations
Bit evaluation
Comparison
evaluation
Rotation
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µPD17107(A1)
5.2.2 Functions of Temporary Registers A and B
Temporary registers A and B are needed for processing of 4-bit data. These registers are used for temporary
storage of the first and second data operands of an instruction.
5.2.3 Functions of the Status Flip-Flop
The status flip-flop is used for controlling operation of the ALU and for storing data which has been processed.
Each flag in the status flip-flop corresponds directly to a flag in the program status word (PSWORD) located in the
system register. This means that when a flag in the system register is manipulated it is the same as manipulating
a flag in the status flip-flop. Each flag in the program status word is described below.
(1) Z flag
This flag is set (1) when the result of an arithmetic operation is 0000B, otherwise it is reset (0). However, as
described below, depending on the status of the CMP flag, the conditions which cause this flag to be set (1) can
be changed.
(i)
When CMP = 0
Z flag is set (1) when the result of an arithmetic operation is 0000B, otherwise it is reset (0).
(ii) When CMP = 1
The previous state of the Z flag is maintained when the result of an arithmetic operation is 0000B, otherwise
it is reset (0). Only affected by arithmetic operations.
(2) CY flag
This flag is set (1) when a carry or borrow is generated in the result of an arithmetic operation, otherwise it is
reset (0).
When an arithmetic operation is being performed using a carry or borrow, the operation is performed using the
CY flag as the least significant bit. When a rotation (RORC instruction) is performed, the contents of the CY flag
becomes the most significant bit (bit b3) of the general register and the least significant bit of the general register
is stored in the CY flag.
Only affected by arithmetic operations and rotations.
(3) CMP flag
When the CMP flag is set (1), the result of an arithmetic operation is not stored in either the general register or
data memory.
When the bit evaluation instruction is performed, the CMP flag is reset (0).
The CMP flag does not affect comparison evaluations, logical operations, or rotations.
(4) BCD flag
When the BCD flag is set (1), all arithmetic operations are performed in BCD. When the flag is reset (0), all
operations are performed in 4-bit binary.
The BCD flag does not affect logical operations, bit evaluations, comparison evaluations, or rotations.
These flags can also be set through direct manipulation of the values in the program status word (PSWORD). When
the flags in the program status word are manipulated, the corresponding flag in the status flip-flop is also manipulated.
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µPD17107(A1)
5.2.4 Performing Operations in 4-Bit Binary
When the BCD flag is set to 0, arithmetic operations are performed in 4-bit binary.
5.2.5 Performing Operations in BCD
When the BCD flag is set to 1, arithmetic operations are performed in BCD. Table 5-2 shows the differences in
the results of operations performed in 4-bit binary and in BCD. When the result of an addition in BCD is equal to
or greater than 20, or the result of a subtraction in BCD is outside of the range -10 to +9, a value of 1010B (0AH)
or higher is stored as the result (shaded area in Table 5-2).
Table 5-2 Results of Arithmetic Operations Performed in 4-Bit Binary and BCD
Operation
result
Addition in
4-bit binary
Addition in
BCD
CY
Operation
result
CY
Operation
result
0
0
0000
0
0000
1
0
0001
0
2
0
0010
3
0
0011
4
0
5
Operation
result
Subtraction in
4-bit binary
Subtraction in
BCD
CY
Operation
result
CY
Operation
result
0
0
0000
0
0000
0001
1
0
0001
0
0001
0
0010
2
0
0010
0
0010
0
0011
3
0
0011
0
0011
0100
0
0100
4
0
0100
0
0100
0
0101
0
0101
5
0
0101
0
0101
6
0
0110
0
0110
6
0
0110
0
0110
7
0
0111
0
0111
7
0
0111
0
0111
8
0
1000
0
1000
8
0
1000
0
1000
9
0
1001
0
1001
9
0
1001
0
1001
10
0
1010
1
0000
10
0
1010
1
1100
11
0
1011
1
0001
11
0
1011
1
1101
12
0
1100
1
0010
12
0
1100
1
1110
13
0
1101
1
0011
13
0
1101
1
1111
14
0
1110
1
0100
14
0
1110
1
1100
15
0
1111
1
0101
15
0
1111
1
1101
16
1
0000
1
0110
–16
1
0000
1
1110
17
1
0001
1
0111
–15
1
0001
1
1111
18
1
0010
1
1000
–14
1
0010
1
1100
19
1
0011
1
1001
–13
1
0011
1
1101
20
1
0100
1
1110
–12
1
0100
1
1110
21
1
0101
1
1111
–11
1
0101
1
1111
22
1
0110
1
1100
–10
1
0110
1
0000
23
1
0111
1
1101
–9
1
0111
1
0001
24
1
1000
1
1110
–8
1
1000
1
0010
25
1
1001
1
1111
–7
1
1001
1
0011
26
1
1010
1
1100
–6
1
1010
1
0100
27
1
1011
1
1101
–5
1
1011
1
0101
28
1
1100
1
1010
–4
1
1100
1
0110
29
1
1101
1
1011
–3
1
1101
1
0111
30
1
1110
1
1100
–2
1
1110
1
1000
31
1
1111
1
1101
–1
1
1111
1
1001
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µPD17107(A1)
5.2.6 Performing Operations in the ALU Block
When arithmetic operations, logical operations, bit evaluations, comparison evaluations or rotations in a program
are executed, the first data operand is stored in temporary register A and the second data operand is stored in
temporary register B.
The first data operand is four bits of data used to specify the contents of an address in the general register or data
memory. The second data operand is four bits of data used to either specify the contents of an address in data memory
or to be used as an immediate value. For example, in the instruction
ADD r, m
Second data operand
First data operand
the first data operand, r, is used to specify the contents of an address in the general register. The second data operand,
m, is used to specify the contents of an address in data memory. In the instruction
ADD m, #n4
the first data operand, m, is used to specify an address in data memory. The second operand, #n4, is immediate
data. In the rotation instruction
RORC r
only the first data operand, r (used to specify the contents of an address in the general register) is used.
Next, using the data stored in temporary registers A and B, the ALU executes the operation specified by the
instruction (arithmetic operation, logical operation, bit evaluation, comparison evaluation, or rotation). When the
instruction being executed is an arithmetic operation, logical operation, or rotation, the data processed by the ALU
is stored in the location specified by the first data operand (general register address or data memory address) and
the operation terminates. When the instruction being executed is a bit evaluation or comparison evaluation, the result
processed by the ALU is used to determine whether or not to skip the next instruction (whether to treat next instruction
as a no operation instruction: NOP) and the operation terminates.
Caution should be taken with regard to the following points:
(1) Arithmetic operations are affected by the CMP and BCD flags in the program status word.
(2) Logical operations are not affected by the CMP or BCD flag in the program status word. Logical operations do
not affect the Z or CY flags.
(3) Bit evaluation causes the CMP flag in the program status word to be reset.
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µPD17107(A1)
5.3 ARITHMETIC OPERATIONS (ADDITION AND SUBTRACTION IN 4-BIT BINARY AND BCD)
As shown in Table 5-3, arithmetic operations consist of addition, subtraction, addition with carry, and subtraction
with borrow. These instructions are ADD, ADDC, SUB, and SUBC.
The ADD, ADDC, SUB, and SUBC instructions are further divided into addition and subtraction of the general
register and data memory and addition and subtraction of data memory and immediate data. When the operands
r and m are used, addition or subtraction is performed using the general register and data memory. When the operands
m and #n4 are used, addition or subtraction is performed using data memory and immediate data.
Arithmetic operations are affected by the status flip-flop and the program status word (PSWORD) in the system
register. The BCD flag in the program status word (PSWORD) is used to specify whether arithmetic operations are
to be performed in 4-bit binary or in BCD. The CMP flag is used to specify whether or not the results of arithmetic
operations are to be stored.
Sections 5.3.1 to 5.3.4 explain the relationship between each command and the program status word (PSWORD).
Table 5-3 Types of Arithmetic Operations
Arithmetic
operation
Addition
Without carry ADD
With carry ADDC
Subtraction
Without borrow SUB
With borrow SUBC
General register and data memory
ADD r, m
Data memory and immediate data
ADD m, #n4
General register and data memory
ADDC r, m
Data memory and immediate data
ADDC m, #n4
General register and data memory
SUB r, m
Data memory and immediate data
SUB m, #n4
General register and data memory
SUBC r, m
Data memory and immediate data
SUBC m, #n4
5.3.1 Addition and Subtraction When BCD = 0 and CMP = 0
Addition and subtraction are performed in 4-bit binary and the result is stored in the general register (or data
memory).
When the result of the operation is greater than 1111B (carry generated) or less than 0000B (borrow generated),
the CY flag is set (1); otherwise it is reset (0).
When the result of the operation is 0000B, the Z flag is set (1) regardless of whether there is carry or borrow;
otherwise it is reset (0).
5.3.2 Addition and Subtraction When BCD = 0 and CMP = 1
Addition and subtraction are performed in 4-bit binary.
However, because the CMP flag is set (1), the result of the operation is not stored in either the general register
(or data memory).
When there is a carry or borrow in the result of the operation, the CY flag is set (1); otherwise it is reset (0).
When the result of the operation is 0000B, the previous state of the Z flag is maintained; otherwise it is reset (0).
25
µPD17107(A1)
5.3.3 Addition and Subtraction When BCD = 1 and CMP = 0
BCD operations are performed.
The result of the operation is stored in the general register (or data memory). When the result of the operation
is greater than 1001B (9D) or less than 0000B (0D), the carry flag is set (1), otherwise it is reset (0).
When the result of the operation is 0000B (0D), the Z flag is set (1), otherwise it is reset (0).
Operations in BCD are performed by first computing the result in binary and then by using the decimal conversion
circuit to convert the result to decimal. For information concerning the binary to decimal conversion, see Table 52 in Section 5.2.5.
In order for operations in BCD to be performed properly, note the following:
(1) Result of an addition must be in the range 0D to 19D.
(2) Result of a subtraction must be in the range 0D to 9D, or in the range -10D to -1D.
The following shows which value is considered the CY flag in the range 0D to 19D (shown in hexadecimal):
0, 0000B to 1, 0011B
CY
CY
The following shows which value is considered the CY flag in the range -10D to -1D (shown in hexadecimal):
1, 0110B to 1, 1111B
CY
CY
When operations in BCD are performed outside of the limits of (1) and (2) stated above, the CY flag is set (1) and
the result of operation is output as a value greater than or equal to 1010B (0AH).
5.3.4 Addition and Subtraction When BCD = 1 and CMP = 1
BCD operations are performed.
The result is not stored in either the general register (or data memory).
Example SET2
BCD, CMP
;
Sets the BCD flag and CMD flag (1).
ADD
PEGX, MEMX
;
Adds the register REGX and data memory MEMX.
CLR1
BCD
;
Clears the BCD flag (0).
SKT1
CY
;
Checks the CY flag and clears the CMP flag (0).
BR
UNDER10
;
REGX + MEMX < 10
BR
OVER10
;
REGX + MEMX ≥ 10
In this example, the ALU checks whether the sum of the register REGX and data memory MEMX
is greater than or equal to 10, without corrupting the contents of REGX and MEMX.
26
µPD17107(A1)
5.3.5 Warnings Concerning Use of Arithmetic Operations
When performing arithmetic operations with the PSW (address 7FH), note the followings:
When the CMP flag is cleared (0) and an arithmetic operation is performed on the PSW, the result is stored in
the PSW. This means that there is no way to check the CY and Z flags in the PSW.
However, when the CMP flag is set (1), results of arithmetic operations are not stored. Therefore, even in the above
case, the CY and Z flags can be checked.
5.4 LOGICAL OPERATIONS
As shown in Table 5-4, logical operations consist of logical OR, logical AND, and logical XOR. Accordingly, the
logical operation instructions are OR, AND, and XOR.
The OR, AND, and XOR instructions can be performed on either the general register and data memory, or on data
memory and immediate data. The operands of these instructions are specified in the same way as for arithmetic
operations ("r, m" or "m, #n4").
Logical operations are not affected by the BCD or CMP flags in the program status word (PSWORD). The
operations do not affect the CY and Z flags at all.
Table 5-4 Logical Operations
Logical
operation
Logical OR
Logical AND
Logical XOR
General register and data memory
OR r, m
Data memory and immediate data
OR m, #n4
General register and data memory
AND r, m
Data memory and immediate data
AND m, #n4
General register and data memory
XOR r, m
Data memory and immediate data
XOR m, #n4
Table 5-5 Table of True Values for Logical Operations
Logical AND
Logical OR
Logical XOR
C = A AND B
C = A OR B
C = A XOR B
A
B
0
0
0
1
1
0
1
1
C
0
0
0
1
A
0
0
1
1
B
0
1
0
1
C
A
B
C
0
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
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µPD17107(A1)
5.5 BIT EVALUATIONS
As shown in Table 5-6, there are both TRUE (1) and FALSE (0) bit evaluation instructions.
The SKT instruction skips the next instruction when a bit is evaluated as TRUE (1) and the SKF instruction skips
the next instruction when a bit is evaluated as FALSE (0).
The SKT and SKF instructions can only be used with data memory.
Bit evaluations are not affected by the BCD flag in the program status word (PSWORD). The evaluations do not
affect the CY and Z flags at all. However, when an SKT or SKF instruction is executed, the CMP flag is reset (0).
Sections 5.5.1 and 5.5.2 explain TRUE (1) and FALSE (0) bit evaluations.
Table 5-6 Bit Evaluation Instructions
Bit evaluation
TRUE (1) bit evaluation
SKT m, #n
FALSE (0) bit evaluation
SKF m, #n
5.5.1 TRUE (1) Bit Evaluation
The TRUE (1) bit evaluation instruction (SKT m, #n) is used to determine whether or not the bits specified by n
in the four bits of data memory m are TRUE (1). When all bits specified by n are TRUE (1), this instruction causes
the next instruction to be skipped.
Example MOV M1, #1011B
SKT
M1, #1011B ; 1
BR
A
BR
B
SKT
·
·
·
M1, #1101B ; 2
BR
C
BR
D
In this example, bits b3, b1, and b0 of data memory M1 are evaluated in step number
1 . Because
all the bits are TRUE (1), the program branches to B. In step number 2 , bits b3, b2, and b0 of data
memory M1 are evaluated. Since b2 of data memory M1 is FALSE (0), the program branches to C.
28
µPD17107(A1)
5.5.2 FALSE (0) Bit Evaluation
The FALSE (0) bit evaluation instruction (SKF m, #n) is used to determine whether or not the bits specified by n
in the four bits of data memory m are FALSE (0). When all bits specified by n are FALSE (0), this instruction causes
the next instruction to be skipped.
Example MOV M1, #1001B
SKF
M1, #0110B ; 1
BR
A
BR
B
SKF
·
·
·
M1, #1110B ; 2
BR
C
BR
D
In this example, bits b2 and b1 of data memory M1 are evaluated in step number 1 . Because both
bits are FALSE (0), the program branches to B. In step number 2 , bits b3, b2, and b1 of data memory
M1 are evaluated. Since b3 of data memory M1 is TRUE (1), the program branches to C.
5.6 COMPARISON EVALUATIONS
As shown in Table 5-7, there are comparison evaluation instructions for determining if one value is "equal to," "not
equal to," "greater than or equal to," or "less than" another.
The SKE instruction is used to determine if two values are equal. The SKNE instruction is used to determine two
values are not equal. The SKGE instruction is used to determine if one value is greater than or equal to another and
the SKLT instruction is used to determine if one value is less than another.
The SKE, SKNE, SKGE, and SKLT instructions perform comparisons between a value in data memory and
immediate data. In order to compare values in the general register and data memory, a subtraction instruction is
performed according to the values in the CMP and Z flags in the program status word (PSWORD). For more
information concerning comparison of the general register and data memory, see Section 5.3.
Comparison evaluations are not affected by the BCD or CMP flags in the program status word (PSWORD). The
evaluations do not affect the CY and Z flags at all.
Sections 5.6.1 to 5.6.4 explain the "equal," "not equal," "greater than or equal," and "less than" comparison
evaluations.
Table 5-7 Comparison Evaluation Instructions
Comparison
evaluation
Equal
SKE m, #n4
Not equal
SKNE m, #n4
Greater than or equal
SKGE m, #n4
Less than
SKLT m, #n4
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µPD17107(A1)
5.6.1 "Equal" Evaluation
The "equal" evaluation instruction (SKE m, #n4) is used to determine if immediate data and the contents of a location
in data memory are equal.
This instruction causes the next instruction to be skipped when the immediate data and the contents of data memory
are equal.
Example MOV M1, #1010B
SKE
M1, #1010B ; 1
BR
A
BR
B
SKE
·
·
·
M1, #1000B ; 2
BR
C
BR
D
In this example, because the contents of data memory M1 and immediate data 1010B in step number
1 are equal, the program branches to B. In step number
2 , because the contents of data memory
M1 and immediate data 1000B are not equal, the program branches to C.
5.6.2 "Not Equal" Evaluation
The "not equal" evaluation instruction (SKNE m, #n4) is used to determine if immediate data and the contents of
a location in data memory are not equal.
This instruction causes the next instruction to be skipped when the immediate data and the contents of data memory
are not equal.
Example MOV
M1, #1010B
SKNE M1, #1000B
BR
A
BR
B
; 1
·
·
·
SKNE M1, #1010B
BR
C
BR
D
; 2
In this example, because the contents of data memory M1 and immediate data 1000B in step number
1
are not equal, the program branches to B. In step number 2 , because the contents of data memory
M1 and immediate data 1010B are equal, the program branches to C.
30
µPD17107(A1)
5.6.3 "Greater Than or Equal" Evaluation
The "greater than or equal" evaluation instruction (SKGE m, #n4) is used to determine if the contents of a location
in data memory is a value greater than or equal to the value of the immediate data operand. If the value in data memory
is greater than or equal to that of the immediate data, this instruction causes the next instruction to be skipped.
Example MOV
M1, #1000B
SKGE M1, #0111B ; 1
BR
A
BR
B
·
·
·
SKGE M1, #1000B ; 2
BR
C
BR
D
·
·
·
SKGE M1, #1001B ; 3
BR
E
BR
F
In this example, the program will first branch to B since the value in data memory is larger than that
of the immediate data ( 1 ). Next it will branch to D since the value in data memory is equal to that
of the immediate data ( 2 ). Last it will branch to E since the value in data memory is less than that
of the immediate data ( 3 ).
5.6.4 "Less Than" Evaluation
The "less than" evaluation instruction (SKLT m, #n4) is used to determine if the contents of a location in data memory
is a value less than that of the immediate data operand. If the value in data memory is less than that of the immediate
data, this instruction causes the next instruction to be skipped.
Example MOV
M1, #1000B
SKLT M1, #1001B ; 1
BR
A
BR
B
·
·
·
SKLT M1, #1000B ; 2
BR
C
BR
D
·
·
·
SKLT M1, #0111B ; 3
BR
E
BR
F
In this example, the program will first branch to B since the value in data memory is less than that of
the immediate data ( 1 ). Next it will branch to C since the value in data memory is equal to that of
the immediate data ( 2 ). Last it will branch to E since the value in data memory is greater than that
of the immediate data ( 3 ).
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µPD17107(A1)
5.7 ROTATIONS
There are rotation instructions for rotation to the right and for rotation to the left.
The RORC instruction is used for rotation to the right.
The RORC instruction can only be used with the general register.
Rotation using the RORC instruction is not affected by the BCD or CMP flags in the program status word
(PSWORD). The rotation does not affect the Z flag at all.
Rotation to the left is performed by using the addition instruction ADDC.
Sections 5.7.1 and 5.7.2 explain rotation.
5.7.1 Rotation to the Right
The instruction used for rotation to the right (RORC r) rotates the contents of the general register in the direction
of its least significant bit.
When this instruction is executed, the contents of the CY flag becomes the most significant bit of the general register
(bit b3) and the least significant bit of the general register (bit b0) is placed in the CY flag.
Examples 1. MOV
MOV
PSW, #0100B ; Sets CY flag to 1.
R1, #1100B
RORC R1
When these instructions are executed, the following operation is performed.
CY flag
b3
b2
b1
b0
1
1
1
0
0
Basically, when rotation to the right is performed, the following operation is executed:
CY flag → b3, b3 → b2, b2 → b1, b1 → b0, b0 → CY flag.
2. MOV
PSW, #0000B ; Resets CY flag to 0.
MOV
R1, #1000B
MOV
R2, #0100B
MOV
R3, #0010B
; Most significant bit
; Least significant bit
RORC R1
RORC R2
RORC R3
The program code above rotates 13 bits in CY, R1, R2, and R3 to the right.
32
µPD17107(A1)
5.7.2 Rotation to the Left
Rotation to the left is performed by using the addition instruction, "ADDC r, m".
Example MOV
PSW, #0000B
; Resets CY flag to 0.
MOV
R1, #1000B
; Most significant bit
MOV
R2, #0100B
MOV
R3, #0010B
; Least significant bit
ADDC R3, R3
ADDC R2, R2
ADDC R1, R1
SKF1
CY
OR
R3, #0001B
The program code above rotates 13 bits in CY, R1, R2, and R3 to the left.
33
µPD17107(A1)
6. PORTS
6.1
PORT 0B (P0B0/RLSHALT, P0B1/RLSSTOP, P0B2)
Port 0B is a three-bit input/output port. Only N-ch open-drain outputs appear on the pins of port 0B. The N-ch
open-drain output mode allows application of 9 V, so it can be used for interfacing with a circuit operating on a different
power supply voltage.
Input and output are set in units of nibbles. The input mode is set at reset, and the output mode is set by writing
data to the port register in address 71H of the data memory. The output mode is maintained until the system is reset.
Output to the port is executed via the port register. Once data is written to the port register, all pins of port 0B
are placed in the output mode to continue to output written data. The data is retained unless new data is written to
the register.
Writing 1 to the port register makes the N-ch open-drain output pin high-impedance. Therefore, the pin which
outputs 1 can be used as an input pin.
Whenever the port register is read, the read data indicates the states of the pinsNote, not the contents of the port
register, regardless of whether the pins are in the input or output mode. In this case, the contents of the port register
remain unchanged.
The port register for port 0B consists of four bits but its highest bit is always set to 0. This means that if an attempt
is made to write data to the highest bit of 71H, the data is invalidated and if an attempt is made to read it, 0 is always
returned.
A P0B0 input signal releases the HALT mode as a pseudo interrupt. A P0B1 input signal releases the STOP mode
as a pseudo interrupt. (See Chapter 7.)
6.2
PORT 0C (P0C0 TO P0C3)
Port 0C is a four-bit input/output port. CMOS (push-pull) outputs appear on those pins.
Input and output are set in units of nibbles. The input mode is set at reset, and the output mode is set by writing
data to the port register in address 72H of the data memory. The output mode is maintained until the system is reset.
Output to the port is executed via the port register. Once data is written to the port register, all pins of the port
0C are placed in the output mode to continue to output written data. The data is retained unless new data is written
to the register.
Whenever the port register is read, the read data indicates the states of the pinsNote, not the contents of the port
register, regardless of whether the pins are in the input or output mode. In this case, the contents of the port register
remain unchanged.
6.3
PORT 0D (P0D0 TO P0D3)
Port 0D is a four-bit input/output port. CMOS (push-pull) outputs appear on these pins.
Input and output are set in units of nibbles. The input mode is set at reset, and the output mode is set by writing
data to the port register in address 73H of the data memory. The output mode is maintained until the system is reset.
Output to the port is executed via the port register. Once data is written to the port register, all pins of the port
0D are placed in the output mode to continue to output written data. The data is retained until new data is written
to the register.
Whenever the port register is read, the read data indicates the states of the pinsNote, not the contents of the port
register, regardless of whether the pins are in the input or output mode. In this case, the contents of the port register
remain unchanged.
Note In the output mode, design an external circuit appropriately depending on the output data.
34
µPD17107(A1)
Fig. 6-1 Port Register Map
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0X
Row
address
Port register
7X
70H
Address
0
0
0
71H
0
0
Bit
symbol
P
0
B
2
P
0
B
1
System register
72H
P
0
B
0
P
0
C
3
P
0
C
2
P
0
C
1
73H
P P
0 0
C D
0 3
P
0
D
2
P P
0 0
D D
1 0
Always set to 0
35
µPD17107(A1)
6.4 NOTES ON MANIPULATING PORT REGISTERS
The states of the I/O port pins of the µPD17107(A1) can be read even when the port pins have been set to output
mode.
When a port register is manipulated with a built-in macro instruction (such as SETn or CLRn) or AND, OR, or XOR
instruction, the states of those pins for which the state should remain unchanged may change unexpectedly.
Especially when using some of the port 0B pins (N-ch open-drain outputs) as input pins, with the remaining port
0B pins being used as output pins, always take the possibility of this change in the states of the pins into consideration.
When a CLR1 P0B2 instruction (identical to an AND 71H, #1011B instruction) is applied to the port 0B pins, the
corresponding port register and internal states are changed, as shown in Fig. 6-2.
Assume that the states of port 0B are those shown in Fig. 6-2 1 . Pins P0B3 and P0B2, used as output pins, output
high level, while pins P0B1 and P0B0, used as input pins, receive low level.
It is required that high level be output, inside the chip, from the port 0B pins to be used as input pins. Although
the µPD17103, µPD17103L, µPD17107, and µPD17107L do not support pin P0B3, it is virtually assumed to exist
within a program.
When a CLR1 P0B2 instruction is executed to set pin P0B2 to low, the states of the port 0B pins change as shown
in Fig. 6-2 2 . The port register changes such that pins P0B1 and P0B0, required to output high level, actually output
low level. This is because the CLR1 P0B2 instruction has been applied to the states of the port 0B pins, but not to
the states of the port register.
To prevent this problem, use another instruction, such as a MOV instruction, to specify the states of all port 0B
pins, not merely the states of those pins whose states are to be changed. In this example, it is recommended that
a MOV 71H, #1011B instruction be used to set only pin P0B2 to low.
Fig. 6-2 Changes in the Port Register According to the Execution of a CLR1 P0B2 Instruction
1
Before the instruction is executed
State
Port register
Internal
Pin
P0B3
P0B2
P0B1
P0B0
1
1
1
1
H output
H output
H output
H output
H
H
L (input)
L (input)
Executing a CLR1 P0B2
instruction [AND 71H, #1011B]
2
After the instruction is executed
State
Port register
Internal
Pin
P0B3
P0B2
P0B1
P0B0
1
0
0
0
H output
L output
L output
L output
H
L
L
L
H: High level, L: Low level
36
µPD17107(A1)
7.
STANDBY FUNCTIONS
The µPD17107(A1) provides two standby modes, the HALT mode and the STOP mode.
7.1
HALT MODE
The HALT mode stops the program counter (PC) while allowing the system clock to continue operating. The HALT
mode can be entered with the HALT instruction, and can be released by a reset signal (RESET) or high-level input
to the P0B0 pin. When the HALT mode is released by a high-level signal input to the P0B0 pin, the system does not
wait for the system clock oscillation to settle. The instruction immediately after the HALT instruction is executed.
When the HALT mode is released forcibly by the reset signal (RESET), normal reset occurs, and the program starts
at address 0H.
7.2
STOP MODE
The STOP mode stops the system clock oscillation so that data can be retained at low power voltage. The STOP
mode can be entered with the STOP instruction, and can be released by a reset signal (RESET) or high-level input
to the P0B1 pin. When the mode is released by a high-level signal input to the P0B1 pin, the program starts with the
instruction immediately after the STOP instruction.
When the STOP mode is released forcibly by the reset signal (RESET), normal reset occurs, and the program
starts at address 0H.
7.3
SETTING AND RELEASING THE STANDBY MODES
(1) Setting and releasing the HALT mode
Conditions for releasing the HALT mode are selected with the least significant bit of the operand in the HALT
instruction as shown in Table 7-1. The high-order three bits of the operand must be set to 0.
Table 7-1 Conditions for Setting/Releasing the HALT Mode
HALT 000XB ← 4-bit data in the operand
X
Conditions for setting/releasing the HALT mode
0
After executing a HALT instruction, the system enters the HALT mode unconditionally.
The mode can be released only by the reset signal (RESET). After the mode is released, the program starts at
address 0H.
1
When a HALT instruction is executed with the P0B0 pin being at low level, the system enters the HALT mode. The
mode can be released by the reset signal (RESET). When the mode is released, the program starts at address 0H.
This mode can also be released when a high-level signal is applied to the P0B0 pin. In this case, the program starts
with the instruction immediately after the HALT instruction.
When a HALT instruction is executed with the P0B0 pin being at high level, the instruction is ignored (regarded as a
NOP instruction) and the system does not enter the HALT mode.
(2) Setting and releasing the STOP mode
Conditions to release the STOP mode are selected with the least significant bit of the operand in the STOP
instruction as shown in Table 7-2. The high-order three bits of the operand must be set to 0.
37
µPD17107(A1)
Table 7-2 Conditions for Setting/Releasing the STOP Mode
STOP 000XB ← 4-bit data in the operand
Conditions for setting/releasing the STOP mode
X
0
After executing a STOP instruction, the system enters the STOP mode unconditionally.
All peripheral circuits are placed in the same initial state as when the system is reset, then they stop operating.
The mode can be released only by the reset signal (RESET). After the mode is released, the program starts at
address 0H.
1
When a STOP instruction is executed with the P0B1 pin being at low level, the system enters the STOP mode. The
mode can be released by the reset signal (RESET). When the mode is released, the program starts at address 0H.
This mode can also be released when a high-level signal is applied to the P0B1 pin. In this case, the program starts
with the instruction immediately after the STOP instruction.
When a STOP instruction is executed with the P0B1 pin being at high level, the instruction is ignored (regarded as a
NOP instruction) and the system does not enter the STOP mode.
7.4 HARDWARE STATUSES IN STANDBY MODE
Hardware statuses in standby mode are as follows:
Table 7-3 Hardware Statuses in Standby Mode
Hardware
STOP 0000B instruction
HALT or STOP 0001B instruction
Clock generator
HALT instruction: Oscillation continued
STOP instruction: Oscillation disabled
Oscillation disabled
Program counter
Address following a HALT or STOP instruction
is indicated.
000H
Data memory (00H to 0FH)
Previous data is retained.
Previous data is retained.
Program status word (PSWORD)
Previous data is retained.
All bits are set to 0.
Port register (71H to 73H)
Previous data is retained.
(Input/output mode of pins is also retained.)
Previous data is retained.
(All pins are placed in input mode.)
7.5 TIMING FOR RELEASING THE STANDBY MODES
Fig. 7-1 Releasing the HALT Mode by RESET Input
HALT
instruction
RESET
Operation mode
Clock
HALT mode
Note
Operation mode
Oscillation
When the RESET signal is applied to release the HALT mode, the RESET input makes a transition from low to
high, then an operation mode is entered.
Note The HALT mode remains effective in this period, waiting for the operation mode.
An operation starts after eight clock pulses on the OSC0 pin are counted.
38
µPD17107(A1)
Fig. 7-2 Releasing the HALT Mode by High-Level Input to the P0B0 Pin
HALT
instruction
Standby release
signal (P0B0)
Operation mode
HALT mode
Operation mode
Oscillation
Clock
Fig. 7-3 Releasing the STOP Mode by RESET Input
STOP
instruction
RESET
Operation mode
STOP mode
Oscillation
Oscillation
stopped
Clock
HALT mode
Operation mode
Note
Oscillation
As soon as the RESET input makes a transition from high to low in the STOP mode, the system clock starts
generating clock pulses.
Note The HALT mode remains effective in this period, waiting for the generation of clock pulses to settle.
An operation starts after eight clock pulses on the OSC0 pin are counted.
Fig. 7-4 Releasing the STOP Mode by High-Level Input to the P0B1 Pin
STOP
instruction
Standby release
signal (P0B1)
Clock
Operation mode
STOP
instruction
Oscillation
Oscillation
stopped
Note
Operation mode
Oscillation
Note The HALT mode remains effective in this period, waiting for the generation of clock pulses to settle.
An operation starts after eight clock pulses on the OSC0 pin are counted.
39
µPD17107(A1)
8. RESET FUNCTION
8.1 RESET FUNCTION
A low-level signal, applied to the RESET pin, resets the system, then the hardware is initialized.
The system clock oscillates as long as the power supply voltage is supplied, even if a low-level signal is applied
to the RESET pin.
A low to high transition on the RESET pin releases the reset status and causes the system to enter the operating
mode once the 8-clock oscillation settling wait time has elapsed.
Table 8-1 Hardware Status after Reset
Hardware
• Reset immediately after power on
• Reset during operation
Reset in standby modeNote
Program counter
000H
000H
Data memory (00H to 0FH)
Undefined
Data existing before reset is retained.
Program status word (PSWORD)
All bits are set to 0.
All bits are set to 0.
Port
Input/output mode
Input
Input
Output latch
Undefined
Data existing before reset is retained.
Note The hardware is initialized when the STOP 0000B instruction is executed.
40
µPD17107(A1)
9. RESERVED WORDS USED IN ASSEMBLY LANGUAGE
9.1
MASK-OPTION PSEUDO INSTRUCTIONS
Source programs in the assembly language for the µPD17107(A1) must include mask-option pseudo instructions
to select pin options.
To do this, be sure to catalog the D17107.OPT file in AS17103 (device file for the µPD17107(A1)) into the current
directory beforehand.
Specify mask options for the following pins:
• P0B0
• P0B1
• P0B2
• RESET
9.1.1
OPTION and ENDOP Pseudo Instructions
The part starting with the OPTION pseudo instruction and ending with the ENDOP pseudo instruction is referred
to as a mask-option definition block. The coding format of the mask-option definition block is as follows.
Only the two pseudo instructions listed in Table 9-1 can be coded in the block.
Format:
Symbol
Mnemonic
[label:]
OPTION
Operand
Comment
[;comment]
•
•
•
ENDOP
9.1.2 Mask-Option Definition Pseudo Instructions
Table 9-1 lists the pseudo instructions to define a mask option for each pin.
Table 9-1 Mask-Option Definition Pseudo Instructions
Pin
Mask-option pseudo
instruction
Number of
operands
Operand
P0B2 P0B0
OPTP0B
3
P0BPLUP (pull-up resistor provided)
OPEN (no pull-up resistor provided)
RESET
OPTRES
1
RESPLUP (pull-up resistor provided)
OPEN (no pull-up resistor provided)
The coding format of OPTP0B is as follows. To define the mask option, specify P0B2 (first operand), P0B1, and
P0B0 in the operand field.
Format:
Symbol
Mnemonic
Operand
Comment
[label:]
OPTP0B
(P0B2),(P0B1),(P0B0)
[;comment]
41
µPD17107(A1)
The coding format of OPTRES is as follows.
Format:
Example
Symbol
Mnemonic
Operand
Comment
[label:]
OPTRES
(RESET)
[;comment]
The following mask options are set in a µPD17107(A1) source file to be assembled:
P0B2: Pull-up, P0B1: Open, P0B0: Open
RESET: Pull-up
•
•
•
;17107(A1)
Setting mask options:
OPTION
OPTP0B
P0BPLUP, OPEN, OPEN
OPTRES
RESPLUP
ENDOP
•
•
•
42
µPD17107(A1)
9.2
RESERVED SYMBOLS
Table 9-2 lists the reserved symbols defined in the µPD17107(A1) device file (AS17103).
Table 9-2 Reserved Symbols
Name
Attribute
Value
R/W
Description
P0B0
FLG
0.71H.0
R/W
Bit 0 of port 0B
P0B1
FLG
0.71H.1
R/W
Bit 1 of port 0B
P0B2
FLG
0.71H.2
R/W
Bit 2 of port 0B
P0B3Note
FLG
0.71H.3
R
Always set to 0
P0C0
FLG
0.72H.0
R/W
Bit 0 of port 0C
P0C1
FLG
0.72H.1
R/W
Bit 1 of port 0C
P0C2
FLG
0.72H.2
R/W
Bit 2 of port 0C
P0C3
FLG
0.72H.3
R/W
Bit 3 of port 0C
P0D0
FLG
0.73H.0
R/W
Bit 0 of port 0D
P0D1
FLG
0.73H.1
R/W
Bit 1 of port 0D
P0D2
FLG
0.73H.2
R/W
Bit 2 of port 0D
P0D3
FLG
0.73H.3
R/W
Bit 3 of port 0D
BCD
FLG
0.7EH.0
R/W
BCD arithmetic flag
PSW
MEM
0.7FH
R/W
Program status word
Z
FLG
0.7FH.1
R/W
Zero flag
CY
FLG
0.7FH.2
R/W
Carry flag
CMP
FLG
0.7FH.3
R/W
Compare flag
R/W: Read/write
Note Although a pin corresponding to P0B3 does not exist in the µPD17107(A1), P0B3 is defined as a read-only
flag so that it is used in a built-in macro.
43
µPD17107(A1)
10. INSTRUCTION SET
10.1
INSTRUCTION SET LIST
b15
b14-b11
1
0
BIN
HEX
0000
0
ADD
r, m
ADD
m, #n4
0001
1
SUB
r, m
SUB
m, #n4
0010
2
ADDC
r, m
ADDC
m, #n4
0011
3
SUBC
r, m
SUBC
m, #n4
0100
4
AND
r, m
AND
m, #n4
0101
5
XOR
r, m
XOR
m, #n4
0110
6
OR
r, m
OR
m, #n4
RET
RETSK
0111
7
RORC
r
STOP
s
HALT
h
NOP
44
1000
8
LD
r, m
ST
m, r
1001
9
SKE
m, #n4
SKGE
m, #n4
1010
A
1011
B
SKNE
m, #n4
SKLT
m, #n4
1100
C
BR
addr
CALL
addr
1101
D
MOV
m, #n4
1110
E
SKT
m, #n
1111
F
SKF
m, #n
µPD17107(A1)
10.2
INSTRUCTIONS
Legend
ASR : Address stack register pointed to by the stack pointer
addr : Program memory address (11 bits, high-order two bits are always set to 0)
CMP: Compare flag
CY : Carry flag
h
: Halt release condition
m
: Data memory address specified by mR or mC
mR : Data memory row address (high order)
mC : Data memory column address (low order)
n
: Bit position (4 bits)
n4
: Immediate data (4 bits)
PC : Program counter
r
: General register column address
SP : Stack pointer
s
: Stop release condition
(×)
: Contents addressed by ×
45
µPD17107(A1)
Instruction
set
Add
Mnemonic
ADD
ADDC
Subtract
SUB
SUBC
Operation
Operand
Machine code
Op code
Operand
r,m
(r) ← (r) + (m)
00000
mR
mC
r
m,#n4
(m) ← (m) + n4
10000
mR
mC
n4
r,m
(r) ← (r) + (m) + CY
00010
mR
mC
r
m,#n4
(m) ← (m) + n4 + CY
10010
mR
mC
n4
r,m
(r) ← (r) – (m)
00001
mR
mC
r
m,#n4
(m) ← (m) – n4
10001
mR
mC
n4
r,m
(r) ← (r) – (m) – CY
00011
mR
mC
r
m,#n4
(m) ← (m) – n4 – CY
10011
mR
mC
n4
00110
mR
mC
r
10110
mR
mC
n4
00100
mR
mC
r
10100
mR
mC
n4
00101
mR
mC
r
10101
mR
mC
n4
n = n, then skip
11110
mR
mC
n
n = 0, then skip
11111
mR
mC
n
m,#n4
∨ (m)
(m) ← (m) ∨ n4
(r) ← (r) ∧ (m)
(m) ← (m) ∧ n4
(r) ← (r) ∨ (m)
(m) ← (m) ∨ n4
SKT
m,#n
CMP ← 0, if (m)
SKF
m,#n
∧
CMP ← 0, if (m) ∧
SKE
m,#n4
(m) – n4, skip if zero
01001
mR
mC
n4
SKNE
m,#n4
(m) – n4, skip if not zero
01011
mR
mC
n4
SKGE
m,#n4
(m) – n4, skip if not borrow
11001
mR
mC
n4
SKLT
m,#n4
(m) – n4, skip if borrow
11011
mR
mC
n4
Rotation
RORC
r
00111
000
0111
r
Transfer
LD
r,m
(r) ← (m)
01000
mR
mC
r
ST
m,r
(m) ← (r)
11000
mR
mC
r
MOV
m,#n4
(m) ← n4
11101
mR
mC
n4
BR
addr
PC ← addr
01100
CALL
addr
Logical
operation
OR
r,m
m,#n4
AND
r,m
m,#n4
XOR
Test
Compare
Branch
Subroutine
Others
CY → (r)b3 → (r)b2 → (r)b1 → (r)b0
addr
SP ← SP – 1, ASR ← PC, PC ← addr
11100
RET
PC ← ASR, SP ← SP + 1
00111
000
1110
0000
RETSK
PC ← ASR, SP ← SP + 1 and skip
00111
001
1110
0000
addr
STOP
s
STOP
00111
010
1111
s
HALT
h
HALT
00111
011
1111
h
No operation
00111
100
1111
0000
NOP
46
r,m
(r) ← (r)
µPD17107(A1)
10.3 ASSEMBLER (AS17K) BUILT-IN MACRO INSTRUCTIONS
Legend
flag n : FLG symbol
<>
: Characters enclosed in < > can be omitted.
Built-in macro
Mnemonic
Operation
Operand
n
SKTn
flag 1, ...flag n
if (flag 1) – (flag n) = all "1", then skip
1≤n≤4
SKFn
flag 1, ...flag n
if (flag 1) – (flag n) = all "0", then skip
1≤n≤4
SETn
flag 1, ...flag n
(flag 1) – (flag n) ← 1
1≤n≤4
CLRn
flag 1, ...flag n
(flag 1) – (flag n) ← 0
1≤n≤4
NOTn
flag 1, ...flag n
if (flag n) = "0", then (flag n) ← 1
if (flag n) = "1", then (flag n) ← 0
1≤n≤4
INITFLG
<NOT> flag 1,
... <<NOT> flag n>
if description = NOT flag n, then (flag n) ← 0
if description = flag n, then (flag n) ← 1
1≤n≤4
47
µPD17107(A1)
11. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
Parameter
Conditions
Rated value
Unit
–0.3 to +7.0
V
P0C, P0D, RESET
–0.3 to VDD + 0.3
V
P0B When a built-in pull-up resistor is connected
–0.3 to VDD + 0.3
V
–0.3 to +11
V
P0C, P0D
–0.3 to VDD + 0.3
V
P0B When a built-in pull-up resistor is connected
–0.3 to VDD + 0.3
V
–0.3 to +11
V
Each of P0C and P0D
–5
mA
Total of all pins
–15
mA
Each of P0B, P0C, and P0D
30
mA
Total of all pins
100
mA
Symbol
VDD
Supply voltage
VI
Input voltage
When a built-in pull-up resistor is not connected
VO
Output voltage
When a built-in pull-up resistor is not connected
High-level output current
IOH
Low-level output current
IOL
Operating ambient temperature
TA
–40 to +110
°C
Storage temperature
Tstg
–65 to +150
°C
Allowable dissipation
Pd
100
mW
TA = 110 °C 16-pin plastic DIP
16-pin plastic SOP
90
Caution Absolute maximum ratings are rated values beyond which some physical damages may be
caused to the product; if any of the parameters in the table above exceeds its rated value even
for a moment, the quality of the product may deteriorate. Be sure to use the product within the
rated values.
CAPACITANCE (TA = 25 ˚C, VDD = 0 V)
Symbol
Conditions
Input capacitance
CIN
I/O capacitance
CIO
f = 1 MHz
0 V for pins other than pins to be measured
Parameter
I/O: Input/output
48
Min.
Typ.
Max.
Unit
15
pF
15
pF
µPD17107(A1)
DC CHARACTERISTICS (TA = -40 to +110 ˚C, VDD = 2.5 to 6.0 V)
Parameter
Symbol
High-level input voltage
VIH1
P0C, P0D
VIH2
RESET
VIH3
P0B
VIH4
Low-level input voltage
High-level output
voltage
Typ.
Unit
0.7VDD
VDD
V
0.8VDD
VDD
V
Note 1
0.8VDD
VDD
V
Note 2
0.8VDD
9
V
VIL1
P0C, P0D
0
0.3VDD
V
VIL2
RESET
0
0.2VDD
V
VIL3
P0B
0
0.2VDD
V
VOH1
P0C, P0D
VOH2
Low-level output voltage
Min.
Max.
Conditions
VOL1
P0B, P0C,
P0D
VOL2
VDD = 4.5 to 6.0 V,
IOH = –2 mA
VDD – 2.0
V
IOH = –200 µA,
VDD – 1.0
V
VDD = 4.5 to 6.0 V,
IOL = 15 mA
2.0
V
IOL = 600 µA
0.5
V
ILIH1
P0C, P0D, VIN = VDD
5
µA
ILIH2
P0B, VIN = VDD
5
µA
ILIH3
P0B, VIN = 9 VNote 2
10
µA
Low-level input leakage
current
ILIL1
P0C, P0D, VIN = 0 V
–5
µA
ILIL2
P0B, VIN = 0 V
–5
µA
High-level output
leakage current
ILOH1
P0C, P0D, VOUT = VDD
5
µA
ILOH2
P0B, VOUT = VDD
5
µA
ILOH3
P0B, VOUT = 9 VNote 2
10
µA
Low-level output leakage current
ILOL
P0B, P0C, P0D, VOUT = 0 V
–5
µA
Built-in pull-up resistor
for pin RESET
RRES
20
47
110
kΩ
Built-in pull-up resistor
for pin P0B
RP0B
5
15
35
kΩ
Power supply
currentNote 3
IDD1
VDD = 5 V ±10 %,
fCC = 1.0 MHz ±20 %
0.4
1.2
mA
VDD = 3 V ±10 %,
fCC = 250 kHz ±20 %
50
150
µA
VDD = 5 V ±10 %,
fCC = 1.0 MHz ±20 %
0.3
0.9
mA
VDD = 3 V ±10 %,
fCC = 250 kHz ±20 %
40
120
µA
VDD = 5 V ±10 %
0.1
15
µA
VDD = 3 V ±10 %
0.1
10
µA
High-level input leakage
current
IDD2
IDD3
Operation
mode
HALT mode
STOP mode
Notes 1. When a built-in pull-up resistor is connected
2. When a built-in pull-up resistor is not connected
3. This current excludes the current which flows through the built-in pull-up resistors.
49
µPD17107(A1)
CHARACTERISTICS OF DATA MEMORY FOR HOLDING DATA ON LOW SUPPLY VOLTAGE IN THE STOP
MODE (TA = –40 to +110 ˚C)
Parameter
Symbol
Data hold supply voltage
VDDDR
Data hold supply
current
IDDDR
Conditions
Min.
Typ.
Max.
Unit
6.0
V
0.1
10
µA
Typ.
Max.
Unit
6.1
180
µs
21
180
µs
2.0
VDDDR = 2.0 V
AC CHARACTERISTICS (TA = –40 to +110 ˚C, VDD = 2.5 to 6.0 V)
Parameter
Symbol
CPU clock cycle time
(instruction execution
time)
tCY
Conditions
VDD = 4.5 to 6.0 V
Min.
High level width on
RLSHALT and RLSSTOP
tRLSH
10
µs
Low level width on
RESET
tRSL
10
µs
Remark tCY = 8/fCC (fCC: frequency of the system clock oscillator)
RLSHALT and RLSSTOP input timing
tRLSH
RLSHALT,
RLSSTOP
RESET input timing
tRSL
RESET
50
µPD17107(A1)
SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +110 ˚C)
Parameter
System clock oscillation frequency
Min.
Typ.
Max.
Unit
VDD = 4.5 to 5.5 V, ROSC = 24 kΩ
700
1000
1300
kHz
VDD = 2.7 to 3.3 V, ROSC = 100 kΩ
170
250
330
kHz
VDD = 2.5 to 6.0 V, ROSC = 100 kΩ
120
250
380
kHz
Symbol
fCC
Conditions
Caution The above conditions do not allow a resistance error.
fCC vs. ROSC
Clock oscillation frequency fCC [kHz]
(TA = 25 ˚C)
VDD = 5.0 V
1000
500
VDD = 3.0 V
100
50
1
10
100
500
Resistor for oscillation ROSC [kΩ]
51
µPD17107(A1)
12. CHARACTERISTIC CURVES (REFERENCE)
fCC vs. VDD for Operation Guarantee Range
(TA = –40 to +110 ˚C)
Resistor for oscillation ROSC [kΩ]
Clock oscillation frequency fCC [kHz]
1300
1000
500
380
300
Operation
guarantee
range
100
ROSC vs. VDD for Operation Guarantee Range
(TA = –40 to +110 ˚C)
50
45
30
OSC0 OSC1
10
500
330
Operation
guarantee range
100
50
24
10
OSC0 OSC1
R
1
0
R
5
1
2
3
4
5
6
Power supply voltage VDD [V]
3
1
0
1
2
3
4
5
6
Power supply voltage VDD [V]
fCC vs. VDD
(TA = 25 ˚C)
fCC vs. TA
1000
VDD = 5.0 V, R = 24 kΩ
1000
900
800
700
600
500
400
300
R = 100 kΩ
200
100
0
0
52
1100
R = 24 kΩ
R = 330 kΩ
5
1
2
4
6
3
Power supply voltage VDD [V]
Clock oscillation frequency fCC [kHz]
Clock oscillation frequency fCC [kHz]
1100
900
800
700
600
500
400
VDD = 3.0 V, R = 100 kΩ
300
200
VDD = 3.0 V, R = 330 kΩ
100
-40
0
25 50
85 110
Ambient temperature TA [˚C]
µPD17107(A1)
IOL vs. VOL
IDD vs. VDD
(TA = 25˚C)
R = 24 kΩ operation
R = 24 kΩ HALT
500
R = 100 kΩ operation
R = 100 kΩ HALT
R = 330 kΩ operation
R = 330 kΩ HALT
100
(TA = 25˚C)
35
50
10
OSC0 OSC1
R
VDD = 5 V VDD = 3.6 V
30
Output low current IOL [mA]
Power supply current IDD [µ A]
1000
25
VDD = 3 V
20
VDD = 2.7 V
15
10
1
0
1
2
3
4
5
6
Power supply voltage VDD [V]
5
0
0
1
2
3
Output low voltage VOL [V]
4
Caution The maximum absolute rating is 30 mA per
pin.
IOH vs. (VDD – VOH)
Output high current IOH [mA]
(TA = 25˚C)
VDD = 3.6 V
VDD = 5 V
VDD = 3 V
–5
VDD = 2.7 V
–4
–3
–2
–1
0
0
1
2
VDD – VOH [V]
Caution The maximum absolute rating is –5 mA per pin.
53
µPD17107(A1)
13. PACKAGE DRAWINGS
PACKAGE DRAWINGS OF MASS-PRODUCED PRODUCTS (1/2)
16 PIN PLASTIC DIP (300 mil)
16
9
1
8
A
I
K
L
H
G
J
P
F
C
D
N
R
M
B
M
NOTES
1) Each lead centerline is located within 0.25 mm (0.01 inch)
of its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
INCHES
A
20.32 MAX.
0.800 MAX.
B
1.27 MAX.
0.050 MAX.
C
2.54 (T.P.)
D
0.50±0.10
0.100 (T.P.)
+0.004
0.020 –0.005
F
1.1 MIN.
0.043 MIN.
G
3.5±0.3
0.138±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
L
7.62 (T.P.)
6.5
0.300 (T.P.)
0.256
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.25
0.01
P
1.1 MIN.
0.043 MIN.
R
0~15°
0~15°
P16C-100-300B-1
Caution The ES is different from the corresponding mass-produced products in shape and material. See
"ES PACKAGE DRAWINGS (1/2)."
54
µPD17107(A1)
PACKAGE DRAWINGS OF MASS-PRODUCED PRODUCTS (2/2)
16 PIN PLASTIC SOP (300 mil)
16
9
P
detail of lead end
1
8
A
H
J
E
K
F
G
I
C
N
D
M
B
L
M
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
10.46 MAX.
0.412 MAX.
B
0.78 MAX.
0.031 MAX.
C
1.27 (T.P.)
0.050 (T.P.)
D
0.40 +0.10
–0.05
0.016 +0.004
–0.003
E
0.1±0.1
0.004±0.004
F
1.8 MAX.
0.071 MAX.
G
1.55
0.061
H
7.7±0.3
0.303±0.012
I
5.6
0.220
J
1.1
0.043
K
0.20 +0.10
–0.05
0.008 +0.004
–0.002
L
0.6±0.2
0.024 +0.008
–0.009
M
0.12
0.005
N
0.10
0.004
P
3° +7°
–3°
3° +7°
–3°
P16GM-50-300B-4
Caution The ES is different from the corresponding mass-produced products in shape and material. See
"ES PACKAGE DRAWINGS (2/2)."
55
µPD17107(A1)
ES PACKAGE DRAWINGS (1/2)
16 PIN PLASTIC SOP (300 mil) (UNIT: mm)
20.32
16
1
7.62
17.78
1.91
0.89
0.33
56
2.54
0.254
µPD17107(A1)
ES PACKAGE DRAWINGS (2/2)
16 PIN CERAMIC SOP (FOR ES)
9
1
8
J
I
16
H
A
C
B
U
G
E
F
K
D
T
ITEM
MILLIMETERS
INCHES
A
10.16
0.40
B
1.02 MAX.
0.041 MAX.
C
1.27 (T.P.)
0.05 (T.P.)
D
0.43
0.017
E
0.48 MAX.
0.019 MAX.
F
2.54 MAX.
0.10 MAX.
G
1.7
0.067
H
12.1
0.476
I
6.9
0.272
J
K
2.35
0.13
0.093
0.005
T
U
4.8
0.025 MIN.
0.189
0.0 MIN.
X16B-50B-1
57
µPD17107(A1)
14. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the µPD17107(A1).
For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology
Manual (IEI-1207).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under
different conditions.
Table 14-1
Soldering Conditions for Surface-Mount Devices
µPD17107GS(A1)-×××: 16-pin plastic SOP (300 mil)
Soldering process
Soldering conditions
Recommended
conditions
Infrared ray reflow
Peak package's surface temperature: 235 ˚C
Reflow time: 30 seconds or less (210 ˚C or more)
Maximum allowable number of reflow processes: 2
<Cautions>
(1) Do not start reflow-soldering the device if its temperature is
higher than the room temperature because of a previous
reflow soldering.
(2) Do not use water for flux cleaning before a second reflow
soldering.
IR35-00-2
VPS
Peak package's surface temperature: 215 ˚C
Reflow time: 40 seconds or less (200 ˚C or more)
Maximum allowable number of reflow processes: 2
<Cautions>
(1) Do not start reflow-soldering the device if its temperature is
higher than the room temperature because of a previous
reflow soldering.
(2) Do not use water for flux cleaning before a second reflow
soldering.
VP15-00-2
Partial heating method
Terminal temperature: 300 ˚C or less
Heat time: 3 seconds or less (for each side of device)
–
Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
Table 14-2
Soldering Conditions for Through Hole Mount Devices
µPD17107CX(A1)-×××: 16-pin plastic DIP (300 mil)
Soldering process
Soldering conditions
Wave soldering
(Only for terminal sections)
Solder temperature: 260 °C or less
Flow time: 10 seconds or less
Partial heating method
Terminal temperature: 300 °C or less
Heat time: 3 seconds or less (for each terminal)
Caution In wave soldering, apply solder only to the terminal section. Care must be taken that jet solder
does not come in contact with the main body of the package.
58
µPD17107(A1)
APPENDIX
DEVELOPMENT TOOLS
The following support tools are available for developing programs for the µPD17107(A1).
Hardware
Name
Description
In-circuit emulator
IE-17K
IE-17K-ETNote 1
EMU-17KNote 2
The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators applicable to the 17K series.
The IE-17K and IE-17K-ET are connected to the PC-9800 series (host machine) or IBM PC/
ATTM through the RS-232-C interface. The EMU-17K is inserted into the extension slot of
SE board
(SE-17107)
The SE-17107 is an SE board for the µPD17107, µPD17107L, or µPD17P107. It is used
solely for evaluating the system. It is also used for debugging in combination with the incircuit emulator.
Emulation probe
(EP-17103CX)
The EP-17103CX is an emulation probe for the µPD17103, µPD17103L, µPD17P103,
µPD17107, µPD17107L, or µPD17P107.
PROM Programmer
AF-9703Note 3
The AF-9703, AF-9704, AF-9705, and AF-9706 are PROM writers for the µPD17P107. Use
one of these PROM writers with the program adapter, AF-9799, to program the µPD17P107.
the PC-9800 series (host machine).
Use the system evaluation board (SE board) corresponding to each product together with
one of these in-circuit emulators. SIMPLEHOST®, a man machine interface, implements an
advanced debug environment.
The EMU-17K also enables user to check the contents of the data memory in real time.
AF-9704Note 3
AF-9705Note 3
AF-9706Note 3
Programmer adapter
(AF-9799Note 3)
The AF-9799 is a socket unit for the µPD17P103, µPD17P104, µPD17P107, and
µPD17P108. It is used with the AF-9703, AF-9704, AF-9705, or AF-9706.
Notes 1. Low-end model, operating on an external power supply
2. The EMU-17K is a product of IC Co., Ltd. Contact IC Co., Ltd. (Tokyo, 03-3447-3793) for details.
3. The AF-9703, AF-9704, AF-9705, AF-9706, and AF-9799 are products of Ando Electric Co., Ltd. Contact
Ando Electric Co., Ltd. (Tokyo, 03-3733-1151) for details.
59
µPD17107(A1)
Software
Host
machine
Description
Name
17K series
assembler
(AS17K)
AS17K is an assembler
applicable to the 17K series.
In developing µPD17107(A1)
programs, AS17K is used in
combination with a device file
(AS17103).
Device file
(AS17103)
AS17103 contains a device file
for the µPD17107(A1) and
µPD17P107.
It is used together with the
assembler (AS17K) which is
applicable to the 17K series.
Support software
(SIMPLEHOST)
SIMPLEHOST, running on the
WindowsTM, provides manmachine-interface in developing
programs by using a personal
computer and the
in-circuit emulator.
PC-9800
series
IBM PC/AT
PC-9800
series
IBM PC/AT
PC-9800
series
OS
MS-DOS TM
PC DOS TM
MS-DOS
PC DOS
MS-DOS
IBM PC/AT PC DOS
Windows
Distribution
media
Part number
5.25-inch,
2HD
µS5A10AS17K
3.5-inch,
2HD
µS5A13AS17K
5.25-inch,
2HC
µS7B10AS17K
3.5-inch,
2HC
µS7B13AS17K
µS5A10AS17103
5.25-inch,
2HD
Note
3.5-inch,
2HD
Note
5.25-inch,
2HC
Note
3.5-inch,
2HC
Note
µS5A13AS17103
µS7B10AS17103
µS7B13AS17103
5.25-inch,
2HD
µS5A10IE17K
3.5-inch,
2HD
µS5A13IE17K
5.25-inch,
2HC
µS7B10IE17K
3.5-inch,
2HC
µS7B13IE17K
Note µS××××AS17103 contains a device file for the µPD17103, µPD17104, µPD17107, µPD17108, µPD17103L,
µPD17104L, µPD17107L, or µPD17108L.
Remark The following table lists the versions of the operating systems described in the above table.
OS
Versions
MS-DOS
Ver. 3.30 to Ver. 5.00ANote
PC DOS
Ver. 3.1 to Ver. 5.0Note
Windows
Ver. 3.0 to Ver. 3.1
Note MS-DOS versions 5.00 and 5.00A
and PC DOS Ver. 5.0 are provided
with a task swap function.
This
function, however, cannot be used
in these software packages.
60
µPD17107(A1)
Cautions on CMOS Devices
1
Countermeasures against static electricity for all MOSs
Caution When handling MOS devices, take care so that they are not electrostatically charged.
Strong static electricity may cause dielectric breakdown in gates. When transporting or storing
MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC
uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not
allow MOS devices to stand on plastic plates or do not touch pins.
Also handle boards on which MOS devices are mounted in the same way.
2
CMOS-specific handling of unused input pins
Caution Hold CMOS devices at a fixed input level.
Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting
in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused
pins may function as output pins at unexpected times, each unused pin should be separately
connected to the VDD or GND pin through a resistor.
If handling of unused pins is documented, follow the instructions in the document.
3
Statuses of all MOS devices at initialization
Caution The initial status of a MOS device is unpredictable when power is turned on.
Since characteristics of a MOS device are determined by the amount of ions implanted in
molecules, the initial status cannot be determined in the manufacture process. NEC has no
responsibility for the output statuses of pins, input and output settings, and the contents of
registers at power on. However, NEC assures operation after reset and items for mode setting
if they are defined.
When you turn on a device having a reset function, be sure to reset the device first.
61
µPD17107(A1)
SIMPLEHOST is a registered trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11