HY6264A Series 8Kx8bit CMOS SRAM DESCRIPTION minimize current drain is unnecessary for the HY6264A Series. The HY6264A is a high-speed, low power and 8,192x8-bits CMOS static RAM fabricated using Hyundai's high performance twin tub CMOS process technology. This high reliability process coupled with innovative circuit design techniques, yields maximum access time of 70ns. The HY6264A has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0 volt. Using the CMOS technology, supply voltage from 2.0 to 5.5 volt has little effect on supply current in the data retention mode. Reducing the supply voltage to FEATURES Product Voltage Speed No. (V) (ns) HY6264A 5.0 70/85/100 Note 1. Current value is max. Standby Current(uA) L LL 1mA 100 10 Operation Current(mA) 50 Fully static operation and Tri-state outputs TTL compatible inputs and outputs Low power consumption Battery backup(L/LL-part) -2.0V(min.) data retention • Standard pin configuration -28 pin 600 mil PDIP -28 pin 330 mil SOP NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Vcc /WE CS2 A8 A9 A11 /OE A10 /CS1 I/O8 I/O7 I/O6 I/O5 I/O4 A12 /CS1 CS2 PDIP SOP /OE /WE MEMORY ARRAY 128x512 I/O1 OUTPUT BUFFER ROW DECODER COLUMN DECODER Vcc /WE CS2 A8 A9 A11 /OE A10 /CS1 I/O8 I/O7 I/O6 I/O5 I/O4 ADD INPUT BUFFER 28 27 26 25 24 23 22 21 20 19 18 17 16 15 I/O8 CONTROL LOGIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SENSE AMP BLOCK DIAGRAM A0 NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss Temperature (°C) 0~70(Normal) WRITE DRIVER PIN CONNECTION • • • • PIN DESCRIPTION Pin Name /CS1 CS2 /WE /OE A0-A12 Pin Function Chip Select 1 Chip Select 2 Write Enable Output Enable Address Inputs Pin Name I/O1-I/O8 Vcc Vss NC Pin Function Data Input/Output Power(+5V) Ground No Connect This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.02 /Jan.99 Hyundai Semiconductor HY6264A Series ORDERING INFORMATION PART NO. HY6264AP HY6264ALP HY6264ALLP HY6264AJ HY6264ALJ HY6264ALLJ SPEED 70/85/100 70/85/100 70/85/100 70/85/100 70/85/100 70/85/100 POWER L-part LL-part L-part LL-part PACKAGE PDIP PDIP PDIP SOP SOP SOP ABSOLUTE MAXIMUM RATING (1) Symbol Vcc, VIN, VOUT TA TSTG PD IOUT TSOLDER Parameter Power Supply, Input/Output Voltage Operating Temperature Storage Temperature Power Dissipation Data Output Current Lead Soldering Temperature & Time Rating -0.5 to 7.0 0 to 70 -65 to 125 1.0 50 260 •10 Unit V °C °C W mA °C•sec Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for an extended period may affect reliability. RECOMMENDED DC OPERATING CONDITIONS TA=0°C TO 70°C Symbol Parameter Vcc Supply Voltage VIH Input High Voltage VIL Input Low Voltage Min. 4.5 2.2 -0.5(1) Typ. 5.0 - Max. 5.5 Vcc+0.5 0.8 Unit V V V Note 1.VIL = -3.0V for pulse width less than 50ns TRUTH TABLE /CS1 H X L L L CS2 X L H H H /WE X X H H L /OE X X H L X MODE Standby Output Disabled Read Write I/O OPERATION High-Z High-Z High-Z Data Out Data In Note 1. H=VIH, L=VIL, X=Don't Care Rev.02 /Jan.99 2 HY6264A Series DC ELECTRICAL CHARACTERISTICS Vcc = 5.0V±10%, TA = 0°C to 70°C (Normal) unless otherwise specified Symbol Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc ILO Output Leakage Current Vss < VOUT < Vcc /CS1=VIH or CS2=VIL or /OE = VIH or/ WE = VIL Icc Operating Power Supply /CS1 = VIL, CS2=VIH, Current VIN = VIH or VIL, II/O = 0mA ICC1 Average Operating /CS1 = VIL, CS2=VIH Min. Duty Current Cycle = 100%, II/O = 0mA ISB TTL Standby Current /CS1 = VIH or CS2=VIL (TTL Input) ISB1 CMOS Standby Current /CS1 > Vcc - 0.2V, (CMOS Input) CS2 < 0.2V,or L CS2 >Vcc-0.2V LL VOL Output Low Voltage IOL = 2.1mA VOH Output High Voltage IOH = -1.0mA Min -1 -1 Typ - Max 1 1 Unit uA uA - 30 50 mA - 30 50 mA - 0.4 2 mA 2.4 2 1 - 1 100 10 0.4 - mA uA uA V V Note : Typical values are at Vcc = 5.0V, TA = 25°C AC CHARACTERISTICS Vcc = 5.0V±10%, TA = 0°C to 70°C (Normal), unless otherwise noted -70 -85 # Parameter Symbol Min Max Min Max READ CYCLE 1 tRC Read Cycle Time 70 85 2 tAA Address Access Time 70 85 3 tACS Chip Select Access Time 70 85 4 tOE Output Enable to Output Valid 45 50 5 tCLZ Chip Select to Output in Low Z 10 10 6 tOLZ Output Enable to Outputin Low Z 5 5 7 tCHZ Chip Deselection to Output in High Z 0 30 0 35 8 tOHZ Out Disable to Output in High Z 0 30 0 35 9 tOH Output Hold from Address Change 5 5 WRITE CYCLE 10 tWC Write Cycle Time 70 85 11 tCW Chip Selection to End of Write 55 60 12 tAW Address Valid to End of Write 55 60 13 tAS Address Set-up Time 0 0 14 tWP Write Pulse Width 50 55 15 tWR Write Recovery Time 0 0 16 tWHZ Write to Output in High Z 0 30 0 35 17 tDW Data to Write Time Overlap 35 35 18 tDH Data Hold from Write Time 0 0 19 tOW Output Active from End of Write 5 5 - Rev.02 /Jan.99 -10 Min Max Unit 100 10 5 0 0 10 100 100 55 35 35 - ns ns ns ns ns ns ns ns ns 100 70 70 0 60 0 0 40 0 5 35 - ns ns ns ns ns ns ns ns ns ns 3 HY6264A Series AC TEST CONDITIONS TA = 0°C to 70°C (Normal), unless otherwise specified. PARAMETER Value Input Pulse Level 0.8V to 2.4V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load CL = 100pF + 1TTL Load AC TEST LOADS TTL CL(1) Note : Including jig and scope capacitance CAPACITANCE Temp = 25°C, f= 1.0MHz Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Condition VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF Note : These parameter are sampled and not 100% tested TIMING DIAGRAM READ CYCLE 1(Note 1) tRC ADDR tAA OE tOE tOH tOLZ CS1 CS2 tACS tOHZ tCHZ tCLZ Data Out Rev.02 /Jan.99 High-Z Data Valid 4 HY6264A Series Note(READ CYCLE): 1.tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2.At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3./WE is high for the read cycle. READ CYCLE 2(Note 1,2,3) tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid Note(Read Cycle) 1./WE is high for the read cycle. 2.Device is continuously selected /CS=VIL, CS2=VIH. 3./OE=VIL. WRITE CYCLE 1(/WE Controlled) tWC ADDR tAW tWR(2) tCW CS1 CS2 tWP tAS WE tDW Data In Data Valid tOHZ Data Out Rev.02 /Jan.99 tDH Data Undefined tOW High-Z 5 HY6264A Series WRITE CYCLE 2 (/CS1Controlled) tWC ADDR tWR1 tAS tCW CS1 tAW tWR2 CS2 tWP WE tDH tDW Data In Data Valid High-Z tCLZ tWHZ Data Out High-Z High-Z WRITE CYCLE 3 (CS2 Controlled) tWC ADDR tAS tWR1 tCW CS1 tAW tWR2 CS2 tWP WE tDW Data In tDH Data Valid High-Z tCLZ tWHZ Data Out Rev.02 /Jan.99 High-Z High-Z 6 HY6264A Series Notes(Write Cycle): 1. A write occurs during the overlap of a low /CS1 and high CS2 and a low /WE. A write begins at the latest transition among /CS1 going low, CS2 going high and /WE going low: A write ends at the earliest transition among /CS1 going high, CS2 going low and /WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS1 going low or CS2 going high to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 is applied in case a write ends as /CS1, or /WE going high, and tWR2 is applied in case a write ends at CS2 going low. 5. If /OE, CS2 and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state, inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS1 goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. 7. DOUT is the read data of the new address. 8. When /CS1 is low and CS2 is high,I /O pins are in the output state. The input signals in the opposite phase leading to the outputs should not be applied. DATA RETENTION CHARACTERISTICS. Symbol VDR Parameter Vcc for Data Retention ICCDR Data Retention Current tCDR Chip Disable to Data Retention Time Operating Recovery Time tR Test Condition /CS1>Vcc-0.2V, CS2¡ Â 0.2V or>Vcc-0.2V, Vss<VIN<Vcc Vcc = 3.0V, /CS1>Vcc-0.2V CS2<0.2V or >Vcc-0.2V Vss<VIN<Vcc See Data Retention Timing Diagram L LL Min 2 Typ - Max - Unit V - 1 1 50 5 uA uA 0 - - ns tRC(2) - - ns Note 1.Typical values are under the condition of TA=25°C. 2.tRC is read cycle time DATA RETENTION TIMING DIAGRAM 1 DATA RETENTION MODE VCC 4.5V tCDR tR 2.2V VDR CS1>VCC-0.2V CS1 VSS Rev.02 /Jan.99 7 HY6264A Series DATA RETENTION TIMING DIAGRAM 2 DATA RETENTION MODE VCC 4.5V tR tCDR CS2 VDR 0.4V CS2<0.2V VSS RELIABILITY SPEC. TEST MODE ESD HBM MM LATCH - UP Rev.02 /Jan.99 TEST SPEC. > 2000V > 250V < -100mA >100mA 8 HY6264A Series PACKAGE INFORMATION 28pin 600mil Dual In-Line Package(P) • UNIT : INCH(mm) MAX. MIN. 1.467(37.262) 1.447(36.754) 0.600(15.240)BSC 0.090(2.286) 0.065(1.650) 0.070(1.778) 0.050(1.270) 0.550(13.970) 0.155(3.937) 0.530(13.462) 0.145(3.683) 0.035(0.889) 0.020(0.508) 0.140(3.556) 0.021(0.533) 0.100(2.54)BSC 3 deg 11 deg 0.120(3.048) 0.014(0.356) 0.008(0.200) 0.015(0.381) 28pin 330mil Small Outline Package(J) 0.346(8.788) UNIT : INCH(mm) MAX .MIN. 0.338(8.585) 0.480(12.192) 0.460(11.684) 0.096(2.438) 0.728(18.491) 0.720(18.288) 0.092(2.335) 0.012(0.305) 0.014(0.356) 0.002(0.051) 0.050(1.270)BSC Rev.02 /Jan.99 0.020(0.508) 0.014(0.356) 0.008(0.203) 0.050(1.270) 0.030(0.762) 9