HY638100 Series 128Kx8bit CMOS FAST SRAM DESCRIPTION The HY638100 is a high-speed 131,072 x 8-bits CMOS static RAM fabricated using Hyundai's high performance CMOS process technology. This high reliability process coupled with high-speed circuit design techniques, yields maximum access time of 15ns. The HY638100 has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0 volt. It is suitable for use in highdensity high-speed system applications. PIN CONNECTION A0 A1 A2 A3 /CS I/O1 I/O2 Vcc Vss I/O3 I/O4 /WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 /OE /WE OUTPUT BUFFER WRITE DRIVER /CS COLUMN DECODER A16 MEMORY ARRAY 512x2048 I/O1 I/O8 PIN DESCRIPTION Pin Name /CS /WE /OE A0~A16 I/O1~I/O8 Vcc Vss A16 A15 A14 A13 /OE I/O8 I/O7 Vss Vcc I/O6 I/O5 A12 A11 A10 A9 A8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ROW DECODER A0 ADD INPUT BUFFER • Single 5V±10% Power Supply • High speed - 15/20/25ns(max.) • Low power consumption(Max.) Mode Conditions Current Units Operating 15ns 150 mA 20/25ns 140 mA Standby TTL 40 mA CMOS 2 mA L 500 uA • Battery backup(L-part) - 2.0V(min.) data retention • Fully static operation and Tri-state outputs - No clock or refresh required • TTL compatible inputs and outputs • Standard pin configuration - 32pin 400mil SOJ - 32pin 400mil TSOP-II SENSE AMP BLOCK DIAGRM CONTROL LOGIC FEATURES Pin Function Chip Select Write Enable Output Enable Adderss Input Data Input/Output Power(+5.0V) Ground SOJ/TSOP-II ORDERING INFORMATION Part No. HY638100J HY638100LJ HY638100T2 HY638100LT2 Speed 15/20/25 15/20/25 15/20/25 15/20/25 Power L-part L-part Package SOJ SOJ TSOP-II TSOP-II This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.02 / Dec.97 Hyundai Semiconductor HY638100 Series ABSOLUTE MAXIMUM RATING (1) Symbol VCC, VIN, VOUT TA TSTG PD IOUT TSOLDER Parameter Power Supply, Input/Output Voltage Operating Temperature Storage Temperature Power Dissipation Data Output Current Lead Soldering Temperature & Time Rating -0.5 to 7.0 0 to 70 -65 to 150 1.0 50 260 • 10 Unit V °C °C W mA °C • sec Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. RECOMMENDED DC OPERATING CONDITIONS TA=0°C to 70°C Symbol Parameter VCC Supply Voltage VSS Ground VIH Input High Voltage VIL Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ 5.0 0 - Max. 5.5 0 Vcc+0.5 0.8 Unit V V V V Note 1. VIL = -3.0V for pulse width less than 10ns TRUTH TABLE /CS H L L L /WE X H H L /OE X H L X Mode Standby Output Disabled Read Write I/O Operation Hi-Z Hi-Z DOUT DIN Note: 1. H=VIH, L=VIL, X=Don't care Rev.02 / Dec.97 2 HY638100 Series DC ELECTRICAL CHARACTERISTICS Vcc = 5.0V±10%, TA = 0°C to 70°C, unless otherwise specified. Symbol Parameter Test Conditions IIL Input Leakage Current VSS < VIN < VCC ILO Output Leakage Current VSS < VOUT < VCC, /CS = VIH or /OE = VIH or /WE = VIL ICC1 Average Operating /CS = VIL, II/O = 0mA, 15ns Current Min. Duty Cycle = 100% 20/25ns ISB TTL Standby Current /CS = VIH, VIN=VIH or VIL Min. Cycle (TTL Inputs) ISB1 CMOS Standby Current /CS > VCC-0.2V, VIN > (CMOS Inputs) VCC-0.2V or VIN < 0.2V L VOL Output Low Voltage IOL = 8.0mA VOH Output High Voltage IOH = -4.0mA Min -2 -2 Typ - Max 2 2 Unit uA uA - - 150 140 40 mA mA mA 2.4 50 - 2 500 0.4 - mA uA V V Note : Typical values are at Vcc = 5.0V, TA = 25°C AC CHARACTERISTICS Vcc = 5.0V±10%, TA = 0°C to 70°C, unless otherwise specified. -15 # Symbol Parameter Min Max READ CYCLE 1 TRC Read Cycle Time 15 2 TAA Address Access Time 15 3 TACS Chip Select Access Time 15 4 TOE Output Enable to Output Valid 7 5 TCLZ Chip Select to Output in Low Z 3 6 TOLZ Output Enable to Output in Low Z 3 7 TCHZ Chip Deselecting to Output in High Z 0 8 8 TOHZ Out Disable to Output in High Z 0 8 9 TOH Output Hold from Address Change 3 WRITE CYCLE 10 TWC Write Cycle Time 15 11 TCW Chip Select to End of Write 12 12 tAW Address Valid to End of Write 12 13 tAS Address Set-up Time 0 14 tWP Write Pulse Width 12 15 tWR Write Recovery Time 2 16 tWHZ Write to Output in High Z 0 7 17 tDW Data to Write Time Overlap 8 18 tDH Data Hold from Write Time 0 19 tOW Output Active from End of Write 3 - Rev.02 / Dec.97 -20 Min Max -25 Unit Min Max 20 3 3 0 0 3 20 20 9 9 9 - 25 3 3 0 0 3 25 25 10 10 10 - ns ns ns ns ns ns ns ns ns 20 15 15 0 15 2 0 9 0 3 9 - 25 17 17 0 17 2 0 10 0 3 10 - ns ns ns ns ns ns ns ns ns ns 3 HY638100 Series AC TEST CONDITIONS Vcc = 5.0V±10%, TA = 0°C to 70°C, unless otherwise specified. Parameter Value Input Pulse Level 0V to 3.0V Input Rise and Fall Time 3ns Input and Output Timing Reference Level 1.5V Output Load See below AC TEST LOADS Output Load (A) Output Load (B) (for tCHZ, tCLZ, tOHZ, tOLZ, tWHZ & tOW) +5V +5V 480 Ohm 480 Ohm DOUT DOUT 255 Ohm CL=30pF(1) CL=5pF(1) 255 Ohm Note : Including jig and scope capacitance CAPACITANCE Temp = 25°C, f= 1.0MHz Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Condition VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF Note : This parameter is sampled and not 100% tested Rev.02 / Dec.97 4 HY638100 Series TIMING DIAGRAM READ CYCLE 1 tRC ADDR tAA OE tOE tOH tOLZ CS tACS tOHZ tCHZ tCLZ Data Out High-Z Data Valid Note (Read Cycle) 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. /WE is high for read cycle. READ CYCLE 2 tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid Note (Read Cycle) 1. /WE is high for read cycle. 2. Device is continuously selected /CS=VIL. 3. /OE=VIL. Rev.02 / Dec.97 5 HY638100 Series WRITE CYCLE 1(/OE Clocked) tWC ADDR OE tAW tCW CS tAS tWR tWP WE tDW Data In tDH Data Valid tOHZ Data Out WRITE CYCLE 2(/OE Low Fixed) tWC ADDR tAW tCW tWR CS tAS tWP WE tDW Data In tDH Data Valid tWHZ tOW (7) (8) Data Out Rev.02 / Dec.97 6 HY638100 Series Notes(Write Cycle) 1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among /CS going low, and /WE going low : A write ends at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. If /OE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state, inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high impedance state. 7. DOUT is the same phase of latest written data in the write cycle. 8. DOUT is the read data of the new address. DATA RETENTION ELECTRIC CHARACTERISTIC( L-Version ) TA=0°C to 70°C Symbol Parameter VDR Vcc for Data Retention ICCDR Data Retention urrent TCDR Chip Deselect to Data Retention Time Operating Recovery Time TR Test Conditions Power /CS > Vcc - 0.2V Vcc = 3V, /CS > Vcc-0.2V L Vin > Vcc – 0.2 or < 0.2V See Data Retention Timing Diagram Min 2.0 - Typ 10 Max 50 Unit V uA 0 - - ns tRC(2) - - ns Notes 1. Typical values are at the condition of TA=25°C 2. tRC is read cycle time DATA RETENTION WAVEFORM DATA RETENTION MODE VCC 4.5V tCDR tR 2.2V VDR CS>VCC-0.2V CS VSS RELIABILITY SPEC. TEST MODE ESD HBM MM LATCH - UP Rev.02 / Dec.97 TEST SPEC. > 2000V > 250V < -100mA > 100mA 7 HY638100 Series PACKAGE INFORMATION 32pin 400mil Small Outline J-Form Package (J) 0.032(0.8128) 0.040(1.016) 0.026(0.6604) 0.030(0.762) 0.405(10.287) 0.380(9.6520) 0.444(11.2776) 0.395(10.033) 0.368(9.3472) 0.436(11.0744) 0.0098(0.2489) 0.0075(0.1905) 0.829(21.0566) 0.821(20.8534) 0.148(3.759) 0.138(3.505) 0.050(1.27) BSC . MAX. UNIT : INCH(mm) MIN. 0.020(0.508) 0.016(0.406) 32pin 400mil Thin Small Outline Package (T2) 0.404(10.2620) 0.396(10.0580) UNIT : INCH(mm) 0.470(11.9380) MAX. MIN. 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) GAGE PLANE BASE PLANE 0-5 0.0235(0.5970) 1.2700 BSC 0.017(0.4500) (0.050) 0.012(0.3050) 0.047(1.1940) 0.039(0.9910) Rev.02 / Dec.97 SEATING PLANE 0.0059(0.1500) 0.0020(0.0500) 0.0160(0.4060) 0.0038(0.2100) 0.0047(0.1200) 8