HY628100B Series 128Kx8bit CMOS SRAM Document Title 128K x8 bit 5.0V Low Power CMOS slow SRAM Revision History Revision No History Draft Date Remark 10 Initial Revision History Insert Jul.14.2000 Final This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 10 / Jul.00 Hyundai Semiconductor HY628100B Series DESCRIPTION FEATURES The HY628100B is a high speed, low power and 1M bit CMOS Static Random Access Memory organized as 131,072 words by 8bit. The HY628100B uses high performance CMOS process technology and designed for high speed low power circuit technology. It is particulary well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0V. • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup(L/LL-part) -. 2.0V(min) data retention • Standard pin configuration -. 32 - SOP - 525mil -. 32 - TSOPI - 8X20(Standard) Product Voltage Speed Operation No (V) (ns) Current/Icc(mA) HY628100B 4.5~5.5 50*/55/70/85 10 Comment : 50ns is available with 30pF test load. Standby Current(uA) L LL 100 20 Temperature (°C) 0~70 PIN CONNECTION NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Vcc A15 CS2 /WE A13 A8 A9 A11 /OE A10 /CS1 I/O8 I/O7 I/O6 I/O5 I/O4 SOP A11 A9 A8 A13 /WE CS2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 /OE A10 /CS1 DQ8 DQ7 DQ6 DQ5 DQ4 Vss DQ3 DQ2 DQ1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TSOP-I(Standard) PIN DESCRIPTION BLOCK DIAGRAM A0 ROW DECODER WRITE DRIVER MEMORY ARRAY 128K x 8 I/O1 DATA I/O BUFFER SENSE AMP A16 COLUMN DECODER Pin Function Chip Select 1 Chip Select 2 Write Enable Output Enable Address Inputs Data Inputs / Outputs Power(4.5V~5.5V) Ground ADD INPUT BUFFER Pin Name /CS1 CS2 /WE /OE A0 ~ A16 I/O1 ~ I/O8 Vcc Vss I/O8 /CS1 /OE CONTROL LOGIC CS2 /WE Rev 10 / Jul.00 2 HY628100B Series ORDERING INFORMATION Part No. Speed Power HY628100BLG 55/70/85 L-part HY628100BLLG 55/70/85 LL-part HY628100BLT1 55/70/85 L-part HY628100BLLT1 55/70/85 LL-part Comment : 50ns is available with 30pF test load. Temp Package SOP SOP TSOPI(Standard) TSOPI(Standard) ABSOLUTE MAXIMUM RATING (1) Symbol Vcc, VIN, VOUT TA TSTG PD IOUT TSOLDER Parameter Power Supply, Input/Output Voltage Operating Temperature Storage Temperature Power Dissipation Data Output Current Lead Soldering Temperature & Time Rating -0.5 to 7.0 0 to 70 -65 to 125 1.0 50 260 •10 Unit V °C °C W mA °C•sec Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliablity. TRUTH TABLE /CS1 H X L L L CS2 X L H H H /WE X X H H L /OE X X H L X Mode Deselected Deselected Output Disabled Read Write I/O High-Z High-Z High-Z Data Out Data In Power Standby Standby Active Active Active Note : 1. H=VIH, L=VIL, X=don't care( VIH or VIL ) Rev 10 / Jul.00 2 HY628100B Series RECOMMENDED DC OPERATING CONDITION TA=0°C to 70°C Symbol Parameter Vcc Supply Voltage Vss Ground VIH Input High Voltage VIL Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 - Max. 5.5 0 Vcc+0.5 0.8 Unit V V V V Note : 1. VIL = -1.5V for pulse width less than 30ns and not 100% tested DC ELECTRICAL CHARACTERISTICS Vcc = 4.5V~5.5V, TA = 0°C to 70°C, unless otherwise specified Symbol Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc ILO Output Leakage Current Vss < VOUT < Vcc, /CS1 = VIH or CS2 = VIL or /OE = VIH or /WE = VIL Icc Operating Power Supply /CS1 = VIL, CS2 = VIH, Current VIN = VIH or VIL, II/O = 0mA ICC1 Average Operating /CS1 = VIL, CS2 = VIH, Current VIN = VIH or VIL Cycle Time = Min, 100% duty, IIO = 0mA ISB TTL Standby Current /CS1 = VIH or CS2 = VIL (TTL Input) ISB1 Standby Current /CS1 > Vcc - 0.2V L (CMOS Input) CS2 < 0.2V or LL CS2 > Vcc - 0.2V VOL Output Low Voltage IOL = 2.1mA VOH Output High Voltage IOH = -1mA Min. -1 -1 Typ. - Max. 1 1 Unit uA uA - - 10 mA - - 50 mA - - 2 mA - 2 1 100 20 uA uA 2.4 - 0.4 - V V Note : Typical values are at Vcc = 5.0V, TA = 25°C CAPACITANCE Temp = 25°C, f= 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Condition VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF Note : These parameters are sampled and not 100% tested Rev 10 / Jul.00 3 HY628100B Series AC CHARACTERISTICS Vcc = 4.5V~5.5V, TA = 0°C to 70°C, unless otherwise specified -55 # Symbol Parameter Min. Max. READ CYCLE 1 tRC Read Cycle Time 55 2 tAA* Address Access Time 55 3 tACS* Chip Select Access Time 55 4 tOE Output Enable to Output Valid 25 5 tCLZ Chip Select to Output in Low Z 10 6 tOLZ Output Enable to Output in Low Z 5 7 tCHZ Chip Deselection to Output in High Z 0 20 8 tOHZ Out Disable to Output in High Z 0 20 9 tOH Output Hold from Address Change 10 WRITE CYCLE 10 tWC Write Cycle Time 55 11 tCW Chip Selection to End of Write 45 12 tAW Address Valid to End of Write 45 13 tAS Address Set-up Time 0 14 tWP Write Pulse Width 40 15 tWR Write Recovery Time 0 16 tWHZ Write to Output in High Z 0 20 17 tDW Data to Write Time Overlap 25 18 tDH Data Hold from Write Time 0 19 tOW Output Active from End of Write 5 Comment : tAA* and tACS* can meet 50ns with 30pF test load. Min. -70 Max. Min -85 Max. Unit 70 10 5 0 0 10 70 70 35 25 25 - 85 10 5 0 0 10 85 85 45 30 30 - ns ns ns ns ns ns ns ns ns 70 60 60 0 50 0 0 30 0 5 25 - 85 70 70 0 55 0 0 40 0 5 30 - ns ns ns ns ns ns ns ns ns ns AC TEST CONDITIONS TA = 0°C to 70°C, unless otherwise specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load Value 0.8V to 2.4V 5ns 1.5V CL = 100pF + 1TTL Load CL* = 30pF + 1TTL Load Comment * : Test load is 30pF for 50ns AC TEST LOADS TTL CL(1) Note : Including jig and scope capacitance Rev 10 / Jul.00 4 HY628100B Series TIMING DIAGRAM READ CYCLE 1(Note 1,4) tRC ADDR tAA tOH tACS /CS1 CS2 tCHZ(3) tOE /OE tOLZ(3) Data Out tOHZ(3) tCLZ(3) High-Z Data Valid READ CYCLE 2(Note 1,2,4) tRC ADDR tAA tOH tOH Data Out Data Valid Previous Data READ CYCLE 3(Note 1,2,4) /CS1 CS2 tACS tCLZ(3) Data Out tCHZ(3) Data Valid Notes: 1. Read Cycle occurs whenever a high on the /WE and /OE is low /CS1 and CS2 are in active status. 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active Rev 10 / Jul.00 5 HY628100B Series WRITE CYCLE 1(1,4,5,9) (/WE Controlled) tW C ADDR tW R (2) tCW /CS1 CS2 tAW tW P /W E tAS Data In tDW High-Z tDH Data Valid tW H Z (3,8) tOW (6) (7) Data Out WRITE CYCLE 2 (Note 1,4,5,9) (/CS1, CS2 Controlled) tW C ADDR tCW tAS tW R (2) /CS1 tAW CS2 tW P /W E tDW Data In Data Out High-Z tDH Data Valid High-Z Notes: 1. A write occurs whenever a low on the /WE and /OE is low /CS1 and CS2 are in active state. 2. tWR is measured from the earlier of /CS1 or /WE going high or CS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the the /CS1 low transition and CS2 high transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. /OE is continuously low(/OE=VIL) 6. Q(data out) is the same phase with the write data of this write cycle. 7. Q(data out) is the read data of the next address. 8. Transition is measured +200mV from steady state. This parameter is sampled and not 100% tested. 9. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active Rev 10 / Jul.00 6 HY628100B Series DATA RETENTION ELECTRIC CHARACTERISTIC TA=0°C to 70°C Sym Parameter VDR Vcc for Data Retention ICCDR tCDR tR Test Condition /CS1 > Vcc - 0.2V, CS2 < 0.2V or > Vcc - 0.2V, Vss<VIN<Vcc Data Retention Current Vcc = 3.0V, /CS1>Vcc - 0.2V L CS2< 0.2V or > Vcc - 0.2V, LL Vss<VIN<Vcc Chip Deselect to Data Retention Time Operating Recovery Time Min 2.0 Typ - Max - Unit V - 2 1 50 10 uA uA 0 tRC(2) - - ns ns Notes: 1. Typical values are under the condition of TA = 25°C. 2. tRC is read cycle time. DATA RETENTION TIMING DIAGRAM 1 DATA RETENTION MODE VCC 4.5V tCDR tR 2.2V VDR CS1>VCC-0.2V CS1 VSS DATA RETENTION TIMING DIAGRAM 2 DATA RETENTION MODE VCC 4.5V tR tCDR CS2 VDR 0.4V VSS Rev 10 / Jul.00 CS2<0.2V 7 HY628100B Series PACKAGE INFORMATION 32pin 525mil Small Outline Package(G) UNIT : INCH(mm) 0.810(20.574) 0.804(20.422) 0.444(11.278) 0.438(11.125) 0.564(14.326) 0.546(13.868) 0.109(2.769) 0.099(2.515) 0.011(0.279) 0.004(0.102) 0.050(1.27)BSC 0.0125(0.318) 0.0061(0.155) 0.020(0.508) 0 deg 0.0425(1.080) 0.014(0.356) 8 deg 0.0235(0.597) 32pin 8x20mm Thin Small Outline Package Standard(T1) #1 #32 UNIT : INCH(mm) 0.319(8.103) 0.311(7.900) #17 #16 0.728(18.491) 0.720(18.288) 0.792(20.117) 0.784(19.914) 0.041(1.05) 0.037(0.95) 0.006(0.15) 0.002(0.05) 0.025(0.64) 0.021(0.54) Rev 10 / Jul.00 0.008(0.21) 0.004(0.10) 0.020(0.50) BSC 0.011(0.27) 0.007(0.17) 8