XR-T7288 ...the analog plus CEPT1 Line Interface company TM June 1997-3 FEATURES Fully Integrated 2.048Mbits/s Line Interface Minimal External Circuitry Required Intended For Use In Systems That Must Comply With CCITT Specifications G.703, G.823, I.431, G.732, G.735, G.739 Robust Frequency Acquisition/Phase-Locked Loop Pin-Selectable 75Ω or 120Ω Operation Loopback Modes for Fault Isolation Monolithic Clock Recovery Multiple Link-Status and Alarm Features Pin-Selectable HDB3 Encoder and Decoder Low Power Dissipation: 100mW for 120Ω Twisted Pair, Typical 108mW for 75Ω Coaxial, Typical Single-Rail/Dual-Rail Interface GENERAL DESCRIPTION The XR-T7288 CEPT1 Line Interface is an integrated circuit that provides a 2.048 Mbits/s line interface to either twisted-pair or coaxial cable as specified in CCITT requirements G.703, G.823, I.431, G.732, and G.735 G.739. The device performs receive pulse regeneration, timing recovery, and transmit pulse driving functions. The XR-T7288 device is manufactured by using low-power CMOS technology and is available in a 28-pin, plastic DIP or in a 28-pin, plastic SOJ package for surface mounting. The XR-T7288 device is functionally compatible with the LC1135B device. The digital circuitry is shown in Figure 1.; the analog circuitry is shown in Figure 6. ORDERING INFORMATION Part No. Package Operating Temperature Range XR-T7288IP 28 Lead 300 Mil PDIP -40°C to +85°C XR-T7288IW 28 Lead 300 Mil Jedec SOJ -40°C to +85°C Rev. 1.01 1992 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 1 XR-T7288 ÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ Î ÎÎÎÎÎ ÎÎÎ Î ÎÎ ÎÎÎ Î ÎÎ HDB3/TNDATA MUX ZS LP2 TBC Blue (AIS) Signal Generator BClk All Analog Functions +5 ALMT VDDA HDB3 Encoder Output Drivers And Logic +5 VDDD Figure 1. Digital Block Diagram Rev. 1.01 2 Output Drivers And Logic GND GNDD All Analog Functions GND GNDA MUX Single-to Dual Rail Converter MUX MUX MUX HDB3/TNDATA RDATA/ RPDATA VIO/ RNDATA MUX SR/DR Blue Signal (AIS) Generator ÎÎ Î ÎÎ ÎÎ Î ÎÎ Î ÎÎ Î ÎÎ ÎÎÎ ÎÎ Î ÎÎÎ RClk MUX Transmit R2 HDB3 Decoder Î Î Î Î Î Î Î ÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ FLM TDATA/ TPDATA MUX T2 MUX MUX MUX R1 Loss Of Clock Detection MUX Receive Dual - To Single Rail Converter MUX T1 MUX MUX ÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎ Bipolar Violation Detection RBC SR/DR MUX HDB3 Code Violation Detection MUX LP3 MUX LOC MUX SD LOS LP1 HDB3/ TNDATA TClk XR-T7288 PIN CONFIGURATION LOS LOC HDB3/TNDATA VIO/RNDATA RClk RDATA/RPDATA TClk TDATA/TPDATA LP1 LP2 LP3 ALMT RBC TBC 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 T1 R1 SD GNDA VDDA ZS T2 VDDD R2 GNDD NC FLM SR/DR BClk LOS LOC HDB3/TNDATA VIO/RNDATA RClk RDATA/RPDATA TClk TDATA/TPDATA LP1 LP2 LP3 ALMT RBC TBC 28 Lead PDIP (0.300”) 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 T1 R1 SD GNDA VDDA ZS T2 VDDD R2 GNDD NC FLM SR/DR BClk 28 Lead SOJ (Jedec, 0.300”) PIN DESCRIPTION Pin # Symbol Type Description 1 LOS O Loss of Signal (Active-Low). This pin is cleared (0) upon loss of the data signal at the receiver inputs. 2 LOC O Loss of Clock (Active-Low). This pin is cleared when SD = 1 and LOS= 0, indicating that a loss of clock has occurred. When LOC= 0, no transitions occur on the RClk and on either RDATA (for single-rail) or RPDATA and RNDATA (for dual-rail operation) outputs. A valid clock must be present at BClk for this function to operate properly. 3 HDB3/ TNDATA I HDB3 Enable/N-Rail Transmit Data. If SR/DR = 0, this pin is set (1) to insert an HDB3 substitution code on the transmit side and to remove the substitution code on the receive side. If SR/DR = 1, this pin is used as the n-rail transmit input data (internal pull-down is included). 4 VIO/ RNDATA O Violation/N-Rail Receive Data. If SR/DR = 0 and HDB3 = 0, bipolar violations on the receive side input are detected, causing VIO to be set; if HDB3 = 1, HDB3 code violations cause VIO to be set. If SR/DR =1, this pin is used as the n-rail receive output data. 5 RClk O Receive Clock. Output receive clock signal to the terminal equipment. 6 RDATA/ RPDATA O Receive Data/P-Rail Receive Data. If SR/DR = 0, this pin is used for 2.048 Mbits/s unipolar output data with a 100% duty cycle. If SR/DR = 1, this pin is used as the p-rail receive output data. 7 TClk I Transmit Clock. Input clock signal (2.048 MHz 80 ppm). 8 TDATA/ TPDATA I Transmit Data/P-Rail Transmit Data. If SR/DR = 0, this pin is used as 2.048 Mbits/s unipolar input data. If SR/DR = 1, this pin is used as the p-rail transmit input data. 9 LP1 I Loopback 1 Enable (Active-Low). This pin is cleared for a full local loopback (transmit converter output to receive converter input). Most of the transmit and receive analog circuitry is exercised in this loopback (internal pull-up is included). 10 LP2 I Loopback 2 Enable (Active-Low). This pin is cleared for a remote loopback. In loopback 2, a high on TBC (pin 14) inserts the blue signal (AIS) on the transmit side (internal pull-up is included). Rev. 1.01 3 XR-T7288 PIN DESCRIPTION (CONT’D) Pin # Symbol Type Description 11 LP3 I Loopback 3 Enable (Active-Low). This pin is cleared for a digital local loopback. Only the transmit and receive digital sections are exercised in this loopback (internal pull-up is included). 12 ALMT I Alarm Test Enable (Active-Low). This pin is cleared, forcing LOS = 0, LOC= 0, and VIO = 1 for testing without affecting data transmission (internal pull-up is included). 13 RBC I Receive Blue Control. This pin is set to insert the blue signal (AIS) on the receive side (internal pull-down is included). 14 TBC I Transmit Blue Control. This pin is set to insert the blue signal (AIS) on the transmit side. This control has priority over a loopback 2 if both are operated (internal pull-down is included). 15 BClk I Blue Clock. Blue clock (AIS) input signal (2.048MHz 80ppm). This clock can be independent of the transmit clock. 16 SR/DR I Single-Rail (Active-Low)/Dual-Rail Operation. If SR/DR = 0 (internal pull-down is included), single-rail operation is selected; if SR/DR = 1, dual-rail operation is selected (see Tables 3-5). 17 FLM I Framer Logic Mode. If FLM = 0 (internal pull-down is included), logic mode 1 operation occurs. If FLM = 1, logic mode 2 operation occurs (see Tables 3-5). 18 NC 19 GNDD 20 R2 21 VDDD 22 T2 O Transmit Bipolar Tip. Positive bipolar transmit output. 23 ZS I Impedance Select. This pin is cleared for 75Ω coaxial cable operation and set for 120Ω shielded twisted-pair operation (internal pull-down is included) No Connection. Test pin for manufacturing purposes only. This pin must be left floating or tied to GNDD. Digital Ground. O Transmit Bipolar Ring. Negative bipolar transmit output. 5V Digital Supply (10%). 24 VDDA 5V Analog Supply (10%). 25 GNDA Analog Ground. 26 SD I Shutdown Enable. If this pin is high, a loss-of-signal detection (LOS= 0) forces LOC low and causes the following (see Table 2): For single-rail operation: RClk high, RDATA low. For dual-rail, logic mode 1 operation RClk high, RPDATA and RNDATA low. For dual-rail, logic mode 2 operation: RClk low, RPDATA and RNDATA high (internal pulldown is included). 27 R1 I Receive Bipolar Ring. Negative bipolar receive input 28 T1 I Receive Bipolar Tip. Positive bipolar receive input. Rev. 1.01 4 XR-T7288 ELECTRICAL CHARACTERISTICS Test Conditions: TA = -40°C to +85°C; VDD = 5V 10% Symbol Parameter Min. Typ. Max. Unit Conditions Logic Interface Electrical Characteristics Input Voltage VIL Low GNDD 0.8 V VIH High 2.0 VDDD V Output Voltage1 VOL Low GNDD 0.4 V 2.0mA Sink VOH High 2.4 VDDD V 80µA Source CI Input Capacitance 20 pF CL Load Capacitance 40 pF Transmitter Specifications Output Pulse Amplitude 75Ω (ZS = 0) 2.14 2.37 2.60 V 120Ω (ZS = 1) 2.70 3.00 3.30 V Pulse Width (50%) 219 244 269 ns 5 % 102 %2 Positive/Negative Pulse Imbalance Zero Level Output Transformer Turns Ratio 1:1.33 1:1.36 1:1.39 Receiver Specifications Receiver Sensitivity3 0.7 4.2 Vp 7 dB 6 dB Allowed Cable Loss at BER 10-9 No Interference 10 Interfering PBRS, 18dB Below Transmitted PBRS PLL4 3dB Bandwidth 28 Peaking 0.24 ICO Free-running Frequency Error kHz 0.5 dB 7 % Notes 1 Digital outputs drive purely capacitive loads to full output levels (V D, GNDD) DD 2 Percentage of the nominal pulse amplitude. 3 Measured at T1, R1 (V peak-to-zero, GND reference) 4 Transfer characteristics (1/4 input) 5 All measurements are with a matched-impedance transmit interface (see Figure 3. and Figure 4.) and with V DD or GND applied to digital input leads. Internal pull-up devices are provided on the following input leads: LP1, LP2, LP3 and ALMT. Internal pull-down devices are provided on the following leads: SD, RBC, HDB3/TNDATA, TBC, SR/DR, FLM, and ZS. The internal pull-up or pull-down devices require the input to source or sink to be no more than 20µA. Specifications are subject to change without notice Rev. 1.01 5 XR-T7288 ELECTRICAL CHARACTERISTICS (CONT’D) Symbol Parameter Min. Typ. Max. 1:1.9 1:2.0 1:2.1 Unit Conditions Receiver Specifications (Cont’d) Input Transformer Turns Ratio Input Resistance, RI or TI, Each Input to Ground 0.9 3.0 kΩ Jitter (20Hz-100kHz) Power Receive Plus Transmit Jitter at T2/R2 0.06 0.09 U.I. peak-to-peak Transmit Jitter at T2/R2 0.012 0.04 U.I. peak-to-peak Dissipation5 (TA=-40°C to +85°C, VDD=5.0 V 10%) Power Dissipation Pdis 75 (ZS = 0) 190 290 mW All 1s transmit and Pdis 120 (ZS = 1) 170 260 mW receive data, VDD=5.5V Power Dissipation: Pdis 75 (ZS = 0) 170 mW All 1s transmit and Pdis 120 (ZS = 1) 150 mW receive data, VDD=5.0V Power Dissipation: Pdis 75 (ZS = 0) 108 mW PRBS (50% 1s) transmit and Pdis 120 (ZS = 1) 100 mW receive data, VDD=5.0V Notes 1 Digital outputs drive purely capacitive loads to full output levels (V D, GNDD) DD 2 Percentage of the nominal pulse amplitude. 3 Measured at T1, R1 (V peak-to-zero, GND reference) 4 Transfer characteristics (1/4 input) 5 All measurements are with a matched-impedance transmit interface (see Figure 3. and Figure 4.) and with V DD or GND applied to digital input leads. Internal pull-up devices are provided on the following input leads: LP1, LP2, LP3 and ALMT. Internal pull-down devices are provided on the following leads: SD, RBC, HDB3/TNDATA, TBC, SR/DR, FLM, and ZS. The internal pull-up or pull-down devices require the input to source or sink to be no more than 20µA. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS DC Supply Voltage (VDD) . . . . . . . . . . . -0.5V to +6.5V Power Dissipation (Pdis) . . . . . . . . . . . . . . . . . 500mW Storage Temperature (Tstg) . . . . . . . -65°C to +125°C Maximum Voltage (any pin) with Respect to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Minimum Voltage (any pin) with Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V Maximum Allowable Voltages (T1, R1) with Respect to GND . . . . . . -5.0V to 5.0V Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure to Absolute Maximum Ratings for extended periods can adversely affect device reliability. pin assignment ordering information Rev. 1.01 6 XR-T7288 Q2E 04 RP5H 330 11 10 8 9 L5 Q2F 13 L1 VIO/RDATA VCC B4 1 2 RPDATA RClk RNDATA J8 2 B6 1 2 J6 2 B5 1 2 J7 1 RPOS 2 3 RRPOS 15 1 RClk 4 3 RRClk 13 1 RNEG 3 3 RRNEG 14 2 VCC RRPOS XTAL2 Q3 RClk 2188 (Jitter Attenuator) RRClk XTAL1 RNEG XTAL GND RST BDS TEST DJA 16 1 6 B8 1 6 5 4 3 HDB3 RPDATA RClk RNDATA TNDATA 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 9 10 11 12 13 14 XTAL1 8.192MHz 9 7 LP1 LP3 LP3 ALMT RBC TBC 1 1 1 1 1 1 5 4 3 2 1 0 9 ON R1 1111111 65432109 2 1 10K RP4A LOC LOS B7 1 2 BLUE CLOCK T2 2 B9 1 TClk TClk 7 TClk R2 22 20 VCC 2 BClk 15 EXT 1 J5 BClk VCCA VCCD R17 75 GNDA GNDD NC RP5C 330 3 14 L3 Q2B 3 RP5E 330 5 12 L2 04 4 LOC LOS R8 270 1 TWP 3 COAX R2 866 T2 PE-65415 B3 1 R16 200 RXIN 2 27 3 B1 1 2 TPDATA Q2A 04 2 1 28 2 TPDATA 8 J4 ON 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 12345678 2 3 4 5 6 7 8 RPDATA BL 10 VCC RST BDS TEST DJA SRDR ZS SD FLM 2 Q1 XR-T7288 RP2B 10K XTALOUT SW2 16 T1 RP5G 7 12 TP1 12 5 6 1 SR/DR 23 ZS 26 SD 17 FLM LOC LOS 04 10 SW1 2 VCC BL 11 1 RP2A 10K TNDATA RPOS RRNEG 8 VCC BL J3 R5 270 1 TWP 3 COAX R3 866 R13 26.1 COAX 3 R14 15.4 TWP 1 R11 26.1 COAX 3 R15 15.4 TWP 1 2:1 T1 PE-64937 J2 1 2 C2 0.1uF 25 19 18 E1 22uF C1 0.1uF J1 2 1:1.36 RP5A 330 1 16 L4 Rev. 1.01 7 P1 VCC PWR 1 Figure 2. Suggested Application Circuit TXOUT 2 1 24 21 B2 P2 GND XR-T7288 SYSTEM DESCRIPTION converter, receive converter, and logic. The transmit and receive converters process information signals through the device in the transmit and receive directions, respectively; the logic is the control and status interface for the device. Figure 3. and Figure 4. include a matched-impedance transmit-interface section in order to match the output impedance of the transmitter to the line. See Table 1 for the G.703/CH-PTT specifications for transmit-interface return loss. The XR-T7288 device is a fully integrated line interface that requires only two transformers, three input termination resistors, and two output impedance-matching resistors to provide a bidirectional line interface between a 2.048 Mbits/s CEPT datalink and terminal equipment. Typical application diagrams are shown in Figure 3. and Figure 4. for 75Ω coaxial cable and 120Ω shielded twisted-pair operation, respectively. The circuit is divided into three main blocks: transmit ÎÎÎ Î RECEIVE DATA ÎÎ ÎÎ ÎÎ ÎÎ T1 RDATA/RPDATA 270Ω 200Ω 270Ω 1:2 VIO/RNDATA Receive Input RClk R1 VDDD +5V VDDA Transmitted Data ÎÎ ÎÎ ÎÎÎ ÎÎ Î ÎÎ ÎÎ ÎÎÎ ÎÎ Î Î 75Ω XR-T7288 CEPT1 Line Interface Matched-impedance Transmit Interface ÎÎ ÎÎ ÎÎ ZS GNDD GNDA 15.4Ω Load 1.36:1 T2 Transmit Output TDATA/TPDATA HDB3/TNDATA TClk R2 15.4Ω Figure 3. Typical Application Diagram for Coaxial Environment Rev. 1.01 8 1µF XR-T7288 RECEIVE DATA ÎÎ ÎÎ ÎÎ 200Ω 1:2 ÎÎ ÎÎ T1 RDATA/RPDATA 866Ω VIO/RNDATA Receive Input RClk 866Ω R1 VDDD +5V VDDA Transmitted Data XR-T7288 CEPT1 Line Interface Matched-impedance Transmit Interface ÎÎ ÎÎ ÎÎ 1µF ZS GNDD GNDA 26.1Ω ÎÎ ÎÎ 120Ω Load 1.36:1 T2 Transmit Output TDATA/TPDATA HDB3/TNDATA TClk R2 26.1Ω Figure 4. Typical Application Diagram for Shielded Twisted-Pair Environment Interface Min Typ Max Units 51 kHz to 102 kHz 8 28 dB 102 kHz to 2.048 MHz 14 26 dB 2.048 MHz to 3.072 MHz 10 24 dB 51 kHz to 102 kHz 12 32 dB 102 kHz to 2.048 MHz 18 31 dB 2.048 MHz to 3.072 MHz 14 30 dB Transmit Receive Table 1. Return Loss (resistor tolerance: 1% on transmit side, 2% on receive side) Rev. 1.01 9 XR-T7288 Transmit Converter The positive and negative pulses meet CCITT specification G.703 template requirements. The normalized pulse template is shown in Figure 5. A block diagram of the analog circuitry is shown in Figure 6. The line-interface transmission format is return-to-zero, bipolar alternate mark inversion (AMI), requiring transmission and sensing of alternately positive and negative pulses. The transmit converter accepts unipolar data and clock and converts the signal to a balanced bipolar data signal. Binary 1s in the data stream become pulses of alternating polarity transmitted between the two output rails, T2 and R2. Binary 0s are transmitted as null pulses. The clock multiplier shown in Figure 6. uses a phase-locked loop (PLL) to produce the high-speed timing waveforms needed to produce a well-controlled pulse width. The clock multiplier also eliminates the need for the tightly.controlled transmit clock duty cycle usually required in discrete implementations. Transmitter specifications are shown in the Electrical Characteristics table. The output pulse waveform is nominally rectangular. The pulses are produced by a high-speed D/A converter and are driven onto the line by low-impedance output buffers. 269ns (244 + 25) Nominal pulse 20% 10% V = 100% 194ns (244 - 50) 10% 20% 50% 244ns 219ns (244 - 25) 10% 10% 0% 10% 20% 488ns (244 + 244) Note: V corresponds to the nominal peak value Figure 5. CCITT G.703 Pulse Template Rev. 1.01 10 10% XR-T7288 LP1 LOS Digital Signal Detector Analog Signal Detector PDATA Receiver Analog Input T1 R1 SD NDATA RP M U X Data/Clock Recovery RDATA/RPDATA VIO/RNDATA RClk RN RClk Transmit and Receive Logic TP TN T2 R2 Transmit Output Drivers High Speed D/A 2 Clock Multiplier TClk TDATA/TPDATA HDB3/TNDATA TClk Timing Signals ZS Figure 6. XR-T7288 Analog Block Diagram RECEIVE CONVERTER The receive converter accepts bipolar input signals (T1, R1), with a maximum of 6dB loss at 1024kHz, through the interconnection cable. The received signal is rectified while the amplitude and rise time are restored. These input signals are peak-detected and sliced by the receiver front end, producing the digital signals PDATA and NDATA (see Figure 6.) Receive decision levels are automatically adjusted to be 50% of peak-to-zero signal levels. The timing is extracted by means of PLL circuitry that locks an internal, free-running, current-controlled oscillator (ICO) to the 2.048MHz component. For robust operation, the PLL is augmented with a frequency-acquisition capability. This feature detects if the recovered PLL clock (RClk) deviates by more than +1.7/-1.6% in frequency from a 2.048 MHz reference clock, which must be provided at BClk. If the RClk frequency is not within the prescribed range of the BClk frequency, the XR-T7288 device enters a training mode in which receive input data is disconnected from the PLL, and the RClk frequency is steered to equal the BClk frequency. After frequency acquisition is completed, the PLL reconnects to receive input data to acquire proper phase-lock and timing of RClk with respect to the incoming T1, R1 data. Valid data is available when proper phase-lock has been achieved. The PLL employs a 3-state phase detector and a low-voltage/temperature coefficient ICO. The ICO free-running frequency is trimmed to within 2.5% of the data rate at wafer probe, with VDD = 5.0 V and TA = 25°C. For all operating conditions (see Operating Conditions section), the free-running oscillator frequency deviates from the data rate by less than 7%, alleviating the problem of harmonic lock. The frequency acquisition circuitry is intended to avoid improper harmonic locking during start-up situations, such as power-up or data interruption. Once the XR-T7288 device is phase-locked to data, the frequency-acquisition mode will not be activated. Rev. 1.01 11 XR-T7288 A continuous (i.e., ungapped, unswitched) 2.048 MHz reference clock must be present at BClk to enable the frequency-acquisition circuitry. However, the receive PLL will operate even in the absence of a 2.048 MHz clock at BClk. The 2.048 MHz clock at TClk can also be used to provide the 2.048 MHz reference at BClk. Hysteresis (140 mV, typical) is provided in the analog detector to eliminate LOS chattering. The digital signal detector counts 0s in the recovered data. If more than 32 consecutive 0s occur, the digital signal detector becomes active. In normal operation, the detector outputs are ORed together to form LOS; however, in loopback 1, only the digital signal detector is used to monitor the looped signal. Table 2 describes the operation of the shutdown, LOS, and LOC functions in normal operation and in loopback 1. Because the clock output of the receive converter is derived from the ICO, a free-running clock can be present at the output of the receive converter without data being present at the input. A shutdown pin (SD) is provided to block this clock, if desired, to eliminate the free-running clock upon loss of the input signal. The PLL is designed to accommodate large amounts of input jitter with high power supply rejection for operation in noisy environments. Low jitter sensitivity to power supply noise allows compact line-card layouts that employ many line interfaces on one board. The minimum input jitter tolerance, as specified in CCITT specification G.823, and the measured XR-T7288 device jitter tolerance are shown in Figure 7. Receiver specifications are shown on page 4. The XR-T7288 device satisfies the CCITT jitter transfer function requirement of recommendations G.735 G.739 (see Figure 8.) Both analog and digital methods of loss of signal detection are used in the XR-T7288 device. The analog signal detector shown in Figure 6. uses the output of the receiver peak detector to determine if a signal is present at T1 and R1. If the input amplitude drops below 0.25 V, typical, the analog detector output becomes active. Analog loss-of-signal is registered, at most, several milliseconds after a drop in signal level, depending on a variety of factors, such as initial signal amplitude. Inputs Outputs Receive Side Input Signal at T1, R1 Loopback 1 Signal LOS LOC Receive Data1 1 Active x 1 1 1 No Signal x 0 1 1 Active x 1 1 No Signal x 0 1 x Active 1 1 LP1 SD ALMT 1 0 1 0 1 1 1 1 0 0 RClk1 Active LOS Detectors Normal Normal Analog & Digital Low 2 Free-running ICO 2 Analog & Digital 1 Normal Normal Analog & Digital 0 Low 3 High Analog & Digital Normal Loopback Normal Loopback Low 4 Free-running ICO 4 Digital Only 0 0 1 x No Signal 0 1 0 1 1 x Active 1 1 0 1 1 x No Signal 0 0 Low High Digital Only x x 0 x x 0 0 Unaffected Unaffected x Normal Loopback Normal Loopback Digital Only Digital Only Notes: 1 These values apply for single-rail or dual-rail/logic mode 1. For dual-rail/logic mode 2, all logic-level outputs except for looped back data are the inverse of that shown above. 2 Activated by analog loss-of-signal (LOS) detection. 3 Digital LOS detection forces receive data low . Analog LOS detection merely forces receive data to stop transitions; receive data will be forced either high or low with analog LOS detection. 4 All-0s looped back data, no HDB3 operation. Sufficiently sparse looped back data (not HDB3 encoded) also causes the receive ICO to free run; therefore, properly timed loopback data is not guaranteed. Table 2. Shutdown LOS and LOC Truth~Table x = don’t care. Rev. 1.01 12 XR-T7288 (1, 2.9) 10 G.823 Specification Input Jitter Amplitude (U.I. Peak-to-Peak) XR-T7288 Measured Performance BER = 1E-6 (20, 1.5) (2.4K, 1.5) ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ 1 Jitter Jitter Jitter Jitter Frequency Amplitude Frequency Amplitude (kHz) (U.I. pp) (kHz) (U.I. pp) 4 8 10 15 20 30 0.1 1 2.00 1.06 0.87 0.65 0.52 0.46 10 40 50 60 70 100 (18k, 0.2) (100k, 0.2) 0.45 0.44 0.43 0.44 0.51 100 1k 10k 100k Jitter Frequency (Hz) Note: Measurement conditions random data, TA = 25°C, VDD = 5V, 6dB cable loss, BClk clock present Figure 7. Random Input Data Jitter Tolerance (HDB3 Encoded) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ G.735–G.739 Specification (36K, 0.5dB) 0 20 Log (JOUT/JIN) (dB) –20dB/Decade -5 XR-T7288 Measured Performance (100K, –8.4dB) -10 -15 -20 0.1 1 10 36 Frequency (kHz) Note: Equivalent binary content of input signal: 1000. Jitter input amplitude = 0.1 U.I. peak-to-peak. Figure 8. Receive Jitter Transfer Function Rev. 1.01 13 100 XR-T7288 Digital Logic In the dual-rail mode (SR/DR = 1), the XR-T7288 receiver converts bipolar input signals (T1, R1) to p-rail and n-rail, nonreturn-to-zero output data on pins RPDATA and RNDATA, respectively. The XR-T7288 transmitter converts non-return-to-zero p-rail and n-rail input data on pins TPDATA and TNDATA, respectively, to a balanced bipolar data signal on pins T2 and R2. In the dual-rail mode, HDB3 encoding/decoding and bipolar violation output functions are unavailable. The logic provides alarms, optional HDB3 coding, blue signal (AIS) insertion circuits, and maintenance loopbacks. It also optionally performs dual-rail to single-rail conversion of the data and provides an alternate logic polarity (logic mode 2) in dual-rail mode for receive clock and receive and transmit data. Single-Rail/Dual-Rail Interface and Alternate Logic Mode The XR-T7288 device supports either single-rail or dual-rail operation by setting the control pin SR/DR. In the single-rail mode (SR/DR = 0), the XR-T7288 receiver converts bipolar input signals (T1, R1) to a unipolar output signal on RDATA. The XR-T7288 transmitter converts a unipolar input signal on TDATA to a balanced bipolar data signal on pins T2 and R2. If desired, the HDB3 control pin can be used to set HDB3 encoding/decoding. Violation information is available on output pin VIO. In the dual-rail mode, an alternate-logic polarity mode is available via control pin FLM. If FLM = 1, the XR-T7288 device operates in logic mode 2; RClk is inverted with respect to logic mode 1, and input and output data (TPDATA, TNDATA, RPDATA, and RNDATA) are active-low (see Figures 10-13). Internal pull-downs on signals SR/DR and FLM set default operation to single-rail, logic mode 1 (see Table 3) FLM SR/DR Single-/Dual-Rail Logic Mode 01 01 Single 1 0 1 Dual 1 1 0 X2 X2 1 1 Dual 2 Notes: 1 Default operation (identical with LC1135B) if both pins are unconnected. 2X = illegal option Table 3. Rail Interface and Logic Mode Options Pin Name Function 3 HDB3/TNDAT HDB3 Enable 4 VIO/RNDATA VIO Violation 6 RDATA/RPDATA RDATA Receive Data 8 TDATA/TPDATA TDATA Transmit Data Table 4. Single-Rail Operation (Default State) SR/DR = 0 (or left unconnected internal pull-down circuitry). Pin Name Function 3 HDB3/TNDATA N-rail Transmit Input Data 4 VIO/RNDATA N-rail Receive Output Data 6 RDATA/RPDATA P-rail Receive Output Data 8 TDATA/TPDATA P-rail Transmit Input Data Table 5. Dual-Rail Operation SR/DR = 1 Rev. 1.01 14 XR-T7288 Blue Signal (AIS) Generators Alarms There are two blue signal (AIS) generators in this device. One (RBC = 1) substitutes an all-1s signal on RDATA output (SR/DR = 0) or RPDATA and RNDATA (SR/DR = 1) toward the terminal equipment. The other (TBC = 1) substitutes a bipolar, all-1s signal for the bipolar data out of the transmit converter which can be used to keep line repeaters active. An independent loss-of-clock (LOC) output is provided so that loss of clock is detected when the shutdown option is in effect. LOS and LOC can be wire-ORed to produce a single alarm. A bipolar violation output is included if HDB3 = 0, giving an alarm (VIO) each time a violation occurs (two or more successive 1s on a rail). The violation alarm output is held in a latch for one cycle of the internal clock (RClk). In the HDB3 mode, HDB3 code violations are detected and an alarm is produced. Loopback Paths The XR-T7288 device has three independent loopback paths that are activated by clearing the respective control inputs, LP1, LP2 or LP3. Loopback 1 bridges the data stream from the transmit converter (transmit converter included) to the input of the receive converter. This maintenance loop includes most of the internal circuitry. An alarm test pin (ALMT) is provided to test the alarm outputs, LOS, LOC and VIO. Clearing this pin forces the alarm outputs to the alarm state without affecting data transmission. Loopback 2 provides a loopback of data and recovered clock from the bipolar inputs (T1, R1) to the bipolar outputs of the transmit converter (T2, R2). The receive front end, receive PLL, and transmit driver circuitry are all exercised. The loop can be used to isolate failures between systems. TBC = 1 overrides this function. HDB3 Option The XR-T7288 device contains an HDB3 encoder and decoder (for single-rail mode only, i.e., SD/DR = 0) that can be selected by setting the HDB3 pin. This allows the encoder to substitute a zero-substitution code for four consecutive 0s detected in the data stream, as illustrated in Table 6 A “V” represents a violation of the HDB3 code, and a “B” represents a bipolar pulse of correct polarity. The decoder detects the zero-substitution code and reinserts four 0s in the data stream. Loopback 3 loops the data stream as in loopback 1 but bypasses the transmit and receive converters. The blue signal (AIS) can be transmitted to the line when in this loopback. Loopbacks 2 and 3 can be operated simultaneously to provide transmission loops in both directions. Case 1: Preceding mark has a polarity opposite the polarity of the preceding violation and is not a violation itself. Current Pulses With all other pins grounded, current pulses of maximum value and time widths are allowed on the T1/R1 and T2/R2 pins without damaging the device, as shown in Table 7. Also, to help ensure long-term reliability, the average value of a current-pulse train is specified. Case 2: Preceding mark has a polarity the same as the polarity of the preceding violation or is a violation itself. Case 1 Case 2 Before HDB3 0000 0000 After HDB3 000V B00V Table 6. HDB3 Substitution Code Pin Max Value Width Avg Value T1, R1 20 mA 1µs to 1s 6 mA T2, R2 200 mA 1µs to 1s 40 mA Table 7. Maximum Allowable Current Rev. 1.01 15 XR-T7288 Handling Precautions capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. EXAR employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500, HBM ESD Threshold Device Voltage XR-T7288 >2500 V Table 8. ÎÎÎÎÎ Î Î ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ RL1 R1 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ P1 Regulated High Voltage Power Supply C1 R2 For Device Testing ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎ Î Î ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ SOCKET Notes: P10kV to 5kV DC power supply. R1At least 10 MΩ, high-voltage, 1W carbon composition. RL1High-voltage (5 kV) relay of a bounceless type (mercury-wetted or equivalent). C1100pF, 5kV capacitor. R21500 Ω ±5%, 1W carbon composition < 1pF shunt capacitance. Figure 9. Circuit Schematic of Human-Body ESD Simulator Rev. 1.01 16 XR-T7288 Timing Characteristics All duty–cycle and timing relationships are in reference to a TTL, 1.4V threshold level. Loss–of–Clock Indication Timing The clock must be absent 6.4 s to guarantee a loss–of–clock indication.However, a loss–of–clock indication can occur if the clock is absent for as little as 1.95µs, depending on the timing relationship of the interruption with respect to the timing cycle. The returning clock must be present 3.91µs to guarantee a normal condition on the loss–of–clock pin (LOC). However, the loss–of–clock indication can return to normal immediately, depending on the timing relationship of the signal return with respect to the timing cycle. TA = –40°C to ±85°C; VDD = 5 V±10%; load capacitance = 40 pF. Symbol Description Min tTCLTCL TCLK Clock Period tTCHTCL TCLK Duty Cycle tTDVTCL tTCLTDV Data Setup Time, TDATA2 Data Hold Time, TCLK to to TCLK Typ Max Unit 1 488 1 ns 40 50 60 % 50 TDATA2 ns 40 ns tr Clock Rise Time (10% 90%) 40 ns tf Clock Fall Time (10% 90%) 40 ns 60 % tRCLRCL tRCHRDV tRDVRCH tRCLRDV RCLK Duty Cycle 40 171 ns RCLK3 131 ns Data Hold Time, RCLK to RDATA, Data Setup Time, RDATA, VIO to 50 VIO3 Propagation Delay, RCLK to RDATA, VIO3 Table 9. Clock Timing Relationships Notes 1 A tolerance of 80 ppm. 2 DATA for single–rail mode; TPDATA and TNDATA for dual–rail mode. 3 RDATA and VIO for single–rail mode; RPDATA and RNDATA for dual–rail mode. Rev. 1.01 17 40 ns XR-T7288 TIMING DIAGRAMS (Single-Rail or Dual-Rail, Logic Mode 1) tr tf tr tf tTCLTCL TClk (TC) TDATA or TPDATA TNDATA (TD) tTDVTCL tTCLTDV Figure 10. Transmit Timing tRCLRDV RClk (RC) tRDVRCH RDATA VIO or RPDATA RNDATA (RD) tRCHRDV Figure 11. Receive Timing Rev. 1.01 18 XR-T7288 TIMING DIAGRAMS (Dual-Rail, Logic Mode 2) tr tf tTCLTCL TClk (TC) TPDATA TNDATA (TD) ACTIVE LOW tTDVTCL tTCLTDV Figure 12. Transmit Timing tRCLRDV tr tf RClk (RC) tRDVRCH RDATA VIO or RPDATA RNDATA (RD) tRCHRDV Figure 13. Receive Timing Rev. 1.01 19 ÎÎ ÎÎ ÎÎ ÎÎ ACTIVE LOW XR-T7288 TRANSFORMER REQUIREMENTS Turns Ratio Line Impedance RLOAD Turns Ratio Line Impedance ROUT 1:1 75Ω 75Ω 1:1 75Ω 68Ω 1:1 120Ω 120Ω 1:1.265 120Ω 68Ω 1:1 100Ω 100Ω 1:1.265 100Ω 62Ω Table 10. Input Transformer Requirements Table 11. Output Transformer Requirements Magnetic Supplier Information: Transpower Technologies, Inc. 24 Highway 28, Suite 202 Crystal Bay, NV 89402–0187 Tel. (702) 831–0140 Fax. (702) 831–3521 Pulse Telecom Product Group P.O. Box 12235 San Diego, CA 92112 Tel. (619) 674-8100 Fax. (619) 674-8262 Rev. 1.01 20 XR-T7288 28 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) Rev. 1.00 28 15 1 14 E1 E D Seating Plane A2 A L A1 B B1 e INCHES SYMBOL eA eB MILLIMETERS MIN MAX MIN A 0.145 0.210 3.68 5.33 A1 0.015 0.070 0.51 1.78 MAX A2 0.115 0.195 2.92 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 1.345 1.400 34.16 35.56 E 0.300 0.325 7.62 8.26 E1 0.265 0.310 7.11 7.49 e eA 0.100 BSC 0.300 BSC 2.54 BSC 7.62 BSC eB 0.310 0.430 7.87 10.92 L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Note: The control dimension is the inch column Rev. 1.01 21 α C XR-T7288 28 LEAD SMALL OUTLINE J LEAD (300 MIL JEDEC SOJ) Rev. 1.00 D 28 15 E H 1 14 A2 A Seating Plane C B e R A1 E1 INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.145 0.200 3.60 5.08 A1 0.025 ––– 0.64 ––– A2 0.120 0.140 3.05 3.56 B 0.014 0.020 0.36 0.51 C 0.008 0.013 0.20 0.30 D 0.697 0.712 17.70 18.08 E 0.292 0.300 7.42 7.62 E1 0.262 0.272 6.65 6.91 e 0.050 BSC MAX 1.27 BSC H 0.335 0.347 8.51 8.81 R 0.030 0.040 0.76 1.02 Note: The control dimension is the inch column Rev. 1.01 22 XR-T7288 Notes Rev. 1.01 23 XR-T7288 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1992 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.01 24