l: Te ， 司 公 限 技 有 讯 科 合 市 金 圳 深 58 5 34 1 66 4 18 QQ : CAT6354 4-to-1 HDMI1.3 Retiming Switch 71 44 51 8 19 ， 廖 R CAT6354 Preliminary Datasheet General Description 71 44 51 8 19 ， 廖 R The CAT6354 is a 2nd-generation four-to-one HDMI v.1.3 retiming switch that supports a signalling rate of up to 2.25Gbps and the new Deep Color modes. A one-port SINK systems such as flat-panel TVs or LCD projectors could also easily upgrade to four-port by adding an CAT6354 at the front. By default the CAT6354 operates in hardware mode and source selection is done by controlling the pins S0 and S1. It also comes with a software mode that allows the system to control it via a two-line serial interface. The CAT6354 offers eight selectable serial programming addresses, making it the optimal choice for KVM applications. 66 4 34 1 58 5 QQ : As a retiming switch, the CAT6354 equalizes and recovers incoming TMDS data before re-transmitting them with optimal quality regardless of the incoming signal quality. The highly acclaimed equalization technology of Chip Advanced Technology provides for support of long or low-quality HDMI cables at even the highest speeds. Input terminations of the TMDS inputs and output current levels are both auto-calibrated. In addition, the input terminations are disconnectable and hence significantly lower the system power consumption in inactive modes. The CAT6354 also incorporates I2C repeater in its DDC switches, which isolates the DDC 18 capacitances of the two sides of the switch. This allows for longer cable cascading as well as 司 ， Te l: significantly eases the system design to pass Test ID 8-9: DDC/CEC Line Capacitance and Voltage of the HDMI Compliance Test. 限 公 Features 讯 科 技 有 HDMI retiming switch, providing superior performance over traditional passive switches, even better than active switches Compliant with HDMI 1.3a and DVI 1.1 standards 圳 市 金 合 Serial data rate at up to 2.25Gbps, capable of supporting the following digital video formats in Deep Color Mode at up to 36 bits (12 bits/color): DTV resolutions: 480i, 576i, 480p, 576p, 720p, 1080i to 1080p PC resolutions: VGA, SVGA, XGA, SXGA to UXGA Single 3.3V operation 深 True retiming capability allows for clean regenerated signals for transmission DDC I2C repeater isolates backend DDC capacitive loading from frontend, enhancing the DDC operation compatibility Integrated HPD switches Human Body Mode ESD protection up to ±8kV for all TMDS differential input pins The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 2/14 CAT6354 Preliminary Datasheet Disconnectable input terminations with auto-calibrated impedances Adaptive input equalization supporting long and short cables at the same time Optional software-mode operation providing flexibility 廖 R 8 possible serial programming device address, perfect for KVM applications. Auto-calibrated and programmable TMDS output current level 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， Auto-calibrated or programmable source terminations compliant with HDMI 1.3a standard, providing optimal source data eyes at high speeds High-impedance TMDS output when disabled Optional backend receiver termination detection for auto powerdown 100-Pin LQFP package The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 3/14 CAT6354 Preliminary Datasheet 83 CSDA 84 CCEC 85 CHPD 86 TXSCL 87 TXSDA 88 TXCEC 89 TXHPD 90 BSCL 91 BSDA 92 BCEC 93 BHPD 94 VSS 95 ASCL 96 ASDA 97 ACEC 98 AHPD 99 OTO 100 59 58 57 56 55 54 53 52 51 50 PCSDA 49 PCSCL 51 8 CSCL 60 71 44 82 61 QQ : NC 62 58 5 81 63 34 1 DHPD 64 CAT6354 66 4 80 65 LQFP-100 Top View 18 DCEC 66 l: 79 67 Te DSDA 68 ， 78 69 司 DSCL 70 公 77 71 限 NC 72 技 有 76 73 讯 科 OE 74 19 ， 75 廖 R Pin Diagram 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC 47 VCC 46 NC 45 NC 44 RESETB 43 TX2P 42 TX2M 41 VCC 40 TX1P 39 TX1M 38 VCC 37 TX0P 36 TX0M 35 VCC 34 TXCP 33 TXCM 32 VCC 31 S1 30 S0 29 VSS 28 PCADR2 27 PCADR1 26 PCADR0 25 Figure 1. The CAT6354 pin diagram 深 圳 市 金 合 1 48 The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 4/14 CAT6354 Preliminary Datasheet Pin Description TMDS High Speed Differential Input Pins (All these pins provide ±8kV HBM ESD Protection) Direction Description Type Pin No. 廖 R Pin Name Input Channel 2 of input port A TMDS ARX1P/M Input Channel 1 of input port A TMDS ARX0P/M Input Channel 0 of input port A TMDS ARXCP/M Input Clock channel of input port A 71 44 51 8 ARX2P/M 19 ， TMDS Input Port A TMDS Input Port B Input Channel 2 of input port B BRX1P/M Input Channel 1 of input port B BRX0P/M Input Channel 0 of input port B BRXCP/M Input Clock channel of input port B 58 5 QQ : BRX2P/M 34 1 TMDS Input Port C Input Channel 2 of input port C CRX1P/M Input Channel 1 of input port C CRX0P/M Input Channel 0 of input port C CRXCP/M Input Clock channel of input port C 21, 20 18, 17 TMDS 15, 14 TMDS 12, 11 TMDS 9, 8 TMDS 6, 5 TMDS 3, 2 TMDS 74, 73 TMDS 71, 70 TMDS 68, 67 TMDS 65, 64 TMDS 62, 61 TMDS 59, 58 TMDS 56, 55 TMDS 53, 52 Type Pin No. l: 18 66 4 CRX2P/M 24, 23 Te TMDS Input Port D Input Channel 2 of input port D DRX1P/M Input Channel 1 of input port D DRX0P/M Input Channel 0 of input port D DRXCP/M Input Clock channel of input port D 技 有 限 公 司 ， DRX2P/M 讯 科 TMDS High Speed Differential Output Pins Direction Description Output Channel 2 of output port TMDS 43, 42 Output Channel 1 of output port TMDS 40, 39 TX0P/M Output Channel 0 of output port TMDS 37, 36 TXCP/M Output Clock channel of output port TMDS 34, 33 Pin Name 深 圳 市 金 TX1P/M 合 TX2P/M The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 5/14 CAT6354 Preliminary Datasheet DDC, CEC and HPD Pins Pin Name Direction Description Type Pin No. TMDS Input Port A I/O DDC clock of input port A 5V-Tol. 96 ASDA I/O DDC data of input port A 5V-Tol. 97 ACEC I/O CEC of input port A 5V-Tol. AHPD I/O HPD output of input port A LVTTL 19 ， 廖 R ASCL 98 51 8 99 I/O DDC clock of input port B BSDA I/O DDC data of input port B BCEC I/O CEC of input port B BHPD I/O HPD output of input port B QQ : BSCL 71 44 TMDS Input Port B CSDA I/O DDC data of input port C CCEC I/O CEC of input port C CHPD I/O HPD output of input port C TMDS Input Port D I/O DDC clock of input port D DSDA I/O DDC data of input port D DCEC I/O CEC of input port D DHPD I/O HPD output of input port D 91 5V-Tol. 92 5V-Tol. 93 LVTTL 94 5V-Tol. 83 5V-Tol. 84 5V-Tol. 85 LVTTL 86 5V-Tol. 78 5V-Tol. 79 5V-Tol. 80 LVTTL 81 司 ， Te l: DSCL 34 1 DDC clock of input port C 66 4 I/O 18 CSCL 58 5 TMDS Input Port C 5V-Tol. 公 TMDS Output Port I/O DDC clock of output port 5V-Tol. 87 TXSDA I/O DDC data of output port 5V-Tol. 88 TXCEC I/O CEC of output port 5V-Tol. 89 TXHPD I/O HPD output of output port LVTTL 90 深 圳 市 金 合 讯 科 技 有 限 TXSCL The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 6/14 CAT6354 Preliminary Datasheet Other Control and Configuration Pins Pin Name Direction Description S[1:0] Input Input port select: Type Pin No. LVTTL 30, 31 廖 R "00": Input port A is selected 19 ， "01": Input port B is selected "10": Input port C is selected 51 8 "11": Input port D is selected Input Output enable. LVTTL 76 OTO Input Enable output terminations LVTTL 100 RESETB Input Reset signal for logic blocks (active-low) LVTTL 44 PCSCL Input Serial programming Clock for chip programming (5V-tolerant) Schmitt 49 PCSDA I/O Serial programming Data for chip programming (5V-tolerant) Schmitt 50 PCADR[2:0] Input Control of serial programming device address: LVTTL 28, 27, 26 34 1 "001": 0x96 66 4 "010": 0x9C "011": 0x9E 18 "100": 0xD4 "101": 0xD6 Te l: "110": 0xDC "111": 0xDE QQ : 58 5 "000": 0x94 71 44 OE 公 司 of 100kΩ) ， (default to "000": 0x94 by internal weak pulled-down resistors Could be left unconnected 45, 46, 限 NC 技 有 77, 82 讯 科 Power and Ground Pins 市 金 VCC Description Type Pin No. Power 1, 7, 13, 19, 22, 32, 35, 38, 41, 47, 54, 57, 63, 69, 75 Chip ground Ground 4, 10, 16, 25, 29, 51, 60, 66, 72, 95 深 圳 VSS Chip power supply (3.3V) 合 Pin Name The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 7/14 CAT6354 Preliminary Datasheet Functional Description 19 ， 廖 R The functional block diagram is shown in Figure 2. As can be seen, the CAT6354 takes in four ports of HDMI input signals and equalizes them. The equalized signals of the selected port are then processed to recover the clock and the data. A genuine HDMI driver is then used to clock out the "cleansed" TMDS signals, the quality of which remains optimal regardless of the incoming signal quality. ARX[2,1,0,C]P 34 1 58 5 QQ : 71 44 51 8 By default the CAT6354 works in hardware mode, in which the operation is carried out solely through controlling S0, S1 and OE pins. An optional advanced software mode is also provided and is accessible through the optional serial programming port at PCSCL and PCSDA. Eight serial programming port addresses are avaiable depending on the logic values at pins PCADR[2:0]. In the software mode, all controls are done through register setting. Once software mode is enabled, the hardware control pins S0, S1 and OE are overrided and functionless. EQ BRX[2,1,0,C]P 18 66 4 ARX[2,1,0,C]M Autocalibration EQ BRX[2,1,0,C]M CRX[2,1,0,C]P AHPD BHPD CHPD DHPD 司 RX Detect 限 EQ 技 有 深 圳 市 金 合 讯 科 ASCL/ASDA BSCL/BSDA CSCL/CSDA DSCL/DSDA TX[2,1,0,C]M OE 公 DRX[2,1,0,C]P TX[2,1,0,C]P DRV ， EQ CRX[2,1,0,C]M DRX[2,1,0,C]M Te l: 4:1 MUX Clock and Data Recovery DDC I2C Repeating Switch TXSCL/TXSDA TXHPD HPD Control TXCEC Register Block and Control Logic ACEC BCEC CCEC DCEC S0, S1 PCSCL/PCSDA Figure 2. The functional block diagram of the CAT6354 The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 8/14 CAT6354 Preliminary Datasheet The CAT6354 distinguishes itself from other active switches in that it recovers the incoming TMDS 71 44 51 8 19 ， 廖 R data before re-transmitting them. Commonly called retiming in optical communications, this techniques provides for true REPEATING performance in that the output signal quality remains constantly optimal regardless of the quality of incoming signal. This is contrary to the case in the active equalizing switches, where the ultimate performance depends more or less on the input signal quality. Hence the retiming switch is sured to deliver a performance better than the active equalizing counterparts. And of course in the CAT6354 the highly acclaimed equalization technology of Chip Advanced Technology is employed to support long cables even at 2.25Gbps. 34 1 58 5 QQ : The differential impedances of the TMDS inputs are internally auto-calibrated to 100Ω (50Ω single-endedly). With auto-calibration, the termination impedances will remain as close to 100Ω as possible in spite of process, supply voltage and temperature variations. These terminations are also disconnectable and by default will be disconnected if its associated port isn't activated. This not only saves power but also provides the mainstream HDMI sources a way to detect the status of the input of the CAT6354 in the handshaking protocol. 公 司 ， Te l: 18 66 4 A backend receiver detector is built-in to monitor the 3.3V termination of the backend HDMI receiver, which is connected to the outputs of the CAT6354. An optional auto-powerdown function, which is enabled through register setting, is provided to faithfully reflect the backend termination status to the frontend. When enabled, the CAT6354 would enter powerdown mode when it does not see a valid 3.3V termination voltage at the clock channel of the backend receiver. In addition to the benefit of powersaving, this function could also prevent those Source devices that monitor the CAT6354's input termination in its protocol design from malfunctioning. 技 有 限 Previous generations of HDMI switches use passive MOSFETs to multiplex the DDC signals, which in effect lump the parasitic capacitances of the backend DDC lines together with those of the frontend ones. Since the DDC overall capacitances impact the I2C signalling quality, the HDMI Compliance Test 深 圳 市 金 合 讯 科 Specifications has long required that the overall DDC capacitances be limited to 50pF per line (Test ID 8-9: DDC/CEC Line Capacitance and Voltage). Hence the multiplexing DDC MOSFETs of the older-generation active switches risk failing this item in SINK systems and are almost impossible to pass this item in REPEATER systems (as an external switch box). To solve this problem, the CAT6354 incorporates DDC I2C repeaters, essentially isolating the backend capacitive loading from the frontend. This would ensure not only that it is easy to pass Test ID 8-9 but also that the external KVM boxes work fine with both input and output ends connected with long cables. While almost all other HDMI signals work its way from input ports A, B, C or D to the output port, the HPD (Hot Plug Detect) signal works backward. In other words, AHPD, BHPD, CHPD and DHPD are outputs while TXHPD is input. For any input port selected, its HPD signal will reflect the logic status The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 9/14 CAT6354 Preliminary Datasheet present at the TXHPD input. For example, if port A is selected, the CAT6354 would check whether TXHPD input is at voltage levels of LVTTL-high or LVTTL-low and AHPD would be at 3.3V or 0V accordingly. Refer to Table 1 for further clarification. Note that AHPD, BHPD, CHPD and DHPD should 19 ， 廖 R each be connected to the input connector with a 1kΩ resistor in series. This is to comply with Test ID 8-11: HPD Output Resistance of the HDMI Compliance Test. Hardware Mode (Default) Source Selected TXSCL/TXSDA AHPD BHPD CHPD DHPD 0 0 Port A ASCL/ASDA TXHPD 0 0 0 0 1 Port B BSCL/BSDA 0 TXHPD 0 0 1 0 Port C CSCL/CSDA 0 0 TXHPD 0 1 1 Port D DSCL/DSDA 0 0 0 TXHPD 34 1 QQ : S1 58 5 S0 71 44 51 8 By default the CAT6354 works in hardware mode. In this mode the source selection is done by controlling S0 and S1. Refer to Table 1 for source selection lookup. 66 4 Table 1. Source selection lookup table in hardware mode 公 司 ， Te l: 18 In hardware mode, only the selected input port will present 50Ω terminations to VCC to the Source. The terminations of the unselected ports are disconnected to save power and prevent malfunctions. Note that most HDMI Sources (e.g. DVD players, settop boxes) detect whether the Sink terminations are present in addition to checking HPD status. If the terminations remain intact even when its port isn't selected, it could lead to malfunctioning of the Sources. 讯 科 技 有 限 Note that the pins PCSCL and PCSDA are better left unconnected when operated in hardware mode, as unexpected data activities on these two pins might inadvertently enable the software mode and render the hardware control pins functionless. Software Mode 深 圳 市 金 合 In addition to the hardware mode, the CAT6354 also provides a software mode, which is enabled through writing bit 7 of Register 0x06 to '1'. In software mode, all controls of the CAT6354 are done through register setting, including source selection and output enable (0x06 bit 5). The hardware control pins S0, S1 and OE would be functionless once software mode is enabled. Eight different serial programming port addresses are available through configuring PCADR[2:0] (pins 28, 27 and 26). These three pins, when left unconnected, are internally weak-pulled down to "000", giving an serial programming device address of 0x94. Refer to Pin Description for the complete address mapping. The maximum operation frequency of the PCSCL- PCSDA serial programming port The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 10/14 CAT6354 Preliminary Datasheet is 100kHz. Electrical Specifications Symbol Parameter Min. Max Unit VCC Supply voltage -0.3 4.0 VI Input voltage -0.3 VCC+0.3 V VO Output voltage -0.3 VCC+0.3 V VIDDC DDC control pins input voltage -0.3 6.0 V TJ Junction Temperature 125 °C TSTG Storage Temperature 150 °C ESD_HB Human body mode ARXs, BRXs, CRXs 8000 ESD sensitivity All other pins 2000 71 44 51 8 19 ， Typ 廖 R Absolute Maximum Ratings V QQ : -65 V 66 4 34 1 58 5 ESD_MM Machine mode ESD sensitivity 200 V Notes: 1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device. 2. Refer to Functional Operation Conditions for normal operation. 18 Functional Operation Conditions Parameter VCC Supply voltage1 TA Ambient temperature Θja Junction to ambient thermal resistance Min. Typ Max Unit 3.135 3.3 3.465 V 0 25 70 °C 40 °C/W 1560 mV 3.465 V ， Te l: Symbol 司 TMDS Differential Pins TMDS differential input swing (peak-to-peak) VTERM TMDS output termination voltage1 3.135 Tbit Average bit time of the TMDS data stream 0.444 40 ns Rbit Signaling rate of the serial TMDS data stream 250 2250 Mbps 150 3.3 讯 科 技 有 限 公 VIDIFF DDC I/O Pins (ASCL/ASDA, BSCL/BSDA, CSCL/CSDA and TXSCL/TXSDA) 深 圳 市 金 合 VIDDC DDC input voltage 0 5.5 V Notes: 1. This is mandated by the HDMI Specifications v1.3 as the supply voltage at pin VCC is also the HDMI termination voltage. The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 11/14 CAT6354 Preliminary Datasheet DC Electrical Specification Under functional operation conditions Symbol Parameter Conditions Min. Typ Max Unit 3 TMDS output low voltage VCC-10 VCC+10 VCC=VTERM=3.3V VCC-700 VCC-400 400 600 mV 10 μA 3 TMDS output single-ended swing IOFF Single-ended standby output current3 VOUT=0 51 8 Vswing Logic I/O Pins (LVTTL and Schmitt) VIL Input low voltage1 2.0 VT Switching threshold VOL Output low voltage1 1 1 VOH Output high voltage VT- Schmitt trigger negative going IOL=2~16mA QQ : Input high voltage1 IOH=-2~-16mA 2.4 58 5 VIH Schmitt trigger positive going threshold 18 voltage1 Input leakage current1 IIN Tri-state output leakage current IOL Serial programming output sink Te IOZ l: 1 2 mV 0.8 V V 0.4 V V 1.1 V 2.0 V VIN=5.5V or 0 ±5 μA VIN=5.5V or 0 ±10 μA VOUT=0.2V 4 16 mA ， current mV V 1.5 1.6 66 4 VT+ 34 1 threshold voltage1 0.8 71 44 VOLTMDS RLOAD=50Ω 19 ， TMDS output high voltage3 VOHTMDS 廖 R TMDS Differential Output Pins (TX2P/M, TX1P/M, TX0P/M, TXCP/M) 深 圳 市 金 合 讯 科 技 有 限 公 司 Notes: 1. Guaranteed by I/O design. 2. The serial programming output ports are not real open-drain drivers. Sink current is guaranteed by I/O design under the condition of driving the output pin with 0.2V. In a real serial programming environment, multiple devices and pull-up resistors could be present on the same bus, rendering the effective pull-up resistance much lower than that specified by the I2C Standard. When set at maximum current, the serial programming output ports of CAT6354 are capable of pulling down an effective pull-up resistance as low as 500Ω connected to 5V termination voltage to the standard I2C VIL. When experiencing insufficient low level problem, try setting the current level to higher than default. Refer to the CAT6354 Register Table for proper register setting. 3. Limits defined by HDMI 1.3a standard The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 12/14 CAT6354 Preliminary Datasheet 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R 100-pin LQFP Package Dimensions Figure2. Package dimensions of LQFP-100 Notes: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 do include mold mismatch and are determined at datum plane. 2. Dimension b does not include dambar protrusion. The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 13/14 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R CAT6354 Preliminary Datasheet 限 公 司 ， Te l: HEADQUARTERS: 3F, No.1, Jin-Shan 8th St., Hsin-Chu City 300, Taiwan (R.O.C.) Tel: +886-3-666-8301 Fax: +886-3-666-8630 Website: http://www.chipadvanced.com 合 讯 科 技 有 TAIPEI OFFICE: 4F, No.112, Jhouzih St., Neihu District, Taipei City 114, Taiwan (R.O.C.) Tel: +886-2-87516119 Fax: +886-2-87516359 深 圳 市 金 Information furnished is believed to be accurate and reliable. However, CAT Inc. assumes no responsibility for the consequences for use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of CAT Inc. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information if previously supplied. CAT Inc. products are not authorized for use as critical components in life support devices or systems without the express written approval of CAT Inc. The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Jun-2007 Rev:0.8 14/14