廖 R 19 ， 51 8 71 44 58 5 QQ : IT6633E-P 34 1 3-to-1 HDMI 1.3 Active Switch with EDID RAM ITE TECH. INC. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 Preliminary Datasheet www.ite.com.tw Nov-2009 Rev:0.6 1/11 IT6633 General Description 51 8 19 ， 廖 R The IT6633 is a three-to-one HDMI v.1.3 active switch that supports a signalling rate of up to 2.25Gbps and the new Deep Color modes. A one-port SINK systems such as flat-panel TVs or LCD projectors could also easily upgrade to three-port by adding an IT6633 at the front. The IT6633 operates in software mode that allows the system to control it via a two-line serial interface, PCSCL/PCSDA. The IT6633 offers two selectable serial programming addresses by PCADR0. 58 5 QQ : 71 44 As a active switch, the IT6633 equalizes incoming TMDS data with optimal quality regardless of the incoming signal quality. The highly acclaimed equalization technology of ITE TECH. INC. provides for support of long or low-quality HDMI cables at even the highest speeds. Input terminations of the TMDS inputs and output current levels are both programmable. In addition, the input terminations are disconnectable and hence significantly lower the system power consumption in inactive modes. 18 66 4 34 1 The IT6633 embeds an EDID RAM to save the cost of the Three external EDID ROMs. The process of downloading the EDID data into the RAM is simplified by the automatic read-back capability of the IT6633, minimizing the need of MCU intervention. The IT6633 also embeds three 1K-ohm resisters for HPD signal paths to save external resisters and easy to implement the plug authentication. l: The IT6633 also incorporates I2C repeater in its DDC switches, which isolates the DDC capacitances Te of the two sides of the switch. This allows for longer cable cascading as well as significantly eases the 公 司 ， system design to pass Test ID 8-9: DDC/CEC Line Capacitance and Voltage of the HDMI Compliance Test. 深 圳 市 金 合 讯 科 技 有 限 The IT6633 also distinguish itself from its peers in that it offers ±8kV of Human Body Mode ESD protection to all TMDS high-speed input pins. This saves significant costs in external high-speed ESD diodes, which could be very expensive . www.ite.com.tw Nov-2009 Rev:0.6 2/11 IT6633 Features 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R HDMI active switch, providing superior performance over traditional passive switches Compliant with HDMI 1.3 and DVI 1.0 standards Serial data rate at up to 2.25Gbps, capable of supporting the following digital video formats in Deep Color Mode at up to 36 bits (12 bits/color): DTV resolutions: 480i, 576i, 480p, 576p, 720p, 1080i to 1080p PC resolutions: VGA, SVGA, XGA, SXGA to UXGA Single 3.3V operation Internal AC-coupling at TMDS inputs to cope with uneven intra-pair DC levels of incoming TMDS signals. Embedded EDID RAM saves external EDID ROM costs Embedded HDP resistors Integrated HPD switches Active port detection by monitoring PWR5V inputs and TMDS input clock. DDC I2C repeater isolates backend DDC capacitive loading from frontend, enhancing the DDC 18 l: Te ， 司 公 限 技 有 市 金 合 Human Body Mode ESD protection up to ±8kV for all TMDS differential input pins Disconnectable input terminations with auto-calibrated impedances Adaptive input equalization supporting long and short cables at the same time Software-mode operation providing flexibility Two possible serial programming device address.. Programmable TMDS output current level Programmable source terminations compliant with HDMI 1.3 standard, providing optimal source data eyes at high speeds High-impedance TMDS output when disabled Optional backend receiver termination detection for auto powerdown 64-Pin LQFP package RoHS Compliant ( 100% Green available ) 讯 科 66 4 operation compatibility 深 圳 Ordering Information Model Temperature Range Package Type Green/Pb free Option IT6633E-P 0~70 64-pin LQFP Green www.ite.com.tw Nov-2009 Rev:0.6 3/11 IT6633 CRX0M 56 CRX0P 57 VSS 58 CRX1M 59 CRX1P 60 VCC 61 CRX2M 62 CRX2P 63 NC 64 34 33 51 8 55 35 QQ : CPWR5V 36 58 5 54 37 34 1 CRXCP 38 66 4 53 39 18 CRXCM 40 l: 52 41 Te CSCL 42 ， 51 43 司 CSDA 44 公 50 45 限 CHPD 46 技 有 49 讯 科 TXPWR5V 47 71 44 48 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 NC 31 REXT 30 ARX2P 29 ARX2M 28 NC 27 ARX1P 26 ARX1M 25 VSS 24 ARX0P 23 ARX0M 22 VCC 21 ARXCP 20 ARXCM 19 ASCL 18 ASDA 17 RESET 16 深 圳 市 金 合 1 19 ， 廖 R Pin Diagram Figure 1. IT6633 pin diagram www.ite.com.tw Nov-2009 Rev:0.6 4/11 IT6633 Pin Description Pin No. Channel 2 positive input of Port A TMDS 30 Input Channel 2 negative input of Port A TMDS 29 ARX1P Input Channel 1 positive input of Port A TMDS ARX1M Input Channel 1 negative input of Port A TMDS 26 ARX0P Input Channel 0 positive input of Port A TMDS 24 ARX0M Input Channel 0 negative input of Port A TMDS 23 ARXCP Input Clock channel positive input of Port A TMDS 21 ARXCM Input Clock channel negative input of Port A TMDS 20 BRX2P Input Channel 2 positive input of Port B TMDS 14 BRX2M Input Channel 2 negative input of Port B TMDS 13 BRX1P Input Channel 1 positive input of Port B TMDS 11 BRX1M Input Channel 1 negative input of Port B TMDS 10 BRX0P Input Channel 0 positive input of Port B TMDS 8 BRX0M Input Channel 0 negative input of Port B TMDS 7 BRXCP Input Clock channel positive input of Port B TMDS 5 BRXCM Input Clock channel negative input of Port B TMDS 4 CRX2P Input Channel 2 positive input of Port C TMDS 63 CRX2M Input Channel 2 negative input of Port C TMDS 62 CRX1P Input Channel 1 positive input of Port C TMDS 60 CRX1M Input Channel 1 negative input of Port C TMDS 59 CRX0P Input Channel 0 positive input of Port C TMDS 57 CRX0M Input Channel 0 negative input of Port C TMDS 56 CRXCP Input Clock channel positive input of Port C TMDS 54 CRXCM Clock channel negative input of Port C TMDS 53 Type Pin No. 18 l: Te ， 司 公 限 技 有 27 合 Input 19 ， 51 8 ARX2M 71 44 Input QQ : ARX2P 58 5 Description 34 1 Direction 66 4 Pin Name 廖 R Type 讯 科 TMDS High Speed Differential Input Pins (All these pins provide ±8kV HBM ESD Protection) 市 金 TMDS High Speed Differential Output Pins Direction Description TX2P Output Channel 2 positive output of output port TMDS 36 TX2M Output Channel 2 negative output of output port TMDS 37 TX1P Output Channel 1 positive output of output port TMDS 39 TX1M Output Channel 1 negative output of output port TMDS 40 TX0P Output Channel 0 positive output of output port TMDS 42 TX0M Output Channel 0 negative output of output port TMDS 43 深 圳 Pin Name www.ite.com.tw Nov-2009 Rev:0.6 5/11 IT6633 TXCP Output Clock channel positive output of output port TMDS 45 TXCM Output Clock channel negative output of output port TMDS 46 Type Pin No. 廖 R DDC, HPD and PWR5V Control Pins Direction Description ASCL I/O Port A DDC bus clock line 5V-Tol. ASDA I/O Port A DDC bus data line 5V-Tol. BSCL I/O Port B DDC bus clock line 5V-Tol. 3 BSDA I/O Port B DDC bus data line 5V-Tol. 2 CSCL I/O Port C DDC bus clock line 5V-Tol. 52 CSDA I/O Port C DDC bus data line 5V-Tol. 51 TXSCL I/O Output Port DDC bus clock line 5V-Tol. 47 TXSDA I/O Output Port DDC bus data line 5V-Tol. 48 TXHPD Input HPD signal of the HDMI Sink 5V-Tol. 44 AHPD Output HPD signal to be sent back to Source connected to Port A LVTTL 16 BHPD Output HPD signal to be sent back to Source connected to Port B LVTTL 1 CHPD Output HPD signal to be sent back to Source connected to Port C LVTTL 50 TXPWR5V Output When ‘1’, indicates that the selected input port has a valid LVTTL 49 19 ， Pin Name 19 18 66 4 34 1 58 5 QQ : 71 44 51 8 18 PWR5V input and TMDS clock Input PWR5v of input port A for detection 5V-Tol 15 BPWR5V Input PWR5v of input port B for detection 5V-Tol 6 CPWR5V Input PWR5v of input port C for detection 5V-Tol 55 Type Pin No. Reset signals for logic blocks (active-high) LVTTL 17 Serial programming Clock for chip programming (5V-tolerant) Schmitt 34 I/O Serial programming Data for chip programming (5V-tolerant) Schmitt 33 Input Control of serial programming device address: LVTTL 35 Analog 31 公 司 ， Te l: APWR5V RESET Input PCSCL Input PCSDA 合 市 金 PCADR0 Description ‘0’: 0x94 ‘1’: 0x96 (default to ‘0’: 0x94 by internal weak pulled-down resistor of 圳 深 REXT 限 Direction 技 有 Pin Name 讯 科 Other Control and Configuration Pins 100kΩ) Analog External resistor for auto-calibration. Must be tied to VSS via a 500Ω precision resistor. NC www.ite.com.tw Must be left unconnected 28, 32, 64 Nov-2009 Rev:0.6 6/11 IT6633 Power and Ground Pins Description Type Pin No. VCC Chip power supply (3.3V) Power 12, 22, 38, 61 VSS Chip ground Ground 9, 25, 41, 58 51 8 19 ， 廖 R Pin Name 71 44 Functional Description ARX[2,1,0,C]P QQ : Autocalibration EQ BRX[2,1,0,C]P 3:1 MUX EQ TX[2,1,0,C]P DRV 66 4 BRX[2,1,0,C]M 34 1 58 5 ARX[2,1,0,C]M 18 TX[2,1,0,C]M CRX[2,1,0,C]P EQ RX Detect 司 ， Te l: CRX[2,1,0,C]M 限 技 有 讯 科 ASCL/ASDA BSCL/BSDA CSCL/CSDA EDID RAM HPD Control Register Block and Control Logic 圳 深 TXPWR5V TXSCL/TXSDA TXHPD DDC I2C Repeater/ Switch 市 金 合 AHPD BHPD CHPD Active port indication 公 APWR5V BPWR5V CPWR5V PCADR0 PCSCL/PCSDA IT6633E-P Block Figure 2. Functional block diagram of IT6633 www.ite.com.tw Nov-2009 Rev:0.6 7/11 IT6633 Power Consumption 廖 R Conditions: Typ VCC=3.3V Condition Current 1080P 12 bit Typ 180mA 58 5 QQ : 71 44 Mode 51 8 19 ， Operation Supply Current Typ 11.5mA 18 Standby 66 4 34 1 Standby Current ， Te l: Power Down Current Typ 2.5mA 深 圳 市 金 合 讯 科 技 有 限 公 司 Power Down www.ite.com.tw Nov-2009 Rev:0.6 8/11 IT6633 Electrical Specifications Max Unit -0.3 4.0 Input voltage -0.3 VCC+0.3 廖 R VO Output voltage -0.3 VCC+0.3 V VIDDC DDC control pins input voltage -0.3 6.0 V TJ Junction Temperature 51 8 Absolute Maximum Ratings Min. VCC Supply voltage VI Typ 125 °C TSTG Storage Temperature 150 °C ESD_HB Human body mode ARXs, BRXs, CRXs 8000 ESD sensitivity All other pins 2000 V 19 ， Parameter 71 44 Symbol V QQ : -65 V 34 1 58 5 ESD_MM Machine mode ESD sensitivity 200 V Notes: 1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device. 2. Refer to Functional Operation Conditions for normal operation. Parameter 18 Symbol 66 4 Functional Operation Conditions 1 Supply voltage TA Ambient temperature Θja Junction to ambient thermal resistance Typ Max Unit 3.135 3.3 3.465 V 0 25 70 °C 40 °C/W 1560 mV 3.465 V 0.444 40 ns 250 2250 Mbps Te ， TMDS Differential Pins TMDS differential input swing (peak-to-peak) 公 司 VIDIFF l: VCC Min. 1 TMDS output termination voltage Tbit Average bit time of the TMDS data stream Rbit Signaling rate of the serial TMDS data stream 技 有 限 VTERM 150 3.135 3.3 讯 科 DDC I/O Pins (ASCL/ASDA, BSCL/BSDA, CSCL/CSDA and TXSCL/TXSDA) 深 圳 市 金 合 VIDDC DDC input voltage 0 5.5 V Notes: 1. This is mandated by the HDMI Specifications v1.3 as the supply voltage at pin VCC is also the HDMI termination voltage. www.ite.com.tw Nov-2009 Rev:0.6 9/11 IT6633 DC Electrical Specification Under functional operation conditions Symbol Parameter Conditions Min. Typ Max Unit TMDS output low voltage VCC-10 VCC+10 VCC=VTERM=3.3V VCC-700 VCC-400 400 600 3 Vswing TMDS output single-ended swing IOFF Single-ended standby output current3 VOUT=0 10 Logic I/O Pins (LVTTL and Schmitt) Input high voltage1 VIH 2.0 1 Input low voltage VOL Output low voltage1 VOH Output high voltage VT- Schmitt trigger negative going threshold voltage VT+ 2.4 Input leakage current1 IOL Serial programming output sink l: Tri-state output leakage current 1 Te IOZ mV mV mV μA V 0.8 1.5 V V 0.4 V V 1.1 1.6 V 2.0 V VIN=5.5V or 0 ±5 μA VIN=5.5V or 0 ±10 μA VOUT=0.2V 4 16 mA ， 2 0.8 18 voltage1 current IOH=-2~-16mA 1 Schmitt trigger positive going threshold IIN IOL=2~16mA 58 5 1 QQ : Switching threshold 34 1 VT 1 66 4 VIL 71 44 VOLTMDS RLOAD=50Ω 19 ， 3 51 8 TMDS output high voltage3 VOHTMDS 廖 R TMDS Differential Output Pins (TX2P/M, TX1P/M, TX0P/M, TXCP/M) 深 圳 市 金 合 讯 科 技 有 限 公 司 Notes: 1. Guaranteed by I/O design. 2. The serial programming output ports are not real open-drain drivers. Sink current is guaranteed by I/O design under the condition of driving the output pin with 0.2V. In a real serial programming environment, multiple devices and pull-up resistors could be present on the same bus, rendering the effective pull-up resistance much lower than that specified by the I2C Standard. When set at maximum current, the serial programming output ports of IT6633E are capable of pulling down an effective pull-up resistance as low as 500Ω connected to 5V termination voltage to the standard I2C VIL. When experiencing insufficient low level problem, try setting the current level to higher than default. Refer to the IT6633E Register Table for proper register setting. 3. Limits defined by HDMI 1.3 standard www.ite.com.tw Nov-2009 Rev:0.6 10/11 IT6633 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R Package Dimensions Figure 3. 64-pin LQFP Package Dimensions www.ite.com.tw Nov-2009 Rev:0.6 11/11