FREESCALE MC33660EFR2

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Freescale Semiconductor
Advance Information
Document Number: MC33660
Rev 5.0, 10/2013
ISO K Line Serial Link Interface
The 33660 is a serial link bus interface device designed to provide
bi-directional half-duplex communication interfacing in automotive
diagnostic applications. It is designed to interface between the
vehicle’s on-board microcontroller, and systems off-board the vehicle
via the special ISO K line. The 33660 is designed to meet the
Diagnostic Systems ISO9141 specification. The device’s K line bus
driver’s output is fully protected against bus shorts and overtemperature conditions.
The 33660 derives its robustness to temperature and voltage
extremes by being built on a SMARTMOS process, incorporating
CMOS logic, bipolar/MOS analog circuitry, and DMOS power FETs.
Although the 33660 was principally designed for automotive
applications, it is suited for other serial communication applications. It
is parametrically specified over an ambient temperature range of
-40 ºC  TA  125 ºC and 8.0 V  VBB  18 V supply. The economical
SO-8 surface-mount plastic package makes the 33660 very cost
effective.
ISO9141 PHYSICAL INTERFACE
EF SUFFIX (PB-FREE)
98ASB42564B
8-PIN SOICN
ORDERING INFORMATION
Features
•
•
•
•
•
•
•
•
•
•
33660
Operates over wide supply voltage of 8.0 to 18 V
Operating temperature of -40 to 125 C
Interfaces directly to standard CMOS microprocessors
ISO K line pin protected against shorts to battery
Thermal shutdown with hysteresis
ISO K line pin capable of high currents
ISO K line can be driven with up to 10 nF of parasitic capacitance
8.0 kV ESD protection attainable with few additional components
Standby mode: no VBAT current drain with VDD at 5.0 V
Low current drain during operation with VDD at 5.0 V
Device
(For tape and reel orders,
add an R2 suffix)
Temperature
Range (TA)
Package
-40 to 125 °C
8-SOICN
MC33660EF
MC33660BEF
+VBAT
VDD
33660
VDD
VDD
VBB
CEN
RX
TX
ISO
MCU
Dx
SCIRxD
SCITxD
ISO K-LINE
TXD
GND
Figure 1. 33660 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are
subject to change without notice. 
© Freescale Semiconductor, Inc., 2011-2013. All rights reserved.
RXD
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Parameter
VBB Load Dump Peak Voltage (in accordance with
ISO 7637-2 & ISO 7637-3)
Module Level ESD (Air Discharge, Powered) (6)
Symbol
Condition
33660
33660B (1)
VBB(5a)
Pulse 5a
470 ohm series resistor
and 100 nF capacitor to
GND on VBB
–
82 V
VBB(5b)
Pulse 5b
470 ohm series resistor
and 100 nF capacitor to
GND on VBB
45 V
45 V
VESD4
33 V zener diode and
470 pF capacitor to
GND on ISO
–
±25000 V
Notes
1. Recommended for all new designs
33660
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VBB
3.0 k
60 V
600 k
20 V
* Only applies to 33660B
CEN
10 V
125 k
RX
RHYS
10 V
55 k
550 k
ISO
45 V
Master
Bias
110 k
55 V
Thermal
Shutdown
VDD
2.0 k
10 V
125 k
TX
10 V
GND
Figure 2. 33660 Simplified Internal Block Diagram
33660
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
VBB
11
88
CEN
NC
22
77
VDD
GND
33
66
RX
ISO
44
55
TX
Figure 3. 33660 Pin Connections
Table 2. 33660 Pin Definitions
Pin Number
Pin Name
1
VBB
Battery power through external resistor and diode.
Definition
2
NC
Not to be connected. (2)
3
GND
Common signal and power return.
4
ISO
Bus connection.
5
TX
Logic level input for data to be transmitted on the bus.
6
RX
Logic output of data received on the bus.
7
VDD
Logic power source input.
8
CEN
Chip enable. Logic “1” for active state. Logic “0” for sleep state.
Notes
2. NC pins should not have any connections made to them. NC pins are not guaranteed to be open circuits.
33660
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating
VDD DC Supply Voltage
Symbol
Value
Unit
VDD
-0.3 to 7.0
V
VBB Load Dump Peak Voltage (in accordance with ISO 7637-2 & ISO
7637-3)
V
Pulse 5a - 33660B only
VBB(5a)
82
Pulse 5b
VBB(5b)
45
VISO
40
Human Body Model (5)
VESD1
±2000
Machine Model (5)
VESD2
ISO Pin Load Dump Peak Voltage
ESD Voltage
(3)
(4)
V
±150
33660
±200
33660B
Charge Device Model
V
(5)
Corner Pins
VESD3-1
±750
All other Pins
VESD3-2
±500
VESD4
±25000
ISO Clamp Energy (7)
ECLAMP
10
mJ
Storage Temperature
TSTG
-55 to +150
C
Operating Case Temperature
TC
-40 to +125
C
Operating Junction Temperature
TJ
-40 to +150
C
PD
100
mW
TPPRT
Note 9.
°C
RJA
150
C/W
Module Level ESD (Air Discharge, Powered) (6)
33660B only
ISO pin with 33 V zener diode and 470 pF capacitor to GND -
Power Dissipation TA = 25 C
Peak Package Reflow Temperature During Reflow
Thermal Resistance: Junction-to-Ambient
(8), (9)
Notes
3. Device will survive double battery jump start conditions in typical applications for 10 minutes duration, but is not guaranteed to remain
within specified parametric limits during this duration.
4. ESD data available upon request.
5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ), ESD3 testing is performed in accordance with the Charge Device
Model (CZAP = 4.0 pF).
6.
7.
8.
9.
ESD4 testing is performed in accordance with ISO 10605 ESD model (C = 330 pF, R = 2.0 k). ESD discharges start at ±5.0 kV and
go up to ±25 kV in increments of 5.0 kV. There are two positions for discharges: 8.0 cm cable from ISO connector, 85 cm cable from
ISO connector. There are 10 ESD discharges per voltage at each cable position at a minimum of 1.0 s intervals. Remaining charge is
not bled off after every discharge.
Nonrepetitive clamping capability at 25 C.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33660
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions of 4.75 V  VDD 5.25 V, 8.0 V  VBB  18 V, -40 C  TC  125 C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER AND CONTROL
VDD Sleep State Current
IDD(SS)
mA
Tx = 0.8 VDD, CEN = 0.3 VDD
VDD Quiescent Operating Current
–
0.1
–
–
1.0
–
–
50
–
–
1.0
IDD(Q)
mA
Tx = 0.2 VDD, CEN = 0.7 VDD
VBB Sleep State Current
–
IBB(SS)
µA
VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD
VBB Quiescent Operating Current
IBB(Q)
mA
TX = 0.2 VDD, CEN = 0.7 VDD
Chip Enable
V
(10)
VIH(CEN)
0.7 VDD
–
–
Input Low Voltage Threshold (11)
VIL(CEN)
–
–
0.3 VDD
IPD(CEN)
2.0
–
40
–
–
0.3 x VDD
0.7 x VDD
–
–
-40
–
-2.0
–
–
0.2 VDD
0.8 VDD
–
–
150
170
–
Input High Voltage Threshold
Chip Enable Pull-down Current (12)
TX Input Low Voltage Threshold
RISO = 510 
V
(13)
TX Input High Voltage Threshold
RISO = 510 
VIL(TX)
VIH(TX)
(14)
TX Pull-up Current (15)
IPU(TX)
RX Output Low Voltage Threshold
VOL(RX)
V
VOH(RX)
RISO = 510 , TX = 0.8 VDD, RX Sourcing 250 µA
Thermal Shutdown (16)
µA
V
RISO = 510 , TX = 0.2 VDD, Rx Sinking 1.0 mA
RX Output High Voltage Threshold
µA
V
TLIM
C
Notes
10. When IBB transitions to >100 µA.
11.
When IBB transitions to <100 µA.
12.
Enable pin has an internal current pull-down. Pull-down current is measured with CEN pin at 0.3 VDD.
13.
Measured by ramping TX down from 0.8 VDD and noting TX value at which ISO falls below 0.2 VBB.
14.
Measured by ramping TX up from 0.2 VDD and noting the value at which ISO rises above 0.9 VBB.
15.
Tx pin has internal current pull-up. Pull-up current is measured with TX pin at 0.7 VDD.
16.
Thermal Shutdown performance (TLIM) is guaranteed by design, but not production tested.
33660
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (Continued)
Characteristics noted under conditions of 4.75 V  VDD 5.25 V, 8.0 V  VBB  18 V, -40C  TC  125C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
ISO I/O
Input Low Voltage Threshold
VIL(ISO)
RISO = 510 , TX = 0.8 VDD
Input High Voltage Threshold
Input Voltage Hysteresis
VHYS(ISO)
Internal Pull-up Current
IPU(ISO)
RISO =  , TX = 0.8 VDD, VISO = 9.0 V, VBB = 18 V
RISO =  , TX = 0.8 VDD
0.4 x VBB
0.7 x VBB
–
–
0.05 x VBB
–
0.1 x VBB
-5.0
–
-140
50
–
200
–
–
0.1 x VBB
V
V
µA
mA
VOL(ISO)
RISO = 510 , TX = 0.2 VDD
Output High Voltage
–
ISC(ISO)
RISO = 0 , TX = 0.4 VDD, VISO = VBB
Output Low Voltage
–
VIH(ISO)
RISO = 510 , TX = 0.8 VDD
Short-circuit Current Limit
V
V
VOH(ISO)
V
0.95 x VBB
–
–
33660
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions of 4.75 V  VDD 5.25 V, 8.0 V  VBB  18 V, -40 C  TC  125 C, unless otherwise
noted.
Characteristic
Fall Time (17)
Symbol
High to Low: RISO = 510 , CISO = 500 pF (19)
Low to High: RISO = 510 , CISO = 500 pF (20)
Typ
Max
–
–
2.0
–
–
2.0
–
–
2.0
tFALL(ISO)
RISO = 510  to VBB, CISO = 10 nF to Ground
ISO Propagation Delay (18)
Min
Unit
µs
tPD(ISO)
µs
Notes
17. Time required ISO voltage to transition from 0.8 VBB to 0.2 VBB.
18.
Changes in the value of CISO affect the rise and fall time but have minimal effect on Propagation Delay.
19.
Step TX voltage from 0.8 VDD to 0.2 VDD. Time measured from VIH(Tx) until VISO reaches 0.3 VBB.
20.
Step TX voltage from 0.2 VDD to 0.8 VDD. Time measured from VIL(Tx) until VISO reaches 0.7 VBB.
33660
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
0.6
VIH; VDD = 5.25 V, VBB =
18 V
VIH; VDD = 4.75 V, VBB =
8.0 V
0.575
0.55
0.525
0.5
0.475
-50
VIL; VDD = 5.25 V, VBB =
18 V
VIL; VDD = 4.75 V, VBB =
8.0 V
0
50
100
150
TA, AMBIENT TEMPERATURE (C)
VOL and VOH, ISO OUTPUT (RATIO)
VIL and VIH, INPUT THRESHOLD (RATIO)
ELECTRICAL PERFORMANCE CURVES
1.2
0.8
0.4
0.2
VOL
0
-50
VDD = 5.25 V, VBB = 18 V
0.85
0.8
0.75
VDD = 4.75 V, VBB = 8.0 V
0.7
0.65
-50
0
50
100
TA, AMBIENT TEMPERATURE (C)
Figure 5. ISO Output/VBB vs. Temperature
150
0
50
100
150
TA, AMBIENT TEMPERATURE (C)
Figure 6. ISO Fall Time vs. Temperature
tPD(ISO), PROPAGATION DELAY (µs)
tfall(ISO), ISO FALL TIME (µs)
0.9
VDD = 4.75 V, VBB = 8.0 V
and
VDD = 5.25 V, VBB = 18 V
0.6
Figure 4. ISO Input Threshold/VBB vs. Temperature
0.95
VOH
1.0
0.7
VDD = 5.25 V, VBB = 18 V
PdH-L
0.6
VDD = 4.75 V, VBB = 8.0 V
0.5
0.4
0.3
0.2
-50
VDD = 5.25 V, VBB = 18 V
PdL-H
VDD = 4.75 V, VBB = 8.0 V
0
50
100
150
TA, AMBIENT TEMPERATURE (C)
Figure 7. ISO Propagation Delay vs. Temperature
33660
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
The 33660 is a serial link bus interface device conforming
to the ISO 9141 physical bus specification. The device is
designed for automotive environment usage, compliant with
On-board Diagnostics (OBD) requirements set forth by the
California Air Resources Board (CARB) using the ISO K line.
The device does not incorporate an ISO L line. It provides bidirectional half-duplex communications interfacing from a
microcontroller to the communication bus. The 33660
incorporates circuitry to interface the digital translations from
5.0 V microcontroller logic levels to battery level logic, and
from battery level logic to 5.0 V logic levels. The 33660 is built
using Freescale Semiconductor’s SMARTMOS process and
is packaged in an 8-pin plastic SOIC.
FUNCTIONAL DESCRIPTION
The 33660 transforms 5.0 V microcontroller logic signals
to battery level logic signals and visa versa. The maximum
data rate is set by the rise and fall time. The fall time is set by
the output driver. The rise time is set by the bus capacitance
and the pull-up resistors on the bus. The fall time of the 33660
allows data rates up to 150 kbps using a 30 percent
maximum bit time transition value. The serial link interface
will remain fully functional over a battery voltage range of 6.0
to 18 V. The device is parametrically specified over a
dynamic VBB voltage range of 8.0 to 18 V.
Required input levels from the microcontroller are ratiometric with the VDD voltage normally used to power the
microcontroller. This enhances the 33660’s ability to remain
in harmony with the RX and TX control input signals of the
microcontroller. The RX and TX control inputs are compatible
with standard 5.0 V CMOS circuitry. For fault tolerant
purposes the TX input from the microcontroller has an internal
D(1)
+VDD = 5.0 V
33660
VBB
VCC
Dx
1.0 nF
A pull-up to battery is internally provided as well as an
active data pull-down. The internal active pull-down is
current-limit protected against shorts to battery, and further
protected by thermal shutdown. Typical applications have
reverse battery protection by the incorporation of an external
510  pull-up resistor and a diode to battery.
Reverse battery protection of the device is provided by the
use of a reverse battery blocking diode (See “D” in the Typical
Application Diagram on page 10). Battery line transient
protection of the device is provided for by using a 45 V zener
and a 500  resistor connected to the VBB source, as shown
in the same diagram. Device ESD protection from the
communication lines exiting the module is through the use of
the capacitor connected to the VBB device pin, and the
capacitor used in conjunction with the 27 V zener connected
to the ISO pin.
+VBAT
On-Board Diagnostic Link
MCU
passive pull-up to VDD, while the CEN input has an internal
passive pull-down to ground.
VDD
45 V(2)
500 (2)
10 nF(3)
510 
CEN ISO
SCIRxD
RX
SCITxD
TX
Service Scan Tool
or
End of Production Line
Programming
or
System Checking
5.0 nF(3)
27 V(3)
TxD
RxD
ISO
K Line
GND
Components necessary for Reverse Battery (1), Overvoltage Transient (2), and 8.0 kV
ESD Protection (3) in a metal module case.
Figure 8. Typical Application Diagram
33660
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
EF SUFFIX (PB-FREE)
8-PIN
98ASB42564B
REV. V
33660
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
PACKAGING
PACKAGE DIMENSIONS
EF SUFFIX (PB-FREE)
8-PIN
98ASB42564B
REV. V
33660
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
1.0
1/2011
• Initial release
2.0
9/2011
• Adjusted format to meet current compliance standards. No data was altered.
3.0
10/2011
• Updated the PC part number to MC.
4.0
2/2013
• Added PC33660BEF to the ordering information
• Redefined VBB Load Dump Peak Voltage (in accordance with ISO 7637-2 & ISO 76373) for the 33660B
• Added Module Level ESD (Air Discharge, Powered) (6) for the 33660B
• Added note (6)
• Increased ESD structure voltage for 33660B, and added bleed-off circuit on VBB pin in
Figure 2
5.0
10/2013
• Clarified machine model limits for MC33660 and MC33660B, page 5
33660
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
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© 2013 Freescale Semiconductor, Inc.
Document Number: MC33660
Rev 5.0
10/2013