FUJITSU MB89374

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-22307-5E
ASSP Communication Control
Data Link Controller (DLC)
MB89374
■ DESCRIPTION
The MB89374 Data Link Controller (DLC) controls transfer of serial data in accordance with Bit Oriented Protocol
(BOP). It supports protocols such as High level Data Link Control (HDLC) (the BOP mode) and Serial Data
Link Control (SDLC) LOOP secondary station (the LOOP mode).
■ FEATURES
•
•
•
•
•
•
•
•
Supports BOP serial data transfer procedure
Supports SDLC LOOP mode
Internal full-duplex communications channel
Data transfer at rates up to 2.5 Mbps (at 10 MHz)
However, in the LOOP mode, the maximum transfer rates are 1.25 Mbps for NRZ/NRZI code and 833 kpbs
for FM/Manchester code.
10 MHz system clock with 1/2 duty, or 8 MHz with 1/3 duty
Internal inter frame spacing counter
Receive address field data compared with address data register
One-byte address compare (multicasting address collating)
-
Two-byte address compare
One-byte two-address compare
Global address compare
• Supports two type of CRC checks (CRC16/CCITT)
(Continued)
■ PACKAGES
42 pin, Plastic SH-DIP
(DIP-42P-M02)
48 pin, Plastic QFP
(FPT-48P-M13)
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
MB89374
(Continued)
• FIFO transmit data (4 bytes) and receive data (8 bytes)
• Supports various codings (NRZ/NRZI/Manchester/FM0/FM1)
• Automatic return mode selectable in NRZI coding mode
• Various error interrupt request functions
• DMA interface function
• Two bit-rate generator channels for SIU transfer clock (Transmit and Receive)
The bit rate generators can also be used as interval timers.
• Direct register access method
• MBL8086/88-family or GMICRO-family bus interface selectable
• Single +5 V power supply
2
MB89374
■ PIN ASSIGNMENTS
CLK
1
42
VCC
FORMAT#
2
41
RXDACK#/PI3
RESET#
3
40
TXDACK#/PI2
RXDRQ/PO3
RD#/DS#
4
39
WR#/R/W#
5
38
TXDRQ/PO2
CS#
6
37
IRQT
A4
7
36
VSS
A3
8
35
IRQ
A2
9
34
FD#/DTR#
A1
10
33
SCLK/DSR#
A0
11
32
TXLAST#/CI#
VSS
12
31
TXCI#/PI1
D7
13
30
TXCO#/PO1
D6
14
29
TXD
D5
15
28
RXD
D4
16
27
RXCI#/PI0
D3
17
26
RXCO#/PO0
D2
18
25
DCD#
D1
19
24
CTS#
D0
20
23
TCLK
VSS
21
22
LOC#/RTS#
<OPEN>
D3
D2
D1
D0
VSS
<OPEN>
LOC#/RTS#
CTS#
TCLK
DCD#
RXCO#/POO
(DIP-42P-M02)
48 47 46 45 44 43 42 41 40 39 38 37
<OPEN>
1
36
D4
RXCI#/PI0
2
35
D5
RXD
3
34
D6
D7
5
32
VSS
TXCI#/PI1
6
31
A0
TXLAST#/CI#
7
30
A1
SCLK/DSR#
8
29
A2
FD#/DTR#
9
28
A3
IRQ
10
27
A4
VSS
11
26
CS#
12
25
<OPEN>
Note: OPEN pins require no connection.
WR#/R/W#
RD#/DS#
RESET#
FORMAT#
20 21 22 23 24
CLK
<OPEN>
17 18 19
VCC
TXDACK/PI2
14 15 16
RXDACK#/PI3
13
RXDRQ/PO3
IRQT
<OPEN>
4
TXCO#/PO1
TXDRQ/PO2
TXD
33
(FPT-48P-M13)
3
MB89374
■ PIN DESCRIPTION
Pin No.
DIP
30
31
26
27
22
34
25
24
QFP
5
6
48
2
44
9
47
46
Symbol
TXCO#/PO1
TXCI#/PI1
RXCO#/PO0
RXCI#/PI0
LOC#/RTS#
FD#/DTR#
DCD#
CTS#
I/O
O
I
O
I
O
O
I
I
Level*
Description
L
Transmit clock-output or port-output 1 pin:
This pin is selected as the clock-output pin or port-output pin
by the TxC0 and TxC1 bits of the transfer mode register
(SMR2) and by the TxBRGEN bit of the transmit mode
register (SMR3).
—
Transmit clock-input or port-input 1 pin:
This pin is selected as the clock-input pin or port-input pin by
the TxC0 and TxC1 bits of the transfer mode register
(SMR2) and by the TxBRGEN bit of the transmit mode
register (SMR3).
L
Receive clock-output or port-output 0 pin:
This pin is selected as the clock-output pin or port-output pin
by the RxC0 and RxC1 bits of the transfer mode register
(SMR2).
—
Receive clock-input or port-input 0 pin:
This pin is selected as the clock-input pin or port-input pin by
the RxC0 and RxC1 bits of the transfer mode register
(SMR2).
H
Loop on-line control or request-to-send pin:
This pin serves as the LOC# output pin in the LOOP mode
and as the RTS# output pin in the BOP mode. If it is used as
the LOC# output pin, it functions as an on-line/off-line control
pin. If it is used as the RTS# output pin, it outputs a LOW
level when the RTS bit of the modem control register (MCR)
is set to 1, and outputs a HIGH level when the RTS bit is set
to 0.
H
Flag-detect or data-terminal-ready pin:
This pin is selected as the flag-detect or data-terminal-ready
pin by the FD or DTR bits of the transmit mode register
(SMR3). If it is used as the FD# pin, it outputs a LOW level
during one cycle of the receive clock after receiving the last
bit of the flag. If it is used as the DTR# pin, it outputs a LOW
level when the DTR bit of the modem control register (MCR)
is set to 1, and a HIGH level when the DTR bit is set to 0.
—
Data-carrier-detect pin:
The DCD bit of the modem status register (MSR) displays 1
when the pin input level is LOW and 0 when the input level is
HIGH.
—
Clear-to-send pin:
The CTS bit of the modem status register (MSR) displays 1
when the pin input level is LOW, and displays 0 when the
input level is HIGH. The DLC is placed in the transmissionenable state when this pin is set to the CTSAUTO mode, and
by the TxE bit of the transmission control register (TxCR).
Transmission is enabled/disabled according to the input level
of the CTS# pin; transmission is enabled when the pin input
level is LOW and disabled when the input level is HIGH.
Signals suffixed by the symbol # are negative logic.
* : Pin output level when reset
4
(Continued)
MB89374
(Continued)
Pin No.
DIP
QFP
Symbol
I/O
Level*
Description
32
7
TXLAST#/CI#
I
—
Transmit DMA-end-signal or calling-indication pin:
This pin serves as the TxLAST# input pin when the DMA
mode is selected by the TxD/I bit of the transmit interrupt
enable register (TxIER), and by the enabling TxLASTEND
bit of the transmit mode register (SMR3). In other cases,
this pin serves as the CI# input pin. If this pin is used as the
CI# input pin, the CI bit of the modem status register (MSR)
displays 1 when the pin input level is LOW, and 0 when the
input level is HIGH.
29
4
TXD
O
H
Transmit-data pin:
This pin is used to output serial data.
28
3
RXD
I
—
Receive-data pin:
This pin is used to input serial data.
—
Source-clock input or data-set-ready pin:
This pin serves as the SCLK input pin for BRG1/BRG2 or
DPLL when:
• BRG, DPLL or BRG + DPLL are selected by the TxC0 and
TxC1 bits of the transfer mode register (SMR2).
• BRG, DPLL or BRG + DPLL are selected by the RxC0 and
RxC1 bits of the transfer mode register (SMR2).
• The BRG1OUTIE bit of the BRG1/DPLL control register
(B1PCR) is set to 1.
• The BRG2CLK bit of the BRG2 control register (B2CR) is
set to 1.
In other cases, this pin serves as the DSR# input pin.
If this pin is used as the DSR# input pin, the DSR bit of the
modem status register (MSR) displays 1 when the pin input
level is LOW, and 0 when the input level is HIGH.
33
8
SCLK/DSR#
I
23
45
TCLK
I
—
BRG2 clock-input pin:
This pin is used only when the clock source for BRG2 is not
set at the SCLK pin (by setting the BRG2CLK bit of the
BRG2 control register (B2CR)).
3
22
RESET#
I
—
Reset pin:
This pin is used to input system reset signals.
—
Read/data strobe pin:
This pin serves as the RD# input pin in the MBL8086/88
mode. A LOW level is input to this pin when reading the
registers in the DLC.
This pin serves as the DS# input pin in the GMICRO mode.
Strobe signals are input to this pin when accessing the
registers in the DLC.
4
23
RD#/DS#3
I
Signals suffixed by the symbol # are negative logic.
(Continued)
* : Pin output level when reset
5
MB89374
(Continued)
Pin No.
DIP
QFP
Symbol
I/O
Level*
Description
5
24
WR#/R/W#
I
—
Write or read/write pin:
This pin serves as the WR# input pin in the MBL8086/88
mode. A LOW level is input to this pin when writing to the
registers in the DLC. This pin serves as the R/W# input pin
in the GMICRO mode. It determines the data direction when
accessing the registers in the DLC.
6
26
CS#
I
—
Chip-select pin:
A LOW level is input to this pin when accessing the registers
in the DLC.
CPU-interface mode-setting pin:
This pin is set to the GMICRO mode when the input level is
LOW, and to the MBL8086/88 mode when the input level is
HIGH. The pin input level must be fixed to LOW or HIGH.
2
21
FORMAT#
I
—
13 to
20
33 to
36,
38 to 41
D7 to D0
I/O
Hi-Z
7 to 11 27 to 31
A4 to A0
I
—
Address pins:
These pins are used to input addresses to select the
registers in the DLC.
L
Interrupt-request pin:
This pin is used to generate HIGH interrupt requests by
using bits other than the BRG2OUT bit of the BRG2 status
register (B2SR) as interrupt trigger bits.
L
Interrupt-request pin:
This pin is used to generate HIGH interrupt requests by
using the BRG2OUT bit of the BRG2 status register (B2SR)
as the interrupt trigger bit.
L
Receive DMA-request or port-output 3 pin:
The receive DMA-request pin or port-output pin is selected
by the RxD/I bit of the receive interrupt enable register
(RxIER). If this pin is used as the RxDRQ pin, it outputs a
HIGH level to request DMA transfer of receive data. If this
pin is used as the PO3 pin, it outputs a HIGH level when the
PO3 bit of the port register (PORTR) is 1, and a LOW level
when the PO3 bit is 0.
L
Transmit DMA-request or port-output 2 pin:
The transmit DMA-request pin or port-output pin is selected
by the TxD/I bit of the transmit interrupt enable register
(TxIER). If this pin is used as the TxDRQ pin, it outputs a
HIGH level to request the DMA transfer of transmit data. If
this pin is used as the PO2 pin, it outputs a HIGH level when
the PO2 bit of the port register (PORTR) is 1, and a LOW
level when the PO2 bit is 0.
35
37
39
38
10
12
15
14
IRQ
IRQT
RXDRQ/PO3
TXDRQ/PO2
O
O
O
O
Signals suffixed by the symbol # are negative logic.
* : Pin output level when reset
6
Data-bus (tristate) pins:
These pins are used to input and output 8-bit data.
(Continued)
MB89374
(Continued)
Pin No.
DIP
41
QFP
17
Symbol
RXDACK#/
PI3
I/O
I
Level*
Description
—
Receive DMA-acknowledge or port-input 3 pin:
The receive DMA-acknowledge pin or port-input pin is
selected by the RxD/I bit of the receive interrupt enable
register (RxIER). If this pin is used as the RxDACK# pin, it
inputs acknowledge signals for DMA transfer of receive data.
If this pin is used as the PI3 pin, the PI3 bit of the port
register (PORTR) is set to 1 when the pin input level is
HIGH, and 0 when the input level is LOW.
40
16
TXDACK#/
PI2
I
—
Transmit DMA-acknowledge or port-input 2 pin:
The transmit DMA-acknowledge pin or port-input pin is
selected by the TxD/I bit of the transmit interrupt enable
register (TxIER). If this pin is used as the TxDACK# pin, it
inputs acknowledge signals for the DMA transfer of transmit
data. If this pin is used as the PI2 pin, the PI2 bit of the port
register (PORTR) is set to1 when the pin input level is HIGH,
and 0 when the input level is LOW.
1
20
CLK
I
—
System clock pin:
This pin is used to input clocks for DLC operation.
12, 21,
36
11, 32,
42
VSS
-
—
Ground pins
42
18
VCC
-
—
+5 VDC ±10% power-supply pin
—
1, 13,
19, 25,
37, 43
<OPEN>
-
—
OPEN pins always require no connection.
Signals suffixed by the symbol # are negative logic.
* : Pin output level when reset
7
MB89374
■ BLOCK DIAGRAM
The DLC internal block diagram is shown below. The DLC consists of the SIU, BRG, DPLL, read/write control, and DMA interface sections.
IRQT
TXCI#/PI1
RXCI#/PI0
BRG1, BRG2 and DPLL sections
Tx
TCLK
BRG2
SCLK/DSR#
Tx
TXCO#/PO0
Tx
CTS#
TxC
Prescaler
DCD#
LOC#/RTS#
BRG1
TURN
switching
DPLL
Rx
RXCO#/PO1
Rx
Rx
FD#/DTR#
TXLAST#/CI#
IRQ
RxC
PortR
MSR
MCR
SIU section
TXIER
RXIER
REQR
MASKR
CRCC
DMA
interface section
ShiftR
Status
FIFO
Odel
TXDRQ/PO2
Decoder
TXDACK#/PI2
Receiver
controller
Receive data
FIFO
RXDRQ/PO3
RXDACK#/PI3
CLK
FORMAT#
RD#/DS#
WR#/R/W#
CS#
A4 to A0
SDR
RXCR
RXSR0, 1
Read/write
control
section
D7 to D0
CRCG
Command
FIFO
Transmitter
controller
ShiftR
Oins
RXD
TXD
coder
TURN
switching
Transmit data
FIFO
TXCR
TXSR
VCC
VSS
RESET#
SDR
Indicates selected circuits
8
MB89374
■ FUNCTIONAL DESCRIPTION OF EACH BLOCK
• SIU section
– Detects and generates flags
– Inserts and deletes 0
– Compares address field data
– Generates and checks CRC
• BRG1 section (Selectable among three below)
– Generates transfer clock
– Generates clock for DPLL operation
– Functions as interval timer
• BRG2 section (Selectable among two below)
– Generates transfer clock
– Functions as interval timer
• DPLL section
Generates receive clock synchronized with received serial data
• CPU interface section
– Read/write control
– DMA interface control
9
MB89374
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Power supply voltage
VCC
–0.3 to +7.0
V
Input voltage
VIN
–0.3 to VCC + 0.3
V
VOUT
–0.3 to VCC + 0.3
V
Ambient temperature
Ta
0 to +70
°C
Storage temperature
Tstg
–55 to +150
°C
Output voltage
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
(VSS = 0 V (Voltage referenced to VSS)
Value
Unit
Min.
Typ.
Max.
Power supply voltage
VCC
+4.5
5
+5.5
V
Ambient temperature
Ta
0
—
+70
°C
■ PIN CAPACITANCE
(Ta = +25°C)
Parameter
Input capacitance
10
Symbol
Test condition
CIN
Output capacitance
COUT
Input/output capacitance
CI/O
fc = 1 MHz
Min.
Max.
Unit
—
20
pF
—
20
pF
—
20
pF
MB89374
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Conditions
Min.
Max.
Unit
Power supply current
ICC
Output open, input 0 V or VCC,
when operating at 10 MHz
—
15
mA
Input leakage current
IILK
0 V ≤ VIN ≤ VCC
—
±10
µA
Output leakage current
IOLK
0 V ≤ VIN ≤ VCC
Output in high impedance state
—
±10
µA
Low-level input voltage
VIL
Pins other than CLK
–0.3
0.8
V
High-level input voltage
VIH
Pins other than CLK
2.0
VCC+0.3
V
Low-level output voltage
VOL
IOL = 2.5 mA
–
0.4
V
High-level output voltage
VOH
IOH = –2.5 mA
3.0
—
IOH = –100 µA
VCC–0.4
—
Low-level clock input voltage
VCL
CLK pin
–0.3
0.6
V
High-level clock input voltage
VCH
CLK pin
3.9
VCC+0.3
V
V
2. AC Characteristics Measurement Conditions
• AC Test Waveform
2.0 V
2.0 V
0.8 V
0.8 V
2.4 V (HIGH level)
0.45 V (LOW level)
Measurement points
• AC Test Load Circuit
Output pin for testing
CL = 100pF
CL includes the probe capacitance.
11
MB89374
3. AC Characteristics
(1) System Clock
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
Clock period
tCK
100
—
Low-level clock pulse duration
tCKL
40
—
High-level clock pulse duration
tCKH
40
—
Clock pulse rise time, fall time
tr, tf
—
10
Unit
ns
tCK
tCKH
tCKL
CLK
tf
tr
(2) System Reset
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
Unit
Reset pulse width
tRESET
5tCK
—
ns
tRESET
RESET#
12
MB89374
(3) Read Timing
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
Read pulse width
tRR
1tck +20
—
Address setup time (RD#, DS# ↓ )
tAR
30
—
Address hold time (RD#, DS# ↑ )
tRA
0
—
Data delay (RD#, DS# ↓ )
tDR
—
90
Data hold time (RD#, DS# ↑ )
tRD
10
60
Unit
ns
tRR
RD#
(DS#)
tAR
tR
A4 to A0, CS#
(R/W#)
tDR
tRA
D7 to D0
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
(4) Write Timing
(VCC = +5 V ±10%, VSS = 0 V, TA = 0°C to +70°C)
Symbol
Min.
Max.
Write pulse width
tWW
1tck +20
—
Address setup time (WR#, DS# ↓ )
tAW
30
—
Address hold time (WR#, DS# ↑ )
tWA
0
—
Data setup time (WR#, DS# ↑ )
tDW
60
—
Data hold time (WR#, DS# ↑ )
tWD
10
—
Parameter
Unit
ns
tWW
WR#
(DS#)
tAW
tWA
A4 to A0, CS#
(R/W#)
tDW
tWD
D7 to D0
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
13
MB89374
(5) Data Access Recovery Time
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Recovery time during
data access
RD# ↑
WR# ↑
DS# ↑
Symbol
Min.
Max.
Unit
tACCS
3tCK +20
—
ns
TXDACK ↓
RXDACK ↓
tACCS
RD# (DS#)
RXDACK
tACCS
WR# (DS#)
TXDACK
tACCS
RD# (DS#)
RXDACK
WR# (DS#)
TXDACK
tACCS
RD# (DS#)
RXDACK
WR# (DS#)
TXDACK
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
14
MB89374
(6) DMA Timing 1
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
TxDACK pulse width
tTXDACK
1tCK + 20
—
TxDACK setup time (WR#, DS# ↓ )
tTXDACKS
0
—
TxDACK hold time (WR#, DS# ↑ )
tTXDACKH
0
—
TxDRQ delay (WR#, DACK# ↑ )
tDTXDRQL
—
60
Data setup time (WR#, DS# ↑ )
tDDIS
60
—
Data hold time (WR#, DS# ↑ )
tDDIH
0
—
TxLAST# setup time (WR#, DS# ↑ )
tTXLASTS
60
—
TxLAST# hold time (WR#, DS# ↑ )
tTXLASTH
0
—
Unit
ns
TXDRQ
tDTXDRQL
tTXDACK
TXDACK
tTXDACKS
tTXDACKH
WR# (DS#)
tDDIS
tDDIH
tTXLASTS
tTXLASTH
D7 to D0
TXLAST#
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
15
MB89374
(7) DMA Timing 2
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
RXDACK pulse width
tRXDACK
1tCK + 20
—
RXDACK setup time (RD#, DS# ↓ )
tRXDACKS
0
—
RXDACK hold time (RD#, DS# ↑ )
tRXDACKH
0
—
RXDRQ ↓ delay (RXDACK↑ )
tDRXDRQL
—
60
Data delay(RD#, DS# ↓ )
tDDOD
—
90
Data hold time (RD#, DS# ↑ )
tDDOH
10
60
RXDRQ
tDRXDRQL
tRXDACK
RXDACK
tRXDACKS
tRR
tRXDACKH
RD#(DS#)
tDDOD
tDDOH
D7 to D0
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
16
Unit
ns
MB89374
(8) IRQ Masking
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (WR#, DS# ↑ )
Symbol
Min.
Max.
Unit
tIIRQM
—
3tCK
ns
MASKR selected
CS#, A4 to A0
WR# (DS#)
tIIRQM
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
(9) Interrupt by Underrun
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (Tx,C# ↓ )
(Note)
Symbol
Min.
Max.
Unit
tSTXUI
—
3tCK
ns
Note: TxC# denotes TxCI# or TxCO#; RxC# denotes RxCI# or RxCO#.
First abort bit
TXCI#, TXCO#
tSTXUI
IRQ
17
MB89374
(10) Interrupt by LOOP Transmit Data Delay
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (TxC# ↓ )
(Note)
Symbol
Min.
Max.
Unit
tSLATEI
—
4tCK
ns
Note: TxC# denotes TxCI# or TxCO#; RxC# denotes RxCI# or RxCO#.
Last bit of go-ahead pattern
TXCI#, TXCO#
tSLATEI
IRQ
(11) Interrupt by Frame Termination
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (TxC# ↓ )
(Note)
Symbol
Min.
Max.
Unit
tSTXENDI
—
3tCK
ns
Note: TxC# denotes TxCI# or TxCO#; RxC# denotes RxCI# or RxCO#.
Last bit of close-flag pattern
TXCI#, TXCO#
tSTXENDI
IRQ
18
MB89374
(12) Interrupt by Transmit Byte Counter
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (TxC# ↓ )
(Note)
Symbol
Min.
Max.
Unit
tSTXCOUTI
—
3tCK
ns
Note: TxC# denotes TxCI# or TxCO#; RxC# denotes RxCI# or RxCO#.
Last bit of last data
TXCI#, TXCO#
tSTXCOUTI
IRQ
(13) Interrupt by Loop On-line
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (RxC# ↑ )
Symbol
Min.
Max.
Unit
tSLOCI
—
9tCK
ns
Center of last bit of on-line pattern (1 in bit 7) when on-line
requested, or off-line pattern (1 in bit 7) when off-line requested
RXCI#, RXCO#
tSLOCI
IRQ
19
MB89374
(14) Interrupt by Loop Error
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (RXC# ↑ )
Symbol
Min.
Max.
Unit
tSLERI
—
5tCK
ns
Center of last bit of flag pattern
RXCI#, RXCO#
tSLERI
IRQ
(15) Interrupt by Detection of Go-agead Pattern
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (RxC# ↑ )
Symbol
Min.
Max.
Unit
tSGAPI
—
3tCK
ns
Center of last bit of go-ahead pattern
RXCI#, RXCO#
tSGAPI
IRQ
20
MB89374
(16) Interrupt by Idle Detection/Idle Termination
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (RXC# ↑ )
Symbol
Min.
Max.
Unit
tSIDLI
—
4tCK
ns
1 in bit 15 when idle detected; center of last bit of flag
pattern when idle terminated
RXCI#, RXCO#
tSIDLI
IRQ
(17) Output Modem Control Signal
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Port output delay (WR#, DS# ↑ )
CS#,A4 to A0
Symbol
Min.
Max.
Unit
tSPORTD
—
2tCK + 60
ns
MSR selected
WR# (DS#)
tSPORTD
DTR#, RTS#
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
21
MB89374
(18) Input Modem Control Signal 1
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
IRQ ↑ delay (Port ↓ ↑ )
tSPORTI
—
4tCK
Port input setting (RD#, DS# ↓ )
tSPORTF
—
1tCK + tCKH + 60
Unit
ns
DSR#, DSD#
CTS#, CI#
MSR selected
CS#, A4 to A0
tSPORTF
RD#, (DS#)
tSPORTI
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
(19) Input Modem Control Signal2
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (SCLK ↓ )
Symbol
Min.
Max.
Unit
tSBRGI
—
5tCK + 250
ns
BRG count completed
SCLK
tSBRGI
IRQ
22
MB89374
(20) Input Modem Control Signal 3
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (SCLK ↓ )
Symbol
Min.
Max.
Unit
tSDPLLI
—
5tCK + 250
ns
After DPLL error detected
SCLK
tSDPLLI
IRQ
(21) Input Modem Control Signal 4
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQT ↑ delay (SCLK, TCLK ↑ )
Symbol
Min.
Max.
Unit
tSTIMI
—
5tCK + 250
ns
Timer count completed
SCLK
TCLK
tSTIMI
IRQT
23
MB89374
(22) Interrupt Request Signal 1 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ delay (WR#, DS# ↑ – MCR)
Symbol
Min.
Max.
Unit
tSMCRI
—
3tCK
ns
CS#, A4 to A0
MCR selected
Manipulating DDCDIE, DCTSIE, or DCIIE bit
WR# (DS#)
tSMCRI
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
(23) Interrupt Request Signal 2 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↓ delay (WR#, DS# ↑ – MSR)
CS#,A4 to A0
Symbol
Min.
Max.
Unit
tSMSRI
—
3tCK
ns
MSR selected
Manipulating DDCD, DCTS, or DCI bit
WR# (DS#)
tSMSRI
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
24
MB89374
(24) Interrupt Request Signal 3 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
Unit
IRQ delay (WR#, DS# ↑ –BPCR)
tSBPCRI
—
3tCK
ns
CS#, A4 to A0
BPCR selected
Manipulating DPLLERIE, or BRGOUTIE bit
WR# (DS#)
tSBPCRI
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
(25) Interrupt Request Signal 4 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↓ delay (WR#, DS# ↑ –BPSR)
CS#, A4 to A0
Symbol
Min.
Max.
Unit
tSBPSRI
—
3tCK
ns
BPSR selected
Manipulating DPLLER, or BRGOUT bit
WR# (DS#)
tSBRSRI
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
25
MB89374
(26) Interrupt Request Signal 5 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
Unit
IRQ ↓ delay (WR#, DS# ↑ –RXCR)
tSRXCRI
—
4tCK
ns
CS#, A4 to A0
RxCR selected
Manipulating STC bit
WR# (DS#)
tSRXCRI
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
(27) Interrupt Request Signal 6 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↓ delay (WR#, DS# ↑ –RXSR0)
CS#, A4 to A0
Symbol
Min.
Max.
Unit
tSRXSR0I
—
3tCK
ns
RxSR0 selected
Manipulating DIDL bit
WR# (DS#)
tSRXSR0I
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
26
MB89374
(28) Interrupt Request Signal 7 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
Unit
IRQ ↓ delay (WR# DS# ↑ –RXSR1)
tSRXSRXI
—
3tCK
ns
CS#, A4 to A0
RxSR1 selected
Manipulating GAPDET, LOOPER, or DLOC bit
WR# (DS#)
tSRXSR1I
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
(29) Interrupt Request Signal 8 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ delay (WR#, DS# ↑ –RXIER)
CS#, A4 to A0
Symbol
Min.
Max.
Unit
tSRXIERI
—
3tCK
ns
RxIER selected
Manipulating various interrupt enable bits
WR# (DS#)
tSRXIERI
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
27
MB89374
(30) Interrupt Request Signal 9 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
Unit
IRQ ↓ delay (WR#, DS# ↑ –TXSR)
tSTXSRI
—
3tCK
ns
CS#, A4 to A0
TxSR selected
Manipulating LATE, TxU, TxEND, or TxCOUT bit
WR# (DS#)
tSTXSRI
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
(31) Interrupt Request Signal 10 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ delay (WR#, DS# ↑ –TXIER)
CS#, A4 to A0
Symbol
Min.
Max.
Unit
tSTXIERI
—
3tCK
ns
TxIER selected
Manipulating various interrupt enable bits
WR# (DS#)
tSTXIERI
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
28
MB89374
(32) Interrupt Request Signal 11 by Manipulation of Each Interrupt
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
IRQ ↓ delay (WR#, DS# ↑ –SDR)
tSSDRWI1
—
4tCK
IRQ ↓ delay (WR#, DS# ↑ –SDR)
tSSDRWI2
—
5tCK
CS#, A4 to A0
Unit
ns
SDR selected
WR# (DS#)
tSSDRWI2
tSSDRWI1
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
(33) Interrupt Request Signal 12 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
IRQ ↓ delay (WR#, DS# –SDR) ↓
tSSDRRI1
—
4tCK
IRQ ↓ delay (WR#, DS# –SDR) ↓
tSSDRRI2
—
5tCK
CS#, A4 to A0
Unit
ns
SDR selected
RD#(DS#)
tSSDRRI2
tSSDRRI1
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
29
MB89374
(34) Interrupt Request Signal 13 by Manipulation of Each Interrupt Cause
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ delay (WR#, DS# ↑ –TCR)
Symbol
Min.
Max.
Unit
tSTCRI
—
3tCK
ns
CS#, A4 to A0
TCR selected
WR# (DS#)
tSTCRI
IRQ
Parameters in parentheses should be ignored when the FORMAT# pin is HIGH and referenced when it is LOW.
(35) SCLK Input
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
External clock period
tSCLK
100
—
LOW-level external clock pulse duration
tSCLKL
40
—
HIGH-level external clock pulse duration
tSCLKH
40
—
tSCLK
tSCLKH
tSCLKL
SCLK
tf
30
tr
Unit
ns
MB89374
(36) TCLK Input
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Symbol
Min.
Max.
Timer clock period
tTCLK
100
—
LOW-level timer clock pulse duration
tTCLKL
40
—
HIGH-level timer clock pulse duration
tTCLKH
40
—
Unit
ns
tTCLK
tTCLKH
tTCLKL
TCLK
tf
tr
31
MB89374
(37) Transmit Clock and Transmit Data
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (TXC# ↓ )
(Note 1)
Symbol
Min.
Max.
tSTXRDYL
—
6tCK
TXCI# clock period
tSTXCW
4tCK
(Note 2)
—
LOW-level TXCI# clock pulse duration
tSTXCL
1tCK + 40
(Note 3)
—
HIGH-level TXCI# clock pulse duration
tSTXCH
1tCK + 40
(Note 3)
—
TXD delay (TXC#)
tSTXDD
—
100
LOC# delay (TXC#)
tSLOCD
—
100
Unit
ns
Notes: 1. TxC# denotes TXCI# or TxCO#; RxC# denotes RxCI# or RxCO#
2. In LOOP mode: if NRZ or NRZI code, the minimum level is 8 tCK; if FM0, FM1, or Manchester code,
the minimum level is 12 tCK.
3. In LOOP mode: if NRZ or NRZI code, the minimum level is 3 tCK+40; if FM0, FM1, or Manchester code,
the minimum level is 5 tCK+40.
tSTXCW
tSTXCH
TXCI#, TXC O#
tSTXDD
tSTXDD
*1
TXD *2
tSLOCD
LOC#
tSTXRDYI
IRQ
*1: No change if NRZ or NZRI code
*2: When the Send High (SH) or Send Break (SB) bit of the TxCR register is enabled, output is assumed after a
maximum of 3 tCK from the rising edge of WR# (DS#).
32
MB89374
(38) Receive Clock and Receive Data
(VCC = +5 V ±10%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
IRQ ↑ delay (RXC# ↑ )
(Note 1)
Symbol
Min.
Max.
tSRXRDYI
—
4tCK
RXCI# clock period
tSRXCW
4tCK
(Note 2)
—
LOW-level RXCI# clock pulse width
tSRXCL
1tCK + 40
(Note 3)
—
HIGH-level RXCI# clock pulse width
tSRXCH
1tCK + 40
(Note 3)
—
RXD setup time (RXC#)
tSRXDS
0
—
RXD hold time (RXC#)
tSRXDH
160
—
tFD
—
3tCK
FD# output delay (RXC#)
Unit
ns
Notes: 1. Interrupt timing due to RXRDY bit, receive errors (CRCER, OER, SFER), frame termination (EOF, ADET)
2. In LOOP mode: if NRZ or NRZI code, the minimum level is 8 tCK; if FM0, FM1, or Manchester code, the
minimum level is 12 tCK.
3. In LOOP mode: if NRZ or NRZI code, the minimum level is 3 tCK+40; if FM0, FM1, or Manchester code,
the minimum level is 5 tCK+40.
tSRXCW
tSRXCL
tSRXCH
RXCI, RXCO#
tSRXDS
tSRXDH
tSRXDS
tSRXDH
*
tSRXDS
tSRXDH
*
RXD
tFD
FD#
tSRXRDYI
IRQ
*
When FM0 and FM1 code, the first value of the data bit must be defined.
33
MB89374
■ FUNCTIONAL OVERVIEW
1. DLC Position in Systems
(1) Supported Range of OSI Models
The DLC supports the HDLC-recommended frame format function for Layer 2 (Data Link Layer) of the seven
layers of OSI models. It also supports the X.21 bis-recommended modem control interface for Layer 1 (Physical
Layer).
Layer 7
Application Layer
Layer 6
Presentation Layer
Layer 5
Session Layer
Layer 4
Transport Layer
Layer 3
Network Layer
Layer 2
Data Link Layer
Layer 1
Physical Layer
Range supported by DLC
(2) Typical System Configuration
Figure 1 shows a typical system configuration using the DLC.
Fig. 1 Typical System Configuration
CPU
ROM
Interrupt controller
RAM
DLC
Communications channel
DMAC
34
MB89374
2. Functional Description
When it is used in microcomputer systems, the DLC manages the serial communications interface by controlling
the transfer of Bit Oriented Protocol (BOP) serial data in full-duplex communications.
At receiving, it compares the addresses in the HDLC frame input from the communications line, checks the
Frame Check Sequence (FCS), and deletes 0s in frames.
If the addresses match, the DLC receives the frame, in which case the address is accepted as part of the received
data. If the addresses do not match, the DLC ignores the frame.
When CRC is enabled, the DLC checks the FCS in the received frame and indicates the results in the status
register. In this case, the FCS data is not accepted as part of the received data. When CRC is disabled, the
DLC does not check the FCS, but handles it as part of the received data.
At transmitting, the DLC sends the flag pattern, generates and adds the FCS, and inserts 0s in the frame.
Addresses are not sent automatically .
35
36
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A2
Address
A3
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A1
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
A0
BRG2 divide value
BRG2 control
BRG2 status
BRG1 divide value
BRG1/DPLL control
BRG1/DPLL status
Mask
Request
Port
Transmit mode
Transmit flag 1
Transmit flag 0
Transmit byte counter 1
Transmit byte counter 0
Serial data
Transmit interrupt enable
Transmit control
Transmit status
Receive interrupt enable
Receive control
Receive status 1
Receive status 0
Modem control
Modem status
Character 1
Character 0
Transfer mode
CRC select
Protocol select
Register Name
BG2DR
B2CR
B2SR
BG1DR
B1PCR
B1PSR
MASKR
REQR
PORTR
SMR3
TXFR1
TXFR0
TXBCR1
TXBCR0
SDR
TXIER
TXCR
TXSR
RXIER
RXCR
RXSR1
RXSR0
MCR
MSR
CHRR1
CHRR0
SMR2
SMR1
SMR0
Abbreviation
DIV7
BRG2CLK
Unused
DIV7
DPLLERIE
Unused
MTXDRQ
TXDRQ
PI0
Unused
FOUT
N7
D15
D7
D7
TXD/I
TXE
LATE
RXD/I
RXE
GAPDET
ADET
DDCDIE
Unused
A15/D7
A7
TURN
Unused
Unused
bit7
DIV6
BRG2OUTIE
Unused
DIV6
TS
Unused
MRXDRQ
RXDRQ
PI2
TXBRGEN
Unused
N6
D14
D6
D6
Unused
SH
Unused
GAPDETIE
Unused
FDET/LOOPER
EOF
DCTSIE
DCI
A14/D6
A6
CODE2
Unused
Unused
bit6
No Access
Reserved
DIV5
BRG2EN
Unused
Reserved
DIV5
BRG1OUTIE
Unused
Unused
Unused
PI1
FD/DTR
Unused
N5
D13
D5
D5
Unused
SB
Unused
LOOPERIE
Unused
DLOC
SFER
DCIIE
DI
Reserved
A13/D5
A5
CODE1
Unused
Unused
bit5
*Access (read/write) to ’reserved’ register locations is inhibited. Allocating other peripheral LSI registers to these locations is also inhibited.
0:LOW level, 1:HIGH level, X:Don’t Care
A4
CS#
DIV4
BRG2G
Unused
DIV4
BRG1G
Unused
Unused
Unused
PI0
NRZIM
Unused
N4
D12
D4
D4
TXCOUTIE
IDLS
TXCOUT
DLOCIE
Unused
LOC
OER
Unused
DSR
A12/D4
A4
CODE0
PRS
Unused
DIV3
N3
Unused
DIV3
N3
Unused
Unused
Unused
PO3
TXCSM
N3
N3
D11
D3
D3
TXENDIE
TXRST
TXEND
ENDIE
Unused
Unused
CRCER
CTSAUTO
DDCD
A11/D3
A3
RXC1
CRCM1
PS3
bit3
Bit Configuration
bit4
bit2
DIV2
N2
Unused
DIV2
N2
Unused
MMODEM
IMODEM
PO2
TXCOUTEND
N2
N2
D10
D2
D2
LATEIE
SA
TXEMP
ERRIE
Unused
RBL2
RXIDL
Unused
DCTS
A10/D2
A2
RXC0
CRCM0
PS2
bit1
DIV1
N1
Unused
DIV1
N1
DPLLER
MTX
ITX
PO1
TXUEND
N1
N1
D9
D1
D1
TXUIE
OFD
TXU
DIDLIE
HUNT
RBL1
DIDL
DTR
DCD
A9/D1
A1
TXC1
Unused
PS1
bit0
DIV0
N0
BRG2OUT
DIV0
N0
BRG1OUT
MRX
IRX
PO0
TXLASTEND
N0
N0
D8
D0
D0
RXRDYIE
TXLAST
TXRDY
RXRDYIE
STC
RBL0
RXRDY
RTS
CTS
A8/D0
A0
TXC0
Unused
PS0
MB89374
■ REGISTER LIST
MB89374
■ DATA FORMAT
1. Receiving
Figure 2 shows the receive data format supported by the DLC.
Fig. 2 Receive Data Format
Opening flag
(01111110)
Address field
(A)
1 or 2 bytes
Control field (A)
1 or 2 bytes
Information field
(I)
n bytes
Frame check sequence
(FCS)
2 bytes
Closing flag
(01111110)
Data to be read from DLC when CRC enabled
Data to be read from DLC when CRC disabled
• The data in the address field is always read from the DLC regardless of whether address comparison is specified.
• When CRC is enabled, the FCS data is used only for the CRC check and is not read from the DLC.
• The data in the control and information fields can be read from the DLC.
2. Transmitting
Figure 3 shows the transmit data format supported by the DLC.
Fig. 3 Transmit Data Format
Opening flag
(01111110)
Address field
(A)
1 or 2 bytes
Control field (A)
1 or 2 bytes
Information field
(I)
n bytes
Frame check sequence
(FCS)
2 bytes
Closing flag
(01111110)
Data to be read from DLC when CRC enabled
Data to be read from DLC when CRC disabled
• The data in the address field is written as the transmit data to the DLC.
• When CRC is enabled, the FCS data is transmitted automatically to the DLC.
• The data in the control and information fields can be written to the DLC.
37
MB89374
■ APPLICATION EXAMPLES
1. Example of System Configuration
System System
address bus data bus
System
control bus
MBL8088
M889237A
HOLD
HLDREQ
HLDA
HLDACK
CLOCK
ADSTB
READY
A8 to A15
A16/S3 to A19/S6
ALE
Address latch
AD0 to AD7
Address latch
Address
latch
System clock
Ready signal generator
AEN
DB7 to DB0
RD#, WR#, M/IO#
END#
A7 to A0 DMAACK0
IR#, IW# DMAACK1
INTA#
CLK
INTR
RESET
Address
decoder
RST
DMAREQ0
CS#
DMAREQ1
TXDRQ/P02
CS#
CS#
INT
INTA#
RXDRQ/P03
TXDACK#/P12
D7 to D0
A4 to A0 RXDACK#/P13
TXLAST#/CI#
A0
RD#, WR#
D7 to D0
SCLK/DSR#
BRG1 source clock
TCLK
BRG2 source clock
RD#/DS#
WR#/R/W#
IR1
IRQT
IR0
IRQ
TXD
RXD
FORMAT#
RESET#
CLK
M89259A
System reset
System reset#
System clock
38
M889374
Serial channel
MB89374
2. Example of Application Software
An example of how to use the DLC is shown below.
(1) Operating Conditions
• BRG1 is used as the receive clock.
• BRG2 is used as the transmit clock.
(2) Flowchart
• Initial settings
BRG1 setting
BRG2 setting
Transfer mode setting
Receive processing
or
BR1DR ⇐ Divide value
B1PCR ⇐ Prescale value
BRG1G bit ⇐ 1
BG2DR ⇐ Divide value
B2PCR ⇐ Prescale value BRG2G bit ⇐ 1
BRG2EN bit ⇐ 1
SMR0 ⇐ Protocol and address detection method
SMR1 ⇐ Selection of CRC
SMR2 ⇐ Transfer clock and code
SMR3 ⇐ TxBRGEN bit ⇐ 1
CHRR0 ⇐ Address
CHRR1 ⇐ Address
transmit processing
39
MB89374
• Receiving Flow
Receive processing
RxCR ⇐ Reception enable
Enabling reception
RxSR0 ⇐ Status check
RXRDY = “0” or “1”
End of frame
Error
RXRDY = “0”
Status?
Error processing
RXRDY = “1”
Reading receive data
No
End of framing?
Yes
Processing received frame
Yes
Processing
continued?
No
Return
40
SDR ⇐ Receive data
MB89374
• Transmitting Flow
Send (transmit)
TxCR ⇐ Transmission enable
Enabling sending
(transmitting)
TXRDY = “0”
TxSR0 ⇐ Status check
TXRDY = “0” or “1”
Error
Status?
Error processing
TXRDY = “1”
Yes
End of framing?
No
Writing transmit data
Yes
Specifying end of frame
TxCR ⇐ T LAST = “1”
Writing transmit data
SDR ⇐ Transmit data
Processing
continued?
No
Return
41
MB89374
■ USAGE PRECAUTIONS
1. Reserved addresses in register map
Do not access reserved addresses or allocate the registers of other LSIs to these addresses.
2. Protocol select register, CRC select register, and transfer mode register
Always set these registers before enabling transmission or reception.
3. Transmit and receive interrupt enable registers
Do not enable interrupts for the TxRDY bit or RxRDY bit when making DMA requests.
4. Using BRG1 or BRG2 as interval timer
When using BRG1 or BRG2 as an interval timer, do not set 0s at all the bits of the BRG1 divide value register
(BG1DR) or the BRG2 divide value register (BG2DR).
5. Using BRG as transfer clock
When using BRG as a transfer clock, always set the division value at the BRG1 or BRG2 register before setting
the clock source with the transfer mode register (SMR2). For details on the setting procedure, refer to the
MB89374 User’s Manual.
■ ORDERING INFORMATION
42
Part number
Package
MB89374P-SH
42-pin plastic SH-DIP
(DIP-42P-M02)
MB89374PFQ
48-pin plastic QFP
(FPT-48P-M13)
Remarks
MB89374
■ PACKAGE DIMENSIONS
42 pin, Plastic SH-DIP
DIP-42P-M02
+0.20
38.35 –0.30
+.008
1.510 –.012
INDEX-1
13.80±0.25
(.543±.010)
INDEX-2
0.51(.020)MIN
5.25(.207)MAX
0.25±0.05
(.010±.002)
3.00(.118)MIN
+0.50
1.00 –0
+.020
.039 –0
1.778±0.18
(.070±.007)
1.778(.070)
MAX
C
1994 FUJITSU LIMITED D42007S-3C-3
0.45±0.10
(.018±.004)
15.24(.600)
TYP
15°MAX
35.56(1.400)REF
Dimensions in mm (inches).
(Continued)
43
MB89374
48 pin, Plastic QFP
FPT-48P-M13
13.10±0.40 SQ
(.516±.016)
10.00±0.20 SQ
(.394±.008)
36
2.35(.093)MAX
0(0)MIN
(STAND OFF)
25
37
Details of "A" part
24
0.15(.006)
8.80
(.346)
REF
INDEX
11.50±0.30
(.453±.012)
0.20(.008)
0.18(.007)MAX
0.53(.021)MAX
"A"
48
13
Details of "B" part
LEAD No.
1
0.80(.0315)TYP
12
0.30±0.10
(.012±.004)
0.16(.006)
M
0.15±0.05
(.006±.002)
0~10°
"B"
0.80±0.30
(.031±.012)
0.10(.004)
C
44
1994 FUJITSU LIMITED F48023S-1C-1
Dimensions in mm (inches).
MB89374
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3753
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281 0770
Fax: (65) 281 0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9703
 FUJITSU LIMITED
48
Printed in Japan