E2U0036-28-81 ¡ Semiconductor ¡ Semiconductor MSM7583 This version: Aug. 1998 MSM7583 Previous version: Nov. 1996 p/4 Shift QPSK MODEM GENERAL DESCRIPTION The MSM7583 is a CMOS IC for the p/4 shift QPSK modem developed for the digital cordless telephone systems. The device, which contains one system of modulator and two systems of demodulater, is optimized for applications for cell stations in a cordless telephone system. FEATURES • Single +5 V Power Supply: 4.5 V to 5.5 V (Modulator Block) • Built in Root Nyquist Filter for Baseband Limitting (50% Roll-off) • Ramp Bit for Burst Signal Rise-up (Fall-down) : 2 Symbols • Built-in D/A converters for Analog Outputs of Quadrature Signal I/Q Components and I 2 + Q 2 (Analog) Power Envelope Output. • Differential I/Q Analog Output Type • I/Q Output, DC Offset/Amplitude Adjustable (Demodulator Block) • Built-in Diversity-corresponding Demodulation Circuit: 2 Systems • Full Digital p/4 Shift QPSK Demodulation System • Input IF Signal Frequency Selectable: 1.2/10.7/10.75/10.8 MHz • Built-in Clock Recovery: 4 Circuits • Transmit/Receive Independent Power-down Control capability • Built-in Precise Analog Voltage Reference • MCU Serial Interface for Mode Setting and Built-in Test Circuit • Test Modes: Eye Pattern/AFC Compensating Signal/Phase Detection Signal Monitoring Capability • Transmission Speed: 384 kbps • Low Power Consumption Operating Mode: 16 mA Typ./Modulator (VDD = 5.0 V) 28 mA Typ./Demodulator (VDD = 5.0 V) Whole Power-down Mode: 0.03 mA Typ. (VDD = 5.0 V) • Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK)(Product name : MSM7583GS-BK) 1/23 ¡ Semiconductor MSM7583 BLOCK DIAGRAM VDD DGND AGND SLS11 SL41 SL41 SL41 SL41 SLS21 AFC1 RXD1 IFIN1 Phase Detector Delay Detector AFC Decision RXC1 RXSC1 MCK IFCK S E L IFSEL0 (From CR) RCW1 RPR1 IFSEL1 (From CR) SL11 To each block D X2 E SL31 S E L DPLL C X1 DEN EXCK DIN DOUT SL21 SL41 S E L Control Register RXD0 RXC0 RXSC0 SL11 RXSEL D To each block E C PDN0 PDN1 PDN2 RESET SL21 S E L DPLL SL31 SL41 RPR2 RCW2 Delay Detector SL12 SL22 RXCS2 RXC2 RXD2 Decision AFC SL42 Phase Detector SL32 IFN2 AFC2 SLS21 SLS22 BST0 I+ +1 I– –1 Q+ +1 Q– –1 ENV +1 DC Offset Adjust DC Offset Adjust LPF D/A I output gain adjust LPF D/A 3.84 MHz To D/A Q output gain adjust S E L LPF VREF D/A To monitor output of each block TXCI PLL 1/10 SG TXD TXW S/P MAPPING Root Nyquist LPF 384 kHZ TXCO TXCEL (From CR) TEST1, TEST0 (From CR) To internal SG 2/23 ¡ Semiconductor MSM7583 49 RXD2 50 RXC2 51 RXSC2 52 RXSEL 53 RXD0 54 RXC0 55 RXSC0 56 RCW1 57 AFC1 58 RPR1 59 RCW2 60 AFC2 61 RPR2 62 X1 63 X2 64 NC PIN CONFIGURATION (TOP VIEW) NC 1 48 NC IFCK 2 47 SLS22 MCK 3 46 SLS12 DGND 4 45 RXSC1 IFIN2 5 44 RXC1 DGND 6 43 RXD1 IFIN1 7 42 SLS21 DGND 8 41 SLS11 VDD 9 40 VDD DOUT 10 39 ENV NC 32 NC 31 NC 30 NC 29 NC 28 33 AGND NC 27 PDN1 16 NC 26 34 SG NC 25 PDN0 15 NC 24 35 I+ TXCI 23 RESET 14 TXCO 22 36 I– TXD 21 DEN 13 TXW 20 37 Q+ BSTO 19 EXCK 12 PDN2 18 38 Q– NC 17 DIN 11 64-Pin Plastic QFP NC : No connect pin 3/23 ¡ Semiconductor MSM7583 PIN AND FUNCTIONAL DESCRIPTIONS TXD Transmit data input for 384 kbps. TXCI Transmit clock input. When the control register CR0 - B6 is “0”, a 384 kHz clock pulse synchronous with TXD should be input to this pin. This clock pulse should be continuous because this device uses APLL to generate internal clock pulses. When CR0 - B6 is “1”, a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz clock pulse is applied to TXCI, TXCO outputs a 384 kHz clock pulse, which is generated by dividing the TXCI input by 10. The transmit data, synchronous 384 kHz clock pulse, should be input to the TXD. In this case the device does not use APLL, and the 3.84 MHz clock pulse need not be continuous. (Refer to Fig. 1.) TXCO Transmit clock output. When CR0 - B6 is “0”, TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring purposes. When CR0 - B6 is “1”, this pin outputs a 384 kHz clock pulse generated by dividing the TXCI input by 10. (Refer to Fig. 1.) TXW Transmit data window signal input. The transmit timing signal for the burst data is input to the device through this pin. If TXW pin is “1”, modulation data is output. (Refer to Fig. 1.) I+, I– Quadrature modulation signal I component differential analog outputs. The level of the outputs is 500 mVpp with 1.6 Vdc as center value. The output pin load conditions are: R ≥ 10 kW, C £ 20 pF. The gain of these pins can be adjusted using the control registers CR1 - B7 to B4, and the offset voltage at the I– pin can be adjusted using CR3 - B7 to B3. Q+, Q– Quadrature modulation signal Q component differential analog outputs. The level of the outputs is 500 mVpp with 1.6 Vdc as center value. The output pin load conditions are: R ≥ 10 kW , C £ 20 pF. The gain of these pins can be adjusted using the control registers CR1 - B3 to B0, and the offset voltage at the Q– pin can be adjusted using CR4 - B7 to B3. 4/23 ¡ Semiconductor MSM7583 ENV Quadrature modulation signal envelope ( I 2 + Q 2 ) output. Its output level is 500 mVpp with 1.6 Vdc as a center value. The output pin load conditions are: R ≥ 10 kW , C £ 20 pF. The gain of this output can be adjusted using the control registers CR2 - B7 to B4. This pin is also used to monitor eye pattern, AFC compensating signal, and phase detection of the demodulator block during the test mode. Refer to the description of the control register for details. BSTO Modulation burst window signal output. The burst position for the I/Q baseband modulation output is output. (Refer to Fig. 1.) (1) CR0 - B6 ="0". TXD TXCI (384 kHz) TXW TXCO (384 kHz) I, Q D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13 Dn-1 Dn Ramp rise-up 2 symbols Ramp fall-down 2 symbols Delay of 6.25 symbols Delay of 6.25 symbols (2) CR0 - B6 ="1". TXD TXCI (3.84 MHz) TXW TXCO (384 kHz) I, Q D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13 Dn-1 Dn Ramp rise-up 2 symbols Delay of 6.25 symbols TXCI (384 kHz) 1 2 8 9 10 Ramp fall-down 2 symbols Delay of 6.25 symbols N N+1 N+2 N+16 N+17 N+18 N+19 TXW BSTO Figure 1 Transmitter Timing Diagram 5/23 ¡ Semiconductor MSM7583 SG Internal reference voltage output. The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin and the AGND pin. The external SG voltage, if necessary should be used via buffer. RESET Control register reset. When this pin is set to "0", the register is reset to the initial value. The reset signal input width is 200 ns or more. PDN0, PDN1, PDN2 Inputs for power-down control. PDN0 controls the standby/communication modes, PDN1 controls the modulator, and PDN2 controls the demodulator. Refer to Table 1 for details. Table 1 Power Down Control PDN0 PDN1 PDN2 Standby Mode Communication Mode Function Mode 0 — 0 All power-down. Mode A 0 — 1 Modulator power is off (VREF and PLL power is also off). Demodulator power is on. Mode B 1 0 0 Modulator power is off (VREF and PLL power is on). I and Q outputs are in a high-impedance state. Only demodulator clock recovery block power is on. Mode C 1 1 0 Modulator power is on. Only demodulator clock recovery block power is on. Mode D 1 0 1 1 1 1 Modulator power is off (VREF and PLL power is on). I and Q outputs are in a high-impedance state. Demodulator power is on. Modulator power is on. Demodulator power is on. Mode E Mode F VDD +5 V power supply voltage. AGND Analog signal ground. DGND Digital signal ground. AGND and DGND are not connected in the device. This pin should be tied to the AGND pin on the PCB as close as possible from the device. AGND and DGND should be connected as close as prossible on the PC board. 6/23 ¡ Semiconductor MSM7583 MCK Master clock input. The clock frequency is 19.2 MHz. IFIN1, IFIN2 Modulated signal inputs for the demodulator block. Select the IF frequency from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz based on CR0 - B4 and B3. IFIN1 is for Channel 1, and IFIN2 for Channel 2. IFCK Clock signal input for demodulator block IF frequency (10.7 MHz or 10.75 MHz). If the IF frequency is 10.7 MHz, 19.0222 MHz should be supplied. When it is 10.75 MHz, 19.1111 MHz should be supplied. When the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to “0” or “1”. (Refer to Fig. 2.) X1, X2 Crystal oscillator connection pins. When supplying a 19.0222 MHz or 19.1111 MHz clock to IFCK, use these pins. (Refer to Fig. 2.) When IFIN = 10.7 MHz or 10.75 MHz When IFIN = 1.2 MHz or 10.8 MHz MSM7583 X1 X2 MSM7583 IFCK X1 X2 IFCK 19.0222 MHz or 19.1111 MHz Figure 2 How to Use IFCK, X1, and X2 7/23 ¡ Semiconductor MSM7583 RXD1, RXC1, RXSC1 Channel 1 receive data, receive clock, and receive symbol clock output pins. During power-on, these output pins are at the output level of the clock recovery circuit selected by a combination of SLS11 and SLS21 (described later). (Refer to Fig. 3.) RXD2, RXC2, RXSC2 Channel 2 receive data, receive clock, and receive symbol clock output pins. During power-on, these output pins are at the output level of the clock recovery circuit selected by a combination of SLS12 and SLS22 (described later). (Refer to Fig. 3.) SLS11, SLS21, SLS12, SLS22 Receiver slot select signal pins of Channel 1 (SLS11, SLS21) and Channel 2 (SLS12, SLS22). The MSM7583 has four sets of clock recovery circuits and four AFC information storage registers. One of the sets is selected according to a combination of the signals at these pins. (Refer to Fig. 3.) Channel 1 (SLS21, SLS11) = (0, 0): Slot 1, (0, 1): Slot 2 (1, 0): Slot 3, (1, 1): Slot 4 Channel 2 (SLS22, SLS12) = (0, 0): Slot 1, (0, 1): Slot 2 (1, 0): Slot 3, (1, 1): Slot 4 RXD1 (RXD2) RXC1 (RXC2) RXSC1 (RXSC2) SLS21 (SLS22) SLS11 (SLS12) The recovery data and clock pulse are selected asynchronously by the SLS signals. Figure 3 RXD, RXC, and RXSC Timing Diagram RXD0, RXC0, RXSC0 Receive data, receive clock, and receive symbol clock outputs. These pins are at the output level selected by RXSEL (described below). 8/23 ¡ Semiconductor MSM7583 RXSEL Receive data, receive clock, and receive symbol clock select signal. If this pin is set to "0", the output levels of Channel 1 RXD1, RXC1, and RXSC1 are selected to be output to RXD0, RXC0, and RXSC0. If this pin is set to "1", the output levels of Channel 2 RXD2, RXC2, and RXSC2 are selected to be output to RXD0, RXC0, and RXSC0. Note that a hazard may sometime occur in RXDO, RXCO, and RXSCO because RXSEL selects asynchronously. RPR1, RPR2 High-speed phase clock control signal input pin for the clock recovery circuit. When each of the pins is “1”, the clock recovery circuit starts in the high-speed phase clock mode. When the phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically. When each of the pins is “0”, the circuit is always in the lowspeed phase clock mode. RPR1 is for Channel 1, and RPR2 for Channel 2. AFC1, AFC2 AFC operation range specification signal inputs. As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to “1”. AFC operation starts at a certain period after the AFC information is reset. When RPR is set to “1”, an average number of times that AFC sets to on is low. When RPR is “0”, it is high. When AFC is “0”, frequency error is not calculated, but the frequency is corrected using an error that is held. AFC1 is for Channel 1, and AFC2 for Channel 2. RCW1, RCW2 Clock recovery circuit operation ON/OFF control signal inputs. When this pin is “0”, DPLL does not make any phase corrections. RCW1 is for Channel 1, and RCW2 for Channel 2. (CASE1) AFC RPR Average number of times AFC information Average AFC is high. is reset. number of times AFC is low. AFC information is maintained. (CASE2) AFC RPR “0” Average number of times The clock recovery AFC is high. circuit starts with the previous AFC information. AFC information is maintained. Figure 4 AFC Control Timing Diagram 9/23 ¡ Semiconductor MSM7583 DEN, EXCK, DIN, DOUT , , Serial control ports for the microprocessor interface. The MSM7583 contains a 6-byte control register. An external CPU uses these pins to read data from and write data to the control register. DEN is the "Enable" signal input pin. EXCK is a data shift clock pulse input pin. DIN is an address and data input pin. DOUT is a data output pin. Figure 5 shows an input/output timing diagram. DEN EXCK DIN W A2 A1 A0 DOUT B7 B6 B5 B4 B3 B2 B1 B0 B2 B1 B0 High Impedance (a) Data Write Timing Diagram DEN EXCK DIN DOUT R A2 High Impedance A1 A0 B7 B6 B5 B4 B3 (b) Data Read Timing Diagram Figure 5 MCU Interface Input/Output Timing Diagram 10/23 ¡ Semiconductor MSM7583 The register map is shown below Table 2 Control Register Map Register Address A2 A1 A0 Data B7 B6 B5 B4 B3 B2 B1 ENVPD TXCSEL MODOFF IFSEL1 IFSEL0 ENVSEL TEST1 Qch Qch Qch Ich Ich Ich Ich GAIN3 GAIN2 GAIN1 GAIN0 GAIN3 GAIN2 GAIN1 CR0 0 0 0 CR1 0 0 1 CR2 0 1 0 ENV GAIN3 CR3 0 1 1 CR4 1 0 0 CR5 1 0 1 ENV GAIN2 ENV GAIN1 ENV GAIN0 B0 R/W TEST0 Qch GAIN0 R/W R/W — — — R/W Ich Ich Ich Ich Ich Offset4 Offset3 Offset2 Offset1 Offset0 — — — R/W Qch Qch Qch Qch Qch Offset4 Offset3 Offset2 Offset1 Offset0 — — — R/W LOCAL INV0 ICT1 ICT0 R/W ICT7 ICT6 ICT5 ICT4 — LOCAL INV1 R/W : Read/Write enable 11/23 ¡ Semiconductor MSM7583 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit VDD — 0 to 7 V Digital Input Voltage VDIN — –0.3 to VDD + 0.3 V Storage Temperature TSTG — –55 to +150 °C Power Supply Voltage RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Symbol VDD (VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C) Condition Voltage must be fixed Min. Typ. Max. Unit 4.5 — 5.5 V –25 +25 +70 °C 2.2 — VDD V — 0.6 — MHz — kHz Operating Temperature Ta Input High Voltage VIH All digital input pins Input Low Voltage VIL All digital input pins 0 19.2 384 3.84 Master Clock Frequency Modulator Input Frequency — fMCK MCK — fTXC1 TXCI (when CR0 - B6 = "0") — — V fTXC2 TXCI (when CR0 - B6 = "1") Demodulator Input Frequency fIFCK1 IFCK (when IFIN = 10.7 MHz) –50 ppm 19.0222 MHz +50 ppm MHz fIFCK2 IFCK (when IFIN = 10.75 MHz) –50 ppm 19.1111 +50 ppm MHz Clock Duty Cycle DCCK MCK, IFCK, TXCI IF Input Duty Cycle DCIF IFCK 40 45 50 50 — 60 55 % % ELECTRICAL CHARACTERISTICS DC Characteristics Parameter Power Supply Current (VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C) Symbol Condition IDD1 Mode A (when VDD = 5.0 V) IDD2 Mode B (when VDD = 5.0 V) Min. — — IDD3 Mode C (when VDD = 5.0 V) — Typ. 0.03 25.0 8.5 IDD4 Mode D (when VDD = 5.0 V) — 16.0 32.0 mA IDD5 Mode E (when VDD = 5.0 V) — 56.0 70.0 mA V Max. 0.06 50.0 17.0 IDD6 Mode F (when VDD = 5.0 V) — 28.0 35.0 Output High Voltage VOH IOH = 0.4 mA 2.8 — VDD Output Low Voltage VOL IIH IOL = –1.6 mA Input Leakage Current IIL Unit mA mA mA mA 0.0 — 0.4 V — — — 10 mA — — — 10 mA 12/23 ¡ Semiconductor MSM7583 Analog Interface Characteristics Parameter (VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C) Condtion Symbol Min. Typ. Max. Unit Output Resistance Load RLIQ I+, I–, Q+, Q–, ENV 10 — — kW Output Capacitance Load CLIQ I+, I–, Q+, Q–, ENV — — 20 pF VDC1 I+, I–, Q+, Q– (TXW = 0) 1.55 1.6 1.65 V — 1.77 — V — 1.67 — V VDC2 Output DC Voltage Level VDC3 I+ (CR0 – B5 = 1) when not modulated Q+ (CR0 – B5 = 1) when not modulated VDC4 ENV (TXW = 0) — 1.35 — V VDC5 ENV (TXW = 1, CR0 – B2 = 0, TXD = 0) — 1.72 — V VDC6 ENV (TXW = 1, CR0 – B2 = 1, TXD = 0) — 1.63 — V 340 360 380 mVPP –20 — +20 mV I+, I–, Q+, Q– Output AC Voltage Level VAC Offset Voltage Difference VOFF Output DC Voltage Adjustment Level Range DCVL — — ±45 — mV Output AC Voltage Adjustment Level Range ACVL — — ±4 — % P600 600 kHz detuning (*) 60 — — dB P900 900 kHz detuning (*) 65 — — dB Out-of-band Spectrum Modulation Accuracy EVM Demodulator IF Input Level IFV IFIN Input Impedance (TXW = 0 continuous input) Difference among I+, I–, Q+, and Q– — IFIN input level — 1.0 3.0 % rms 0.5 — VDD VPP RIF — — 20 — kW CIF — — 5 — pF SG Output Voltage VSG — — 2.0 — V SG Output Impedance RSG — — 2 — kW SG warm-up Time TSG — 400 — ms SG´AGND 0.1 mF (Rise Time to 90% of max. level.) Modulator D/A Conversion Sampling Frequency Modulator D/A Conversion Offset Frequency FSDA — — 1.92 — MHz FCDA — — 380 — kHz * Power attenuation at 600 kHz or 900 kHz ±96 kHz as referred to two times of the power in frequency band of 0 to 96 kHz 13/23 ¡ Semiconductor MSM7583 Digital Interface Characteristics Parameter (VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C) Condtion Min. Typ. Max. Unit 200 — — ns 200 — — ns 0 — 200 ns 0 — 200 ns 0 — 200 ns 0 — 200 ns 10 — — ms tRW 10 — — ms tM1 50 — — ns tM2 50 — — ns tM3 50 — — ns Symbol Other tSX tXS tDS Transmitter Digital tDH Input/Output Setting Time tXD1 C load = 50 pF Fig. 6 tXD2 tXD3 tXD4 tRD1 Receiver Digital Input/Output Setting Time Serial Port Digital Input/Output Setting Time tRD2 tRS1 to C load = 50 pF Fig. 7 tRS4 tM4 50 — — ns tM5 100 — — ns 50 — — ns 50 — — ns tM6 C load = 50 pF Fig. 8 tM7 tM8 0 — 100 ns tM9 50 — — ns tM10 50 — — ns tM11 EXCK Clock Frequency fEXCK — EXCK 0 — 50 ns — — 10 MHz 14/23 ¡ Semiconductor MSM7583 TIMING DIAGRAM Transmit Data Input Timing TXCI [TXCO*] (384 kHz) 1 2 3 N-2 N-1 N N+1 tXS tSX tXS tSX TXW 1 2 3 N-2 ,,, ,,, ,,, ,,, TXD ,, ,,, ,,, , tDS tDH N-1 N *[ ]: When CR0 - B6 = "1", TXCO is indicated. Transmit Clock (TXCO) Output Timing (when CR0 - B6 = 1) TXCI (3.84 MHz) 2 1 3 4 5 tXD1 6 7 8 9 10 tXD2 tXD1 TXCO (384 kHz) Transmit Burst Position Output (BSTO) Timing TXCI (384 kHz) 1 2 9 10 N N+1 N+16 N+17 N+18 TXW tXD3 tXD4 BSTO Figure 6 Transmit (Modulator) Digital Input/Output Timing SLS1 SLS2 tRS1 tRS2 RCW tRS3 tRS4 AFC tRW RPR RXC tRD1 tRD2 RXD Figure 7 Receiver (Demodulator) Digital Input/Output Timing 15/23 ¡ Semiconductor MSM7583 DEN tM1 DIN tM3 2 3 4 tM6 tM4 W/R tM10 tM5 tM2 1 EXCK A2 5 6 11 12 tM9 tM7 A1 A0 B7 B1 B0 tM11 tM8 DOUT B7 B1 B0 Figure 8 Serial Control Port Interface 16/23 ¡ Semiconductor MSM7583 FUNCTIONAL DESCRIPTION Control Registers (1) CR0 (basic operation mode setting) B7 ENVPD CR0 Initial value (*) 0 B6 B5 B4 B3 B2 B1 B0 TXCSEL MODOFF IFSEL1 IFSEL2 ENVSEL TEST1 TEST0 0 0 0 0 0 0 0 * The initial value is set when a reset signal is supplied at RESET. B7: Transmit envelope output power down control 0/Envelope output ON 1/Envelope output OFF B6: Transmit timing clock selection 0/TXCI input: 384 kHz. TXCO output: 384 kHz output from APLL Transmit data TXD is input in synchronization with the rising edge of TXCI (APLL is on.) 1/TXCI input: 3.84 MHz. TXCO output: 384 kHz (one-tenth of the TXCI frequency) Transmit data TXD is input in synchronization with the rising edge of TXCO (APLL is off.) B5: Modulation on/off control 1/modulation OFF (with phase fixed) 0/modulation ON. B4, B3: Receiver input IF frequency selection (0, 0), (0, 1) : 1.2 MHz (1, 0) : 10.8 MHz (1, 1) : 10.7 MHz/10.75 MHz B2: Transmit envelope (I2 + Q2 or I 2 + Q 2 ) output selection When B1, B0 is (0, 0) : 0/ I 2 + Q 2 output 1/I2 + Q2 output When B1, B0 is other than (0, 0) : 0/Channel 1 receive monitor output 1/Channel 2 receive monitor output B1, B0: Test mode selection bits. Each monitor output is output to the transmit ENV pin. (0, 0): transmit envelope (I2 + Q2 or I 2 + Q 2 ) output (0, 1): receiver phase detection signal output (1, 0): receiver delay detection signal output (1, 1): receiver internal AFC information output 17/23 ¡ Semiconductor MSM7583 (2) CR1 (I, Q gain adjustment) CR1 Initial value B7 B6 B5 B4 B3 B2 B1 B0 Ich GAIN3 Ich GAIN2 Ich GAIN1 Ich GAIN0 Qch GAIN3 Qch GAIN2 Qch GAIN1 Qch GAIN0 0 0 0 0 0 0 0 0 B7 to B4: I+/I- output gain setting, in 3 mV steps (Refer to Table 3.) B3 to B0: Q+/Q- output gain setting, in 3 mV steps (Refer to Table 3.) (3) CR2 (ENV gain adjustment) CR2 Initial value B7 B6 B5 B4 B3 B2 B1 B0 ENV GAIN3 ENV GAIN2 ENV GAIN1 ENV GAIN0 — — — — 0 0 0 0 0 0 0 0 B7 to B4: ENV output gain setting, in 9 mV steps (Refer to Table 3.) B3 to B0: Not used Table 3 I, Q, and ENV Output Gain Values I and Q Amplitude CR1 B7 B6 B5 B4 (value relative to the reference (1.000) at (0, 0, 0, 0)) B3 B2 B1 B0 0 1 1 1 1.042 1.036 0 1 1 0 0 1 0 1 1.030 0 1 0 0 1.024 1.018 0 0 1 1 1.012 0 0 1 0 0 0 0 1 1.006 1.000 0 0 0 0 0.994 1 1 1 1 0.988 1 1 1 0 0.982 1 1 0 1 0.976 1 1 0 0 0.970 1 0 1 1 0.964 1 0 1 0 0.958 1 0 0 1 0.952 1 0 0 0 CR2 B7 B6 B5 B4 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 ENV Amplitude (value relative to the reference (1.000) at (0, 0, 0, 0)) 1.126 1.108 1.090 1.072 1.054 1.036 1.018 1.000 0.982 0.964 0.946 0.928 0.910 0.892 0.874 0.856 18/23 ¡ Semiconductor MSM7583 (4) CR3 (I– output offset voltage adjustment) CR3 Initial value B7 B6 B5 B4 B3 B2 B1 B0 Ich Offset4 Ich Offset3 Ich Offset2 Ich Offset1 Ich Offset0 — — — 0 0 0 0 0 0 0 0 B7 to B3: I– output pin offset voltage adjustment (Refer to Table 4.) B2 to B0: Not used (5) CR4 (Q– output offset voltage adjustment) CR4 Initial value B7 B6 B5 B4 B3 B2 B1 B0 Qch Offset4 Qch Offset3 Qch Offset2 Qch Offset1 Qch Offset0 — — — 0 0 0 0 0 0 0 0 B7 to B3: Q– output pin offset voltage adjustment (Refer to Table 4.) B2 to B0: Not used Table 4 I and Q Channel Offset Adjustment Values CR3, CR4 CR3, CR4 I and Q offset I and Q offset B7 B6 B5 B4 B3 (mV) B7 B6 B5 B4 B3 (mV) 0 1 1 1 1 +45 1 1 1 1 1 –3 0 1 1 1 0 +42 1 1 1 1 0 –6 0 1 1 0 1 +39 1 1 1 0 1 –9 0 1 1 0 0 +36 1 1 1 0 0 –12 0 1 0 1 1 +33 1 1 0 1 1 –15 0 1 0 1 0 +30 1 1 0 1 0 –18 0 1 0 0 1 +27 1 1 0 0 1 –21 0 1 0 0 0 +24 1 1 0 0 0 –24 0 0 1 1 1 +21 1 0 1 1 1 –27 0 0 1 1 0 +18 1 0 1 1 0 –30 0 0 1 0 1 +15 1 0 1 0 1 –33 0 0 1 0 0 +12 1 0 1 0 0 –36 0 0 0 1 1 +9 1 0 0 1 1 –39 0 0 0 1 0 +6 1 0 0 1 0 –42 0 0 0 0 1 +3 1 0 0 0 1 –45 0 0 0 0 0 0 1 0 0 0 0 –48 19/23 ¡ Semiconductor MSM7583 (6) CR5 (IC test) B7 CR5 Initial value B6 B5 B4 B3 B2 B1 B0 LOCAL INV0 ICT1 ICT0 0 0 0 ICT7 ICT6 ICT5 ICT4 LOCAL INV1 0 0 0 0 0 B7 to B4: ICT7 to ICT4. Device test control bits. B3, B2 : Local inverting mode setting bits. (Used when the phase of the demodulator IF input to this device is inverted.) (1, 1) = local inverting mode (0, 0) = normal mode B1, B0 : ICT1, ICT0. Device test control bits. Note: CR5 - B7 to B4, B1, and B0 are used to test the device. They should be set to “0” during normal operation. State Transition Time Note: The transition time is 1 ms or less unless otherwise stated 1 ms Mode A 5 ms Standby mode (PDN0 = 0) Mode B PDN1 = 0 PDN2 = 0 PDN1 = 0 PDN2 = 1 Communication mode (PDN0 = 1) 40 ms Mode D 5 ms Mode C PDN1 = 1 PDN2 = 0 Mode E PDN1 = 0 PDN2 = 0 PDN1 = 0 PDN2 = 1 40 ms 5 ms Mode F PDN1 = 1 PDN2 = 1 Figure 9 Power-Down State Transition Time 20/23 ¡ Semiconductor MSM7583 APPLICATION CIRCUIT Receive symbol clock output Demodulator 1 control signal Receive clock output Receive data output Receive channel select signal Demodulator 2 control signal Receive symbol clock 2 output Receive clock 2 output Burst window output Modulator data window Modulator input data VDD DOUT ENV DIN Q– EXCK Q+ DEN I– RESET I+ 47 Demodulator 2 control signal Receive symbol clock 1 output Receive clock 1 output 46 45 44 43 Receive data 1 output 42 Demodulator 1 control signal 41 40 39 38 VDD Modulator Q component output Modulator I component output 37 36 35 34 VDD 33 NC C3 C2 C1 32 NC NC NC NC 31 30 29 28 27 26 NC AGND NC SG PDN1 NC PDN0 48 To orthogonal modulator 50 51 49 RXD2 RXC2 RXSC2 52 RXSEL 53 RXD0 54 RXC0 56 55 RXSC0 57 AFC1 RCW1 58 RPR1 59 RCW2 60 AFC2 62 63 61 RPR2 X1 MSM7583GS-BK VDD NC 16 SLS11 17 Power down control signal 15 DGND 25 Reset signal 14 SLS21 TXCI 13 IFIN1 24 12 RXD1 TXCO Control register control signal 11 DGND 23 9 10 RXC1 TXD 8 IFIN2 22 VDD 7 RXSC1 21 Demodulator 1 IF input 6 DGND TXW C4 5 SLS12 20 Demodulator 2 IF input 4 MCK BSTO C5 SLS22 PDN2 19.2 MHz input NC IFCK 19 3 NC NC 2 18 1 X2 NC 64 Receive data 2 output C1 = 10 mF C2 = C3 = 0.1 mF C4 = C5 = 1000 pF Modulator 384 kHz input Figure 10 Example of Circuit Configuration 21/23 ¡ Semiconductor MSM7583 , , ,, Demodulator Control Timing Diagram (Example) Demodulator unit Modulator input data Slot 1 R1 G Slot 2 G Slot 3 R2 G Slot 4 R3 G R4 G Timing for CS PDN2 SLS2 "0" "0" "1" "1" SLS1 "0" "1" "0" "1" R1 R2 R3 R4 AFC RXD RXC 240 bits 625 ms (1) Control channel/synchronous burst (SS + PR = 64 bits) 64 bits RXD G G G G G G G G R R R R SS SS PR PR ------------- PR UW ------------- CR CR G G G G G G G G AFC RPR RCW 56 bits (2) Communication channel (SS + PR = 8 bits) RXD 8 bits G G G G G G G G R R R R SS SS PR PR ----- PR UW ------------- CR CR G G G G G G G G AFC RPR "0" RCW Loss than 30 bits G: Guard bit R: Ramp bit SS: Start symbol bit PR: Preamble bit UW: Unique word bit CR: CRC bit * AFC and RCW may be controlled at the same timing. 22/23 ¡ Semiconductor MSM7583 PACKAGE DIMENSIONS (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 23/23