ETC STK6036A

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Enhanced video driver for portable LCD
panels with analog I/F
STK 6036A．B
Specification
Version 1.0
August 28, 2006
Taipei Office
10F, No. 1, Alley 30, Lane 358, Rueiguang Road, Neihu District, Taipei, Taiwan R.O.C.
台北市內湖區瑞光路 358 巷 30 弄 1 號 10 樓
TEL: 886-2-26590055
FAX: 886-2-26590077
Hsinchu Office
3F, No. 24-2, Industry E. Road IV, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C.
新竹市科學工業園區工業東四路 24-2 號 3 樓
TEL: 886-3-5773181
FAX: 886-3-5778010
Caution!
The information in this document is subject to change without notice and does not represent a commitment on
part of the vendor, who assumes no liability or responsibility for any errors that may appear in this data sheet. No
warranty or representation, either expressed or implied, is made with respect to the quality, accuracy, or fitness for
any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special,
incidental or consequential damages arising from any defect or error in this data sheet or product. Product names
appearing in this data sheet are for identification purpose only, and trademarks and product names or brand names
appearing in this document are property of their respective owners. All rights reserved. No part of this data sheet
may be reproduced, transmitted, or transcribed without the expressed written permission of the manufacturer and
authors of this data sheet.
Specification
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Table of Contents
1
2
3
4
5
6
7
Product Overview.........................................................................................................................................3
Product Features ..........................................................................................................................................3
2.1
Support inputs.........................................................................................................................................3
2.2
Video decoder.........................................................................................................................................3
2.3
Video Scaling .........................................................................................................................................3
2.4
OSD ........................................................................................................................................................3
2.5
ADC auto gain and offset control...........................................................................................................3
2.6
sRGB processing ....................................................................................................................................3
2.7
Chroma coring for noise reduction .........................................................................................................4
2.8
Hardware TV sub-system detection........................................................................................................4
2.9
Support free-run mode if the sync signal is missing...............................................................................4
2.10 Built-in DC-DC switching control for high voltage generation and white LED panel...........................4
2.11 2-to-1 multiplexed 8-bit SAR-ADC support ..........................................................................................4
2.12 Built-in RGB output AMP for gain/offset control..................................................................................4
2.13 Low power consumption ~230mW (CCIR656 input with RGB AMP)..................................................4
2.14 64-LQFP/128-pin LQFP package...........................................................................................................4
Block Diagram ..............................................................................................................................................5
3.1
QFN Pin Descriptions.............................................................................................................................6
Functional Comparison................................................................................................................................9
Register Specification and Function Description.....................................................................................10
5.1
Analog registers....................................................................................................................................10
5.1.1
Analog front end slave addresses..................................................................................................10
5.1.2
PI-ADC I2C registers ...................................................................................................................10
5.2
Video Decoder......................................................................................................................................12
5.2.1
Video decoder slave addresses .....................................................................................................12
5.2.2
I2C registers..................................................................................................................................12
5.3
Miscellanies..........................................................................................................................................14
5.3.1
Misc. slave address .......................................................................................................................14
5.3.2
Misc. I2C registers........................................................................................................................14
5.4
Scaler Registers ....................................................................................................................................19
5.4.1
Scaler slave address ......................................................................................................................19
5.4.2
Scaler I2C registers.......................................................................................................................19
5.4.3
I2C Register for Scaler Input window ..........................................................................................19
5.4.4
I2C Register for Scalar .................................................................................................................21
5.4.5
I2C Register for Scaler Output Control ........................................................................................22
5.5
2D-Noise Reduction .............................................................................................................................24
5.6
I2C Register for LTI/CTI .....................................................................................................................26
5.7
I2C Register for sRGB .........................................................................................................................26
5.8
I2C Register for OSD ...........................................................................................................................28
5.9
PWM and DC-DC PWG control ..........................................................................................................30
5.9.1
PWM.............................................................................................................................................30
5.9.2
DC-DC PWG................................................................................................................................30
Electrical Characteristics...........................................................................................................................33
Package Outline ..........................................................................................................................................34
Specification
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1 Product Overview
The STK6036, is an one-chip video decoder with integrated scalar, OSD function, TCON, and DAC,
which can drives small size 3.5, 4, 5.6, 7, 8, 9, and up to 10-inch TFT-LCD panel with analog
interlace. For analog panels, STK6036 can support the display resolutions of 1920x468, 1440x468,
960x468, 1920x234, 1440x234, 1200x234, 960x234, 480x234.
2 Product Features
2.1
Support inputs
Composite video (CVBS) input
S-video input
Digital CCIR-656 input
2.2
Video decoder
Supporting NTSC/PAL/SECAM standard
2D comb filter
2D noise reduction
Macro-vision copy protection
2.3
Video Scaling
Horizontal scaling
Vertical scaling
4:3 to/from 16:9 conversion
2.4
OSD
The normal font size of 12x16
63-downloadable fonts and one space code
Alpha blending, blinking
Maximum display dimension is 20(row) by 31(column)
Flexible memory partition to allocated normal character fonts (with 16 foreground colors
and 8 background colors) and graphic character fonts (with 8 colors per dot)
Programmable character height, width, row space, column space
2.5
ADC auto gain and offset control
Brightness, contrast, tint, and color adjustment
Programmable gamma correction
2.6
sRGB processing
H-peaking and CTI
Specification
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2.7
Chroma coring for noise reduction
2.8
Hardware TV sub-system detection
2.9
Support free-run mode if the sync signal is missing
Programmable TCON
Three PWMs
2.10 Built-in DC-DC switching control for high voltage generation and
white LED panel
2.11 2-to-1 multiplexed 8-bit SAR-ADC support
2.12 Built-in RGB output AMP for gain/offset control
On-chip triple video DAC
2.13 Low power consumption ~230mW (CCIR656 input with RGB AMP)
2.14 64-LQFP/128-pin LQFP package
Specification
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3 Block Diagram
VOUT
STK6036
NSTC/PAL/SECAM decoder
CVBS
S-Video
ADC
2D- Comb filter
CCIR OUT
Chroma
Luma
DCFBK1/2/3
CCIR-656 in
C_D [7:0]
2D
Noise reduction
Color adjustment
LTI/CTI
DC-DC
H/V
Scalar
Gamma
correction/
sRGB
RGB
amp.
TCON
DAC
DCPWM
1/2/3
DAC_R
DAC_G
DAC_B
TCON
signals
Internal OSD
SDA
SCL
I2C
SAR ADC
ADC0/1
Specification
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3.1 QFN Pin Descriptions
PIN NAME
PIN
TYPE
PIN#
PIN#
DESCRIPTION
STK6036A STK6036B
VOUT
A
Y
A
7
14
12
Luma of S-Video Input (CT675A:CVBS1/Y1)
CVBS1
A
8
15
Composite video input 1 (CT675A:CVBS2/Y2)
RMIDBYPASS
A
10
18
R channel internal midscale voltage bypass
(default to be ground)
C
A
11
21
Chroma of S-Video Input (CT675A:CVBS3/C1)
CVBS2
A
GMIDBYPAS
S
A
12
13
22
26
LPFILTER
A
14
30
External connection for filter capacitor
REFBYPASS
A
15
31
Internal reference bypass
TPAD
A
35
Test mode output
C_FID
IO
43
Field ID
C_VS
IO
44
Vertical sync of video port
C_HS
IO
45
Horizontal sync of video port
C_CLK
IO
46
Clock for video port
C_D0
IO
47
YUV data of video port bit 0
C_D1
IO
48
YUV data of video port bit 1
C_D2
IO
49
YUV data of video port bit 2
C_D3
IO
50
YUV data of video port bit 3
C_D4
IO
51
YUV data of video port bit 4
C_D5
IO
52
YUV data of video port bit 5
C_D6
IO
21
53
YUV data of video port bit 6
C_D7
IO
22
54
YUV data of video port bit 7
ITU656_VS
IO
Vertical sync of video port
ITU656_HS
IO
Horizontal sync of video port
ITU656_FID
IO
Field ID
ITU656_CLK
IO
Clock for video port
ITU656_O[7:
0]
IO
YUV data of video port bit 7~0
Buffered composite video output
Composite video input 2 (CT675A:CVBS4/C2)
G channel internal midscale voltage bypass (default
to be ground)
SDA
IO
2
4
Serial I/F data in/out
SCL
IO
1
3
Serial I/F clock
8
Serial I/F sub-address setting
IICADRSEL
I
TESTA
I
18
39
Test pin A
TESTS
I
19
40
Test pin S
XTAL1
I
32
66
Input crystal OSC. clock
XTAL2
O
31
65
Output crystal OSC. clock
Specification
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RSTN
I
PRG_0
PRG_1
PRG_2
O
PRG_3
O
PRG_4
O
PRG_5
3
5
Reset signal (active low)
O
108
Programmable Output G0
O
109
Programmable Output G1
110
Programmable Output G2
111
Programmable Output G3
112
Programmable Output G4
O
113
Programmable Output G5
PRG_6
O
114
Programmable Output G6
PRG_7
O
115
Programmable Output G7
PWM1
O
PWM2
59
60
77
PWM output 1
O
78
PWM output 2
PWM3
O
79
PWM output 3
DCPWM1
O
80
DC-DC control PWM output 1
DCPWM2
O
81
DC-DC control PWM output 2
DCPWM3
O
39
82
DC-DC control PWM output 3
DCFBK1
A
40
83
DC-DC feedback input 1
DCFBK2
A
84
DC-DC feedback input 2
DCFBK3
A
41
85
DC-DC feedback input 3
P_STHL
O
30
64
Start pulse for source driver IC; Active when scan
from L to R, and tri-state when scan from R to L
P_STHR
O
29
63
Start pulse for source driver IC; Active when scan
from R to L, and tri-state when scan from L to R
P_CLKV
O
28
62
Clock for gate driver IC
P_STVU
O
27
61
Start pulse for gate driver; Active when scan from U
to D, and tri-state when scan from D to U
P_STVD
O
26
60
Start pulse for gate driver; Active when scan from D
to U, and tri-state when scan from U to D
P_LP/OEH
O
25
59
Latch pulse for source driver IC
P_POL/PFRP
I
24
58
Polarity for source driver IC
P_HME
O
57
Data inversion control for source driver IC
P_GP1/OEV
O
69
TCON GPO1
P_GP2/Q1H
O
68
TCON GPO2
P_GP3
O
67
TCON GPO3
P_HS
O
1
Panel H sync output
P_VS
O
2
Panel V sync output
P_DE
O
128
Panel data enable output
CPH1
O
56
102
Clock phase 1 for sourced river IC
CPH2
O
57
103
Clock phase 2 for source driver IC
CPH3
O
58
104
Clock phase 3 for source driver IC
DAC_R
A
45
90
Red channel DAC output
DAC_G
A
47
93
Green channel DAC output
DAC_B
A
48
94
Blue channel DAC output
DAC_REXT
A
43
88
External resistor input for DAC
DAC_COMP
A
44
89
Compensation pin of DAC
OP_R
A
52
98
Red channel DAC output
Specification
37
38
34
33
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OP_G
A
53
99
OP_B
A
54
100
Blue channel DAC output
ADC0
A
63
118
SAR ADC input channel 0
/CT675A P_B0 Panel blue pixel data output bit0
ADC1
A
64
119
SAR ADC input channel 1
/CT675A P_B1 Panel blue pixel data output bit1
VCCA_DAC1
P
42
86
Dedicated Analog VCC (3.3V) for DAC
VSSA_DAC1
P
87
Dedicated Analog Ground for DAC
VCCA_DAC2
P
VSSA_DAC2
P
VCCA_DAC3
P
49
95
Dedicated Analog VCC (3.3V) for DAC
VSSA_DAC3
P
50
96
Dedicated Analog Ground for DAC
VCCA2_PLL
P
35
73
Analog VDD (1.8V) for PLL clock generator
VSSA2_PLL
P
36
74
Analog Ground for PLL clock generator
VCCA3
P
27
3.3V analogy supply
VSSA3
P
32
Analog ground
VCC2A_I
P
16
37
Analog 1.8v supply
VSS2A_I
P
17
38
Analog ground
VCC2A_O
P
33
Analog 1.8v supply
VSS2A_O
P
36
Analog ground
AVDD (3.3V) for ADC analog core
46
Green channel DAC output
91
Dedicated Analog VCC (3.3V) for DAC
92
Dedicated Analog Ground for DAC
VCCA3_ADC
P
6
11
VSSA_ADC
P
9
17
VDD5
P
55
101
Ground for ADC analog core
VDD (5.0V) for RGB amplifier
VSS5
P
51
97
VDD3
P
23,62
6,55,
76,117
VDD (3.3V) for IO
VSS3
P
61
7,56,
75,116
Ground for IO
VDD2
P
4,20
VDD (1.8V) for digital core
VSS2
P
5
9,42,
71,107
10,41,
70,106
Ground for RGB amplifier
Ground for digital core
I: Input
O: Output
IO: In/out
P: Power
A: Analog
Specification
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4 Functional Comparison
STK6036A
STK6036B
Package
Power
Video sources
64-LQFP
1.8/3.3V/5V (*1)
CVBS
S-video
128-LQFP
1.8/3.3V/5V (*1)
CVBS
S-video
Hardware TV
subsystem detection
Free-run mode
CVBS Input ports
CCIR-656 input
Sharpness
VOUT
Enhanced TCON
Yes
Yes
Yes
4
No
LTI/CTI
No
3.5” delta type
PVI 10”
Yes
Yes
3x
24.576MHz
63
No
Yes
4
Yes
LTI/CTI
Yes
3.5” delta type
PVI 10”
Yes
Yes
3x
24.576MHz
63
No
1x
2x
RGB amplifier
sRGB
DCDC
Crystal frequency
OSD fonts
External OSD
overlap
low speed ADC
Note : 1). 5V is provided for RGB amplifier use only
Specification
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5 Register Specification and Function Description
5.1 Analog registers
5.1.1
Analog front end slave addresses
Device name
IICADRSEL
Slave Address (hex)
[6:0],0
Analog Front End
5.1.2
Bit#
0
42
1
4A
PI-ADC I2C registers
Control bits
default
R/W
Description
80
R/W
ADC gain
80
R/W
ADC offset
80
R/W
C channel clamp offset voltage
R/W
Band gap power down
GAIN (03H)
7-0
GAIN[7:0]
OFFSET (06H)
7-0
OFFSET[7:0]
CBOFF (0EH)
7-0
CBOFF[7:0]
Band gap Power control (11H)
7-6
Reserved
00
5
BANDGAP
0
2-0
Reserved
000
Clamping control (12H)
7
Reserved
0
3
CSSEL3
0
R/W
C channel clamp 240 level
2
CSSEL2
0
R/W
C channel clamp 252 level
Reserved
0
R/W
1-0
XCLAMPSEL 0~1 (13H)
7
COMPY
1
R/W
Y Mid-level clamping op-amp compensation (1 to
5
YCLAMPSEL
0
R/W
Y channel clamp select (0 to ground, 1 to mid-level)
3
CCLAMPSEL
0
R/W
C channel clamp select (0 to ground, 1 to mid-level)
Reserved
0
R/W
enable)
1-0
CONVERT (15H)
7-4
Reserved
0
R/W
3
CONV11
1
R/W
2
Reserved
1
R/W
1
CONV9
0
R/W
0
Reserved
0
R/W
0
R/W
Conversion range 1.6V mode 1
Conversion range 1.6V mode 2 (when CONV[11]=0)
VOUTSEL (16H)
7-2
Reserved
Specification
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1
VOUTSEL1
1
R/W
VOUT enable
0: disable
1: enable
0
VOUTSEL0
0
R/W
Output channel selection
0: Y channel
1: C channel
MODE (17H)
7
MODE7
0
R/W
dual mode selection
0: single mode
1: dual mode
6-4
3
Reserved
0
R/W
MODE3
0
R/W
Y channel power-down
0: Normal
1: Power down
2
MODE2
0
R/W
VOUT buffer power-down
0: Normal
1: Power down
1
Reserved
1
R/W
0
MODE0
1
R/W
Conversion range 1.3V
R/W
ADC bias default current selection
R/W
0001: Select Y1 (CVSB1) on Y channel
0100: Select Y2 (CVBS3) on Y channel
SPEED (1BH)
7-4
SPEED[7:4]
A
3-0
Reserved
0
YINSEL (20H)
7-0
YINSEL[7:0]
00
0010, 1000: reserved
CINSEL (23H)
7-0
CINSEL[7:0]
00
R/W
0001: Select C1(CVBS2) on C channel
0100: Select C2 (CVSB4) on C channel
0010, 1000: reserved
PWDNB (25H)
7-1
0
Reserved
PWDNB
1
R/W
Power down ADC
1: active
0: power down
YBOFF (26H)
7-0
YBOFF
80
R/W
Y channel clamp offset voltage
CSSEL7
0
R/W
Y channel clamp 240 level
CSSEL6
0
R/W
Y channel clamp 252 level
CSSEL (28H)
7-4
1
0
Reserved
Specification
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5.2 Video Decoder
5.2.1
Video decoder slave addresses
Device name
Video Decoder
5.2.2
IICADRSEL
Slave Address (hex)
[6:0],0
0
40
1
48
I2C registers
MISC_CTRL1 (00H)
7
REG_SWP_YUV
1
R/W
Swap y and uv for ccir656 output
6
REG_FLIP_UV
0
R/W
Flip u and v
5
REG_BLUE_FLIP
1
R/W
Flip blue mode
4
REG_CKILL
0
R/W
Chroma kill
3
REG_422MASK_EN
0
R/W
Mask blanking period data for 422 output
2
REG_CCIR656_EN
1
R/W
Enable ccir 656 output
1
REG_SVIDEO
0
R/W
Enable S-Video
0
RESERVED
0
R/W
1
R/W
AUTO_MODE_1 (01H)
7
REG_AUTO_DFE
Automatic register programming for digital front
end
6
REG_AUTO_SYNC
1
R/W
Automatic register programming for video
synchronization
5
REG_AUTO_LUMA
1
R/W
Automatic register programming for luma
processing
4
REG_AUTO_CHROMA
1
R/W
Automatic register programming for chroma
processing
3
REG_AUTO_STD
1
R/W
Automatic sub-system detection
REG_STD_SEL
5
R/W
when reg_auto_std disabled, manually select sub-
2-0
system standard :
000: SECAM
001: NTSC 50
010: PAL B/G
011: PAL N
100: NTSC 60
101: NTSC M
110: PAL 60
111: PAL M
AUTO_MODE_2 (02H)
7-6
reserved
Specification
0
R/W
12 / 35
Reserved
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5-4
REG_EXT_OSC
1
R/W
00: reserved
01: 24.576MHz
10: reserved
11: reserved
3-1
0
RESERVED
0
R/W
Reserved
REG_AUTO_DCF
1
R/W
Automatic programming for 2D comb
00
R/W
REG_Y2C_CORING
0
R/W
1: Y-dependent C coring
REG_UV_BW_CORING
2
R/W
Coring level
2
R/W
blue screen mode
CORING_REG0 (03H)
7-4
3
RESERVED
0: Y & C independent coring
2-0
MVD_CHROMA0 (04H)
7-6
REG_BLUE_MODE
00: disable
01: enable
1X: auto
5
REG_USR_CKILL
0
R/W
4
REG_USR_CKILL_ON
0
R/W
0: auto color kill
1: manual color kill
Manual color kill
0: off
1: on
3
REG_CKILLMODE
0
R/W
color kill counting mode
2
REG_DIRECT_NOCLR
1
R/W
0: delay mode to update color-kill status
1
Reserved
0
R/W
Reserved
0
REG_CHROMA_UVSWAP
0
R/W
UV swap
20
R/W
DC offset adjustment
00
R/W
Brightness adjustment
7A
R/W
Contract adjustment
00
R/W
1: real time mode to update color-kill status
MVD_DC (05H)
7-0
REG_DC_OFFSET
MVD_BRIGT (06H)
7-0
REG_BRIGHTNESS
MVD_CTRST (07H)
7-0
REG_CONTRAST
MVD_HUE (08H)
7-0
REG_HUEC
hue adjustment
suggested setting from BEh ~ 00h
MVD_SAT (09H)
7-0
REG_SATURATION
28
R/W
suggested setting 00h ~ 50h
13
R/W
Vertical active start
MVD_VSTART (0AH)
7-0
REG_VSTART
MVD_VWIDTH (0BH)
Specification
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7-0
REG_VWIDTH
80
R/W
Vertical active width
80
R/W
Horizontal active start
80
R/W
Horizontal active width
80
R/W
Hsync start
20
R/W
MVD_HSTART (0CH)
7-0
REG_HSTART
MVD_HWIDTH (0DH)
7-0
REG_HWIDTH
MVD_HS_START (0EH)
7-0
REG_HS_START
VCR_THRESHOLD (0FH)
7-0
REG_VCR_THR
VCR detect threshold
5.3 Miscellanies
5.3.1
Misc. slave address
Device name
IICADRSEL
Misc
5.3.2
Slave Address (hex)
[6:0],0
0
F4
1
FC
Misc. I2C registers
VERSION_REG (00H)
7-0
REG_STK6036_VERSION
00
R
Version control of STK6036
CLOCK_REG0 (02H)
7
REG_DUAL_ADC
0
R/W
Dual (switched) ADC mode
6
REG_ADC_OCLK_DIV
0
R/W
Adc oclk deivider
0: 1* adc_clk
1: 1/2 * adc_clk
5
REG_MVD_CLK_SEL
0
R/W
Mvd clock select
0: 1/2 * VPLL
1: adc oclk
4
REG_DFE_CLK_SEL
0
R/W
Front end MVD clock xpll_clk select
0: XSOC
3-0
REG_ADC_CLK_DLY
0
R/W
Adc iclk delay
1: 1/2 * XPLL
CLOCK_REG1 (03H)
7-4
REG_CCLKO_DLY
0
R/W
CCLK output delay
3
REG_MDAC_DIV
0
R/W
Front end MVD clock xpll_clk select
0: 1 * XPLL
1: 1/2 * XPLL
Specification
14 / 35
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2-0
REG_EXT_LLC_DLY
0
R/W
External llc clock delay
0
R/W
Front end pclk select
00: 1 * fpclk
CLOCK_REG3 (04H)
7:6
REG_PCNT_SEL
01: 1/2 * fpclk
10: 1/3 * fpclk
11: 1/6 * fpclk
5:4
REG_SAR_FSEL
0
R/W
SAR ADC clock divider ratio of XOSC
00: 1 * 1/32
01: 1/2 * 1/32
10: 1/4 * 1/32
11: 1/8 * 1/32
3:2
REG_PWM_FSEL
0
R/W
PWM clock divider ratio of XOSC
00: 1/2
01: 1/4
10: 1/8
11: 1/16
1:0
REG_I2C_FSEL
0
R/W
I2c clock divider ratio of XOSC
00: 1/4
01: 1/8
10: 1/16
11: 1/32
CLOCK_REG3 (06H)
7
6-4
REG_PCLKO_DIV2
0
R/W
Pclk ouput divider of 2
REG_PCLK_FSEL
0
R/W
Panel clock divider ratio for PLL clock
000: 1
001: 1/2
010: 1/4
011: 1/8
100: 1/16
3-0
REG_PCLKO_DLY
0
R/W
Pclk output delay
CLOCK_OFF (07H)
7
REG_SOFT_RST_OSD
0
R/W
Soft-reset for OSD
6
REG_CPH_OFF
0
R/W
Disable CPH control signals
5
REG_ICLK_OFF
0
R/W
Disable ICLK
4
REG_PWG_OFF
0
R/W
Disable DC-DC clock
3
REG_SAR_OFF
1
R/W
Disable SAR ADC clock
2
REG_TCON_OFF
0
R/W
Disable Tcon
1
REG_PCLK_OFF
0
R/W
Disable PCLK
0
REG_OSD_OFF
0
R/W
Disable OSD
Specification
15 / 35
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SOFT_RESET (08H)
7
REG_AUTO_SCL_RST
0
R/W
Automatic scaler soft reset
6
REG_SOFT_RST_VDIN
0
R/W
Soft-reset for scaler video in
5
REG_SOFT_RST_CORE
0
R/W
Soft-reset for scaler misc.
4
REG_SOFT_RST_SCAL
0
R/W
Soft-reset for scaler core
3
REG_SOFT_RST_CHROMA
0
R/W
Soft-reset for MVD chroma
2
REG_SOFT_RST_SYNC
0
R/W
Soft-reset for MVD sync
1
REG_SOFT_RST_DFE
0
R/W
Soft-reset for MVD dfe
0
REG_SOFT_RST
0
R/W
Soft rest for all
01 : STK6036B/STK6036C
MISC_CTRL1 (0AH)
7-6
REG_VPLUS_PACK
0
R/W
5
REG_ADC_ALONE
0
R/W
Stand-alone ADC mode
4
REG_DAC_ALONE
0
R/W
Stand-alone DAC mode
3
REG_BYP_MVD_DAC
0
R/W
Bypass internal 6 bits DAC
2
REG_BYP_PI_ADC
0
R/W
Bypass internal PI-ADC
REG_CCIR_OUT[1:0]
0
R/W
00: disable ccir656 output
01: ccir656 from MVD
10 : STK6036A
1-0
10: ccir656 from SCALER
11: STK6036B ccir in and out mode
MISC_CTRL2 (0BH)
7
REG_SWAP_ADC
0
R/W
Swap ADC channel
6
REG_DCDC_OFF
0
R/W
Disable DC-DC
5
REG_TOUT_OFF
0
R/W
Disable Tcon control signals output
4
REG_POUT_OFF
0
R/W
Disable Tcon data output
3
REG_DAC_R_PD
0
R/W
Power down DAC R channel
2
REG_DAC_G_PD
0
R/W
Power down DAC G channel
1
REG_DAC_B_PD
0
R/W
Power down DAC B channel
0
REG_DAC_PD
0
R/W
Power down DAC
HIV_CTRL (0CH)
Specification
16 / 35
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7
REG_HIV_PD
0
R/W
Power down RGB Ampilfier
6
REG_LLC2_INV
0
R/W
llc2 inverse
0: diable
1: enable
5-4
REG_HIV_DS
0
R/W
3-0
REG_HIV_BC
0
R/W
Driving current
Default 0, max value 11
Bias current
Default 0, max value 1111
SAR_CTRL (0EH)
7-4
RESERVED
0
R/W
3
REG_SAR_ACK
R
Sar adc finish flag
2
REG_SAR_TRG
0
R/W
Sar adc trigger enable
1-0
REG_SAR_CSEL
0
R/W
Sar adc channel sel
00: ADC0
01: ADC1
SAR_DATA (0FH)
7-0
REG_SAR_DOUT
0
R
02
R/W
Sar adc data output
PPLL_CTRL0 (20H)
7-0
REG_PPLL_M
PLL_OUT = XIN*(M/N)/(1+K)
1 < (XIN/N) < 15
100 < PLL_OUT(1+K) < 500
M >= 2, N>= 2
PPLL_CTRL1 (21H)
7
REG_PPLL_K
1
R/W
PPLL post divider for output clock
6-0
REG_PPLL_N
02
R/W
PPLLL input deivide value
PPLL_CTRL2 (22H)
00
R/W
3
REG_PPLL_SEL
0
R/W
2
REG_PPLL_PD
0
R/W
Power down PPLL
1-0
REG_PPLL_TST
0
R/W
PPLL test mode
10
R/W
PLL_OUT = XIN*(M/N)/(1+K)
1 < (XIN/N) < 15
7-4
RESERVED
PPLL select
VPLL_CTRL0 (23H)
7-0
REG_VPLL_M
100 < PLL_OUT(1+K) < 500
M >= 2, N>= 2
VPLL_CTRL1 (24H)
7
REG_VPLL_K
0
R/W
VPLL post divider for output clock
6-0
REG_VPLL_N
2
R/W
VPLLL input deivide value
VPLL_CTRL2 (25H)
Specification
17 / 35
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RESERVED
0
R/W
2
REG_VPLL_PD
0
R/W
Power down VPLL
1-0
REG_VPLL_TST
0
R/W
VPLL test mode
04
R/W
PLL_OUT = XIN*(M/N)/(1+K)
1 < (XIN/N) < 15
7-3
XPLL_CTRL0 (26H)
7-0
REG_XPLL_M
100 < PLL_OUT(1+K) < 500
M >= 2, N>= 2
XPLL_CTRL1 (27H)
7
REG_XPLL_K
0
R/W
XPLL post divider for output clock
6-0
REG_XPLL_N
2
R/W
XPLLL input deivide value
RESERVED
0
R/W
2
REG_XPLL_PD
0
R/W
Power down XPLL
1-0
REG_XPLL_TST
0
R/W
XPLL test mode
XPLL_CTRL2 (28H)
7-3
CPH_CTRL0 (29H)
7
REG_CPH_MODE
0
R/W
0: innolux 3.5" panel
1: pvi 10" panel
6-4
REG_CPH1_DLY
0
R/W
Cph1 clock delay
3-2
REG_CPH1_PHASE
0
R/W
Cph1 clock phase adjust for degree 120 shift in
3.5’’ panel
1-0
REG_CPH1_SEL
0
R/W
Select cph1 clock source
Cph2 clock phase adjust for degree 120 shift in
CPH_CTRL1 (2AH)
7-6
REG_CPH2_PHASE
1
R/W
5-4
REG_CPH3_PHASE
2
R/W
Cph2 clock phase adjust for degree 120 shift in
3.5’’ panel
3-0
REG_CPH1_ADJ
0
R/W
Cph1 cell delay adjust
3.5’’ panel
CPH_CTRL2 (2BH)
7-4
REG_CPH2_ADJ
00
R/W
Cph2 cell delay adjust
3-0
REG_CPH3_ADJ
00
R/W
Cph3 cell delay adjust
REG_CPH_PHASE
0
R/W
Cph clock phase adjust for degree 120 shift in
3.5’’ panel
REG_CPH2_DLY
0
R/W
Cph2 clock delay
REG_CPH_DIV
0
R/W
Cph1 clock divide two
0: div 2 disable
REG_CPH3_DLY
0
R/W
Cph3 clock delay
CPH_CTRL3 (2CH)
7
6-4
3
1: div 2 enable
2-0
Specification
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RG_OUT (2DH)
7-0
REG_PRG_OUT
00
R/W
GPIO
RESERVED
0
R/W
2
REG_PRG_OFF
1
R/W
Disable programmable output
1-0
REG_PIN_SEL
0
R/W
00: PWM2, PWM1
MISC_PACK (2EH)
7-3
01: PWM2, P_GP1
10: P_GP2, PWM1
11: P_GP2, P_GP1
5.4 Scaler Registers
5.4.1
Scaler slave address
Device name
IICADRSEL
Slave Address (hex)
[6:0],0
Scaler
5.4.2
0
F4
1
FC
Scaler I2C registers
REG_INPUT_CTRL0 (01H)
6
REG_EXT_VIDEO
0
R/W
Video source selection
0: internal video
5
REG_CCIR656_ENCODE
0
R/W
Video input is
1: external video
0: normal CCIR656
1: CCIR656 encoded
4
REG_INCODE
0
R/W
Video input formation
0: Binary
1: 2’complement
3
REG_HREF_USE
0
R/W
Reference HREF selection
1: HREF is from video source
2
REG_VREF_USE
0
R/W
Reference VREF selection
1: VREF is from video source
1
REG_IVS_EDGE
0
R/W
Input VS reference edge selection
0: HREF is generated by internal counter
0: VREF is generated by internal counter
0: refer to input VS falling edge
1: refer to input VS rising edge
0
REG_BLANK_CHECK
0
R/W
Whether to check the blanking period while in
CCIR656 decoding process
0: no check the blanking period
1: check the blanking period
REG_OUT_CTRL2 (05H)
7
REG_GAMMA_USE
Specification
0
R/W
19 / 35
Gamma correction
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0: bypass
1: enable
6
REG_RST_GT_ADR
0
R/W
Reset the gamma correction table starting
address to the value defined by
REG_GCT_ADDR (H80) while there is a
transition from low to high
5
REG_DITHER_EN
0
R/W
Dithering
0: disable
1: enable
4
REG_FORCE_BK
0
R/W
Force background
0: disable
1: enable
3
REG_PVS_POL
0
R/W
Output VS polarity setting
0: active low
1: active high
2
REG_PHS_POL
0
R/W
Output HS polarity setting
0: active low
1
REG_PDE_POL
0
R/W
Output DE polarity setting
1: active high
0: active high
1: active low
0
REG_OUT_OFF
0
R/W
Output data
0: enable
1: set to tri-state
REG_MISC_CTRL0 (09H)
3-2
1
reserved
0
R/W
REG_FREERUN_N
1
R/W
Panel output mode selection
0: free run
1: output take a reference from input
0
REG_IIC_DIRECTW
1
R/W
I2C register update sequence
0: wait until next VS
1: update immediately
REG_STATUS (0DH)
7
REG_SCLB_OVERFLOW
0
R
Report Scaler line buffer status
0: normal function
1: overflow
6
REG_SCLB_UNDERFLOW
0
R
Report Scaler line buffer status
0: normal function
1: underflow
5.4.3
I2C Register for Scaler Input window
REG_IH_ASTART (11,10H)
10-0
000
W
Video 1 input horizontal active start
000
W
Video 1 input horizontal active width
000
W
Video 1 input vertical active start
REG_IH_AWIDTH (13,12H)
10-0
REG_IV_ASTART (15,14H)
9-0
REG_IV_AWIDTH (17,16H)
Specification
20 / 35
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9-0
000
W
Video 1 input vertical active width
001
W
Input H-sync delay for wrapping around
0
W
Input VS delay by VS_DELAY * 16 pixel
01
W
REG_IH_WRAP (19,18H)
10-0
REG_VS_DELAY (1AH)
3-0
REG_VS_SPDL (1BH)
7-0
Input VS delay by number of HS. The delayed
signal can used to synchronize the panel VS
REG_VS_FPORCH (1CH)
7-0
01
W
Define the vertical front porch in case the
input is encoded CCIR656
REG_DE_IV_TOTAL (1E,1FH)
9-0
000
5.4.4
R
Read out input total line
I2C Register for Scalar
REG_PH_TOTAL (31, 30H)
10-0
320
W
Panel horizontal total counted by panel clock
0A0
W
Panel horizontal active start
5A0
W
Panel horizontal active width
W
Specify the number of m lines among n lines
from which PH_TOTAL is compensated by 1
08
W
Panel H-sync pulse width
42A
W
Define the offset between IVS and PVS
008
W
Panel vertical active width
408
W
Panel vertical total
08
W
Panel V-sync pulse width
0A0
W
Panel horizontal background start
5A0
W
Panel horizontal background end
008
W
The 9 LSB defines the offset between panel
vertical background and vertical active window
REG_PH_ASTART (33, 32H)
10-0
REG_PH_AWIDTH (35, 34H)
10-0
REG_OFFSET_NO (36H)
7-0
REG_PHS_PULWIDTH (37H)
7-0
REG_PH_DELAY (39, 38H)
10-0
REG_PV_AWIDTH (3B, 3AH)
9-0
REG_PV_TOTAL (3D, 3CH)
9-0
REG_PVS_PULWIDTH (3EH)
7-0
REG_BH_ASTART (41, 40H)
10-0
REG_BH_AEND (43, 42H)
10-0
REG_BV_AOFFSET_EVEN (45, 44H)
9-0
for even field. The MSB bit defines whether
background lead or lag to active window
REG_BV_AOFFSET_ODD (47, 46H)
9-0
408
W
The 9 LSB defines the offset between panel
vertical background and vertical active window
for odd field. The MSB bit defines whether
Specification
21 / 35
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background lead or lag to active window
REG_BV_ASTART (49, 48H)
9-0
0001
W
Define the vertical back-porch in free run
mode
REG_BV_AWIDTH (4B, 4AH)
9-0
0000
W
Define the vertical back ground active width
0000
W
Specify horizontal starting address in freeze
mode
0000
W
Specify vertical starting address in freeze
mode
01
R
Report the distance between IHS to next PHS
from which the output starts to display
0
R
Report the distance between the last IHS to
next PVS
0
R
Report the offset number for last synchronized
PHS
0
R
Report the distance between HIS to next PHS
from which Line Buffer start being activated
0
R
Read out the frozen data in Y/U/V order
0
W
Specify vertical scaling factor
0
W
Specify vertical scaling factor
20
W
Specified vertical scaling factor
0
R/W
REG_FREEZE_HADDR (4D, 4CH)
10-0
REG_FREEZE_VADDR (4F, 4EH)
9-0
REG_SYNC_DISTANCE (51, 50H)
10-0
REG_LHNV_DISTANCE (53, 52H)
10-0
REG_LINE_MARGIN (55, 54H)
10-0
REG_LB_MARGIN (57, 56H)
10-0
REG_FREEZE_READ (58H)
7-0
RGE_VDX (60H)
6-0
REG_VDY (61H)
6-0
REG_VINC (62H)
6-0
REG_SCALE_CTRL (63H)
7-6
REG_SC_ALGO
Scaling algorithm selection
00: linear
01: bell shape
10: SINC
11: pixel replicate
5
REG_VSD_EN
0
R/W
Vertical scaling down
0: disable
1: enable
4
REG_HSD_EN
0
R/W
Horizontal scaling down
0: disable
3
REG_OSD_VSEL
0
R/W
OSD vertical reference selection
0: Panel VS
2
REG_FREEZE
0
R/W
Freeze mode
1: enable
1: Panel vertical active
0: disable
Specification
22 / 35
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1: enable
1
REG_FRZADR_RELOAD
0
R/W
Reload freeze horizontal starting address
0: no reload
0
REG_OSD_HSEL
0
R/W
OSD horizontal reference selection
1: reload starting address
0: Panel HS
1: Panel vertical active
REG_HSD_HDX (64H)
5-0
01
W
Horizontal scaling down factor
00
W
Horizontal scaling down factor
08
W
Horizontal scaling down factor
0
W
REG_HSD_HDY (65H)
5-0
REG_HSD_HINC (66H)
5-0
REG_ARX_INI (67H)
3
REG_AVERAGE_EN
0: interpolation by weighting
1: interpolation by average
2-0
REG_ARX_INI
0
W
Set ARX initial vale
01
W
Define vertical scaling factor
00
W
Define vertical scaling factor
320
W
Define the input active window for horizontal
scaling factor calculation
REG_DENO (68H)
6-0
REG_NEMU (69H)
6-0
REG_IHSC_AWIDTH (6B, 6AH)
10-0
5.4.5
I2C Register for Scaler Output Control
REG_GCT_START (80H)
7-0
00
W
Define the starting address while reload
content of gamma correction table
REG_RED_GCT (81H)
7-0
00
W
Update the red component of gamma
correction table
REG_GRN_GCT (82H)
7-0
00
W
Update the green component of gamma
correction table
REG_RED_GCT (83H)
7-0
00
W
Update the blue component of gamma
correction table
REG_OSD_LUT (84H)
7-0
00
W
Update the content of 16X16 color palette
look up table; the format could be either
RGB565 or RGB555 depends on
REG_CLUT_ALPHA[4]
0: RGB555
1: RGB565
REG_CLUT_ALPHA (85H)
4
0
W
Color look up table format setting
0: RGB555
1: RGB565
Specification
23 / 35
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3-0
00
W
The weighting for Alpha Blending
0000: no Alpha blending
0001
.
~ : Video*CLUT[3:0]/16 +
. CLUT*(1- CLUT[3:0])/16
1111
REG_OSDLUT_ADDR (86H)
7
0
W
Reset CLUT starting address
0: no reset
1: reset starting address to the value defined
by REG_OSDLUT_ADDR[3:0]
3-0
00
W
Re-specified the CLUT starting address while
reload the content of CLUT
00
W
Define red component of the background
color
00
W
Define green component of the background
REG_FORCEBACKGRD_RED (88H)
7-0
REG_FORCEBACKGRD_GRN (89H)
7-0
color
REG_FORCEBACKGRD_BLU (8AH)
7-0
0
W
Define blue component of the background
color
5.5 2D-Noise Reduction
REG_NR_CNTR1 (90H)
7
REG_RECURSIVE
0
W/R
filtering method
0: non-recursive
1: recursive
6
REG_NRTHD_METHOD
1
W/R
nr threshold method
0: fixed by reg_nr_cntr2[3:0]
REG_SOB_DET
2
W/R
SOB (sum of block) method
1: adaptive
5-4
00: off
10: directly thd by reg_YWUp_thd and
reg_YBDn_thd
11: iir filtering thd
3
2-1
0
REG_SAD_METHOD
0
W/R
(debug register)
REG_ PALS_DIST
3
W/R
(debug register)
REG_ PA_DIST
1
W/R
(debug register)
1
W/R
remainder method in divider
REG_NR_CNTR2 (91H)
5
REG_ROUND_OFF
0: ignore
1: round off
4
REG_SCRAMBLE
1
W/R
scramble aperture
0: by line
REG_NRTHD_FORCE
2
W/R
fixed nr threshold
1: by field and line
3-0
Specification
24 / 35
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REG_NRTHD_CONST (92H)
7-4
REG_TH_UPBOUND
0A
W/R
upper bound of nr threshold
3-0
REG_TH_LOWBOUND
00
W/R
lower bound of nr threshold
REG_NESTVAL_CONST (93H)
7-4
REG_NEST_UPBOUND
04
W/R
upper bound of nest value
3-0
REG_NEST_LOWBOUND
00
W/R
lower bound of nest value
REG_NRTHD_OFFSET (94H)
7-4
REG_CORING_THD
08
W/R
coring threshold
3-0
REG_NRTHD_OFFSET
04
W/R
threshold offset in luma filter
[3:2] integer offset
[1:0] floating offset
REG_HP_CNTR (95H)
7
REG_CORING_EN
1
W/R
coring enable
0: disable
1: enable
CORING_LPVAL_EN
0
W/R
5-4
6
CORING_LPVAL_THD
0
W/R
(debug register)
(debug register)
3-2
REG_COMPLEXIMG_EN
3
W/R
ComplexImg enable
00: disable
11: enable
1
REG_COMPLEXIMG_METHOD
1
W/R
ComplexImg method
0: directly
1: iir
REG_NE_THD1 (96H)
7-0
03
W/R
noise estimation threshold[15:8]
E8
W/R
noise estimation threshold[7:0]
REG_NE_THD2 (97H)
7-0
REG_TASTE (98H)
7-6
REG_BYPASS_NR2D
0
W/R
00: bypass nr2d
5-3
REG_NR2D_DEMO
0
W/R
[5]: demo mode
[4]
11: enable nr2d
0: left or up
1: right or down
[3]
0: demo vertical
1: demo horizontal
2-0
REG_TASTE
1
W/R
nr taste
FF
W/R
threshold of upper bound of white region in
SOB
F0
W/R
threshold of lower bound of white region in
SOB
19
W/R
threshold of upper bound of black region in
SOB
00
W/R
threshold of lower bound of black region in
REG_YWUP_THD (99H)
7-0
REG_YWDN_THD (9AH)
7-0
REG_YBUP_THD (9BH)
7-0H
REG_YBDN_THD (9CH)
7-0
Specification
25 / 35
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SOB
REG_WBINV_THD (9DH)
7-0
69
W/R
ratio of non-blanking to total pixel
16
W/R
ratio of histogram to total pixel
B3
W/R
ratio of grouping pixel to histogram
REG_COMPLEXIMG_THD1 (9EH)
7-0
REG_COMPLEXIMG_THD2 (9FH)
7-0
5.6 I2C Register for LTI/CTI
REG_YUV_CTRL (B0H)
7-0
0
R/W
yuv sharpen control.
0
R/W
y sharpen weight.
0
R/W
u sharpen weight.
0
R/W
v sharpen weight.
0
R/W
y sharpen 1st peaking weight.
0
R/W
y sharpen 2nd peaking weight.
0
R/W
u sharpen 1st peaking weight.
0
R/W
u sharpen 2nd peaking weight.
0
R/W
v sharpen 1st peaking weight.
0
R/W
v sharpen 2nd peaking weight.
0
R/W
y sharpen coring weight.
0
R/W
u sharpen coring weight.
0
R/W
v sharpen coring weight.
Main picture sRGB color matrix
0: disable.
REG_Y_CNTR_EDCR_WT (B1H)
7-0
REG_U_CNTR_EDCR_WT (B2H)
7-0
REG_V_CNTR_EDCR_WT (B3H)
7-0
REG_Y_PAEK_WT (B4H)
7-0
REG_Y_CNTR_PK_WT (B5H)
7-0
REG_U_PAEK_WT (B6H)
7-0
REG_U_CNTR_PK_WT (B7H)
7-0
REG_V_PAEK_WT (B8H)
7-0
REG_V_CNTR_PK_WT (B9H)
7-0
REG_Y_CNTR_EDCR_COR (BAH)
7-0
REG_U_CNTR_EDCR_COR (BBH)
7-0
REG_V_CNTR_EDCR_COR (BCH)
7-0
5.7 I2C Register for sRGB
REG_SRGB_CTRL (E0H)
7
REG_MSRGB_EN
0
R/W
6
REG_RY_FORMAT
0
R/W
Define R/Y input data formatting
0: binary
5
REG_GU_FORMAT
0
R/W
Define G/U input data formatting
1: enable.
1: 2’s complement
0: binary
Specification
26 / 35
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1: 2’s complement
4
REG_BV_FORMAT
0
R/W
3-2
REG_UV_CORING
00
R/W
00
W
Define B/V input data formatting
0: binary
1: 2’s complement
REG_SRGB_YOFFSET (E1H)
7-0
256-level offset control for Y component. The
input of matrix is added by the specified offset
that is represented as a 2’s complement vale
80:
-128
00:
7F:
0
127
REG_SRGB_RCOEFF1 (E3, E2H)
10-0
100
W
Define the coefficient 1 of red component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_RCOEFF2 (E5, E4H)
10-0
000
W
Define the coefficient 2 of red component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_RCOEFF3 (E7, E6H)
10-0
000
W
Define the coefficient 3 of red component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_GCOEFF1 (E9, E8H)
10-0
100
W
Define the coefficient 1 of green component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_ SRGB_GCOEFF2 (EB, EAH)
10-0
000
W
Define the coefficient 2 of green component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_GCOEFF3 (ED, ECH)
10-0
000
W
Define the coefficient 3 of green component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_BCOEFF1 (EF, EEH)
10-0
100
W
Define the coefficient 1 of blue component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_BCOEFF2 (F1, F0H)
10-0
000
W
Define the coefficient 2 of blue component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_BCOEFF3 (F3, F2H)
10-0
000
W
Define the coefficient 3 of blue component of
the 3 by 3 matrix which performs color space
conversion on main picture
REG_SRGB_ROFFSSET (F4H)
Specification
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7-0
00
W
256-level sRGB offset control for R
component. The output of matrix is added by
the specified offset that is represented as a
2’s complement value.
80:
00:
-128
0
7F:
127
REG_SRGB_GOFFSSET (F5H)
7-0
00
W
256-level sRGB offset control for G
component. The output of matrix is added by
the specified offset that is represented as a
2’s complement value.
80:
-128
00:
7F:
0
127
REG_SRGB_BOFFSSET (F6H)
7-0
00
W
256-level sRGB offset control for B
component. The output of matrix is added by
the specified offset that is represented as a
2’s complement value.
80:
00:
-128
0
7F:
127
5.8 I2C Register for OSD
REG_GRAPHIC_START (C0H)
6-0
REG_GRAPHIC_START
7F
W
Graphic font start
7F
W
Graphic font end
00
W
Font RAM write address (Auto increment)
00
W
Font LBS (7-0)
00
W
Font MSB (11-8)
00
W
Font code attribute
00
W
Font code address
00
W
Display RAM address (0-255)
00
W
Display RAM address (256-511)
00
W
Display RAM address (512-639)
0
W
The outer of OSD window
REG_GRAPHIC_END (C1H)
6-0
REG_GRAPHIC_END
REG_FONT_ADDR (C2H)
6-0
REG_FONT_ADDR
REG_FONT_LSB (C3H)
7-0
REG_FONT_LSB
REG_FONT_MSB (C4H)
3-0
REG_FONT_MSB
REG_FONT_ATTRIBUTE (C5H)
7-0
REG_FONT_ATTRIBUTE
REG_DT (C6H)
6-0
REG_DT
REG_OSD_AD0 (C7H)
7-0
REG_OSD_AD0
REG_OSD_AD1 (C8H)
7-0
REG_OSD_AD1
REG_OSD_AD2 (C9H)
7-0
REG_OSD_AD2
REG_SODSYS_CTRL (CAH)
7
REG_WINMASK
0: display
Specification
28 / 35
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1: no display
6
REG_FADERATE
0
W
Determine the fade rate
0: 0.5 sec
5
REG_VINTORENDL
0
W
Selection between the leading edge of Vsync
00
W
1: 0.25 sec
and the last scanning line
1-0
REG_OSD_DIV
Dot rate selection
01: divided by 1
02: divided by 2
03: divided by 3
REG_SPACECODE (CBH)
7-6
REG_HposStep
00
W
Horizontal position step
00(1 dots)
01(2 dots)
10(3 dots)
11(4 dots)
5-4
REG_VposStep
00
W
Vertical position step
00(1 lines)
01(2 lines)
10(3 lines)
11(4 lines)
3
REG_SPDEF_R
0
W
Red color of space code
2
REG_SPDEF_G
0
W
Green color of space code
1
REG_SPDEF_B
0
W
Blue color of space code
0
REG_SPDEF_I
0
W
Intensity color of space code
0
W
Column space
000: no space
REG_OSD_DISPLAT_OPTION1 (CCH)
7-5
REG_Column_space
001: 1 dot
:
111: 7 dot
4-0
REG_first_row
00
W
Point to the first display row in the DISPLAY
RAM
REG_OSD_HPOS (CDH)
7-0
REG_HPOS
FF
W
The horizontal starting position
FF
W
The vertical starting position
REG_OSD_VPOS (CEH)
7-0
REG_VPOS
REG_OSD_CTRL2 (CFH)
3
REG_MONITOR_R
0
W
Red color of monitor mode
2
REG_MONITOR_G
0
W
Green color of monitor mode
1
REG_MONITOR_B
0
W
Blue color of monitor mode
0
REG_MONITOR_I
1
W
Intensity color of monitor mode
REG_OSD_CTRL (D0H)
7
REG_SPLIT
0
W
Split bit is valid in boxing mode
6
REG_HALFTONE
0
W
Half Tone bit is valid in boxing mode
4
REG_HSYNC_P
0
W
The polarity of Horizontal sync
0: Negative
1: Positive
3
REG_VSYNC_P
Specification
1
W
29 / 35
The polarity of Vertical sync
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0: Negative
1: Positive
2
REG_BP
1
W
The polarity of Red, Green, Blue, FB outputs
0: Negative
1: Positive
1
REG_BF
0
W
0
REG_OSD_EN
0
W
The blinking rate selection
0 : toggled per 32 Vsync pulses
1 : toggled per 64 Vsync pulses
OSD enable bit
0: disable
1: enable
REG_OSD_DISP_OPTION2 (D1H)
2
REG_ROTATE_FONT
0
W
Rotate font
1
REG_V_MIRROR
0
W
Vertical mirror character font
0
REG_H_MIRROR
0
W
Horizontal mirror character font
REG_OSDWIN_ADDR (D2H)
6
REG_HPOS_BIT8
0
W
The horizontal starting position bit8
5
REG_VPOS_BIT8
0
W
The horizontal starting position bit8
REG_OSDWINDOW_ADDR
00
W
4-0
The OSD window registers address port(Auto
increment)
REG_OSDWIN_DATA (D3H)
7-0
REG_OSDWINDOW_DATA
00
W
The OSD window registers data port
This register was the data port when access
the OSD window register. Writing data to this
register will trigger a write operation to one
of the 20 OSD registers selected by the
OSDWindow_Addr.
5.9 PWM and DC-DC PWG control
5.9.1
PWM
REG_ICLK_MEASURE (D7, D6H)
15-0
R
Measure the ICLK period
R
Measure the PCLK period
REG_PCLK_MEASURE (D9, D8H)
15-0
REG_PWM_CTRL (F9H)
2
REG_PWM1_ON
1
R/W
PWM1
0: enable
1: disable
1
REG_PWM2_ON
1
R/W
0
REG_PWM3_ON
1
R/W
PWM2
0: enable
1: disable
PWM3
0: enable
1: disable
REG_PWM3_DUTY (FAH)
7-0
Specification
00
W
30 / 35
Define the duty cycle of PWM 3
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PWM 3’ Freq = XTAL’s Freq / 1024
REG_PWM2_DUTY (FBH)
7-0
00
W
Define the duty cycle of PWM 2
PWM 2’ Freq = XTAL’s Freq / 1024
REG_PWM1_DUTY (FD, FCH)
15-0
0000
W
With specified output frequency, define the
duty cycle of PWM 1
REG_PWM1_PERIOD (FF, FEH)
15-0
0080
W
Define the output frequency of PWM 1
PWM 1’s Freq =
XTAL’s Freq / 4 * REG_PWM1_PERIOD
5.9.2
DC-DC PWG
1. Optional PWG frequency form 40K up to 1.2 MHz
2. PWG On duration should be limited in 50 %,( 70%, 80%, 90%)
REG_PWG1_INCTL(DAH)
7-6
REG_PWG1_DUTY
01
R/W
On duty limitation of PWG1
00: 50%
01: 70%
10: 80%
11: 90%
5-4
REG_PWG1_MODE
00
R/W
The DC-DC force the PWG1’s pulse width
increment or decrement per:
00: 212 enabled XOSC
01: 214 enabled XOSC
10: 216 enabled XOSC
11: 217 enabled XOSC
3
DCDC_EN
2-0
REG_PWG1_OSC_DIV
1
R/W
0: enable DCDC
1: disable DCDC(low power consumption)
011
R/W
PWG1 clock divider ratio
01
R/W
On duty limitation of PWG2
REG_PWG2_INCTL(DBH)
7-6
REG_PWG2_DUTY
00: 50%
01: 70%
10: 80%
11: 90%
5-4
REG_PWG2_MODE
01
R/W
The DC-DC force the PWG2’s pulse width
increment or decrement per:
00: 212 enabled XOSC
01: 214 enabled XOSC
10: 216 enabled XOSC
11: 217 enabled XOSC
2-0
REG_PWG2_OSC_DIV
000
R/W
PWG2 clock divider ratio
01
R/W
On duty limitation of PWG3
REG_PWG3_INCTL(DCH)
7-6
REG_PWG3_DUTY
00: 50%
Specification
31 / 35
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01: 70%
10: 80%
11: 90%
5-4
REG_PWG3_MODE
01
R/W
The DC-DC force the PWG3’s pulse width
increment or decrement per:
00: 212 enabled XOSC
01: 214 enabled XOSC
10: 216 enabled XOSC
11: 217 enabled XOSC
2-0
REG_PWG3_OSC_DIV
001
R/W
PWG3 clock divider ratio
REG_PWG1_OUTCTL(DDH)
7-4
1000
R/W
PWG1 pulse modulation parameters
3
REG_PWG1_RSTN
REG_PWG1_FC
0
R/W
0: PWG1 reset
2
REG_PWG1_CKEN_ON
1
R/W
0: PWG1’s XOSC controlled by CK_EN
1
REG_PWG1_VSET_EN
0
R/W
1: PWG1 no reset
1: PWG1’s XOSC is disabled
0: PWG1’s VSET from DC-DC is disabled
1: PWG1’s VSET from DC-DC is enabled
0
REG_PWG1_INV
0
R/W
0: PWG1’s output no invert
1: PWG1’s output invert
REG_PWG2_OUTCTL(DEH)
7-4
1000
R/W
PWG2 pulse modulation parameters
3
REG_PWG2_RSTN
REG_PWG2_FC
0
R/W
0: PWG2 reset
2
REG_PWG2_CKEN_ON
1
R/W
0: PWG2’s XOSC controlled by CK_EN
1: PWG2’s XOSC is disabled
1
REG_PWG2_VSET_EN
0
R/W
0: PWG2’s VSET from DC-DC is disabled
1: PWG2’s VSET from DC-DC is enabled
0
REG_PWG2_INV
0
R/W
0: PWG2’s output no invert
1: PWG2 no reset
1: PWG2’s output invert
REG_PWG3_OUTCTL(DFH)
7-4
1001
R/W
PWG3 pulse modulation parameters
3
REG_PWG3_RSTN
REG_PWG3_FC
0
R/W
0: PWG3 reset
1: PWG3 no reset
2
REG_PWG3_CKEN_ON
1
R/W
0: PWG3’s XOSC controlled by CK_EN
1
REG_PWG3_VSET_EN
0
R/W
1: PWG3’s XOSC is disabled
0: PWG3’s VSET from DC-DC is disabled
1: PWG3’s VSET from DC-DC is enabled
0
REG_PWG3_INV
0
R/W
0: PWG3’s output no invert
1: PWG3’s output invert
Specification
32 / 35
STK6036A.B_V1.0
太
太欣
欣半
半導
導體
體股
股份
份有
有限
限公
公司
司
SSYYN
NTTEEK
K SSEEM
MIIC
CO
ON
ND
DU
UC
CTTO
OR
RC
CO
O..,, LLTTD
D..
6 Electrical Characteristics
6.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
RATING
UNIT
VDD3
IO Power Supply
-0.3 to 3.6
V
VDD2
Core Power Supply
-0.25 to 2.0
V
VDD5
RGB amp. power Supply
-0.25 to 5.25
V
VIN
Input Voltage
-0.3 to VCC3+0.3
V
VOUT
Output Voltage
-0.3 to VCC3+0.3
V
o
TSTG
Storage Temperature
-40 to 125
C
*Stress beyond the absolute maximum ratings may cause permanent damage to the devices. These are stress
ratings only and functional operation of the device at these or any other conditions beyond those indicated under
DC Characteristics is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
6.2 Recommended Operating Condition
Symbol
VDD3
VDD2
VDD5
VIN
TOC
Parameter
IO DC Power Supply
Core DC Power Supply
Core DC Power Supply
DC Input Voltage
Operating Classic Temperature
Min.
3.0
1.6
Typ.
3.3
1.8
5
0
0
Max.
3.6
2.0
5.25
VCC3
70
25
Unit
V
V
V
V
o
C
6.3 DC Characteristics
VDD3=3.0~3.6V; VDD2=1.6~2.0V, VSS=0V; TOC=0~+70 oC
Symbol
Parameter
Condition
Min.
IRUN
Supply current in run state (S- VCC3=3.3V,
video mode)
VCC2=1.8V,
VCC5=5V
IPD
Power saving supply current Power down mode
VIH
Low-level input voltage
0.7* VCC
VIL
High-level input voltage
IIL
Input leakage current
-1.0
VOH
Low-level output voltage
2.4
VOL
High-level output voltage
Specification
33 / 35
Typ.
70
48
8
t.b.f.
Max.
0.3* VCC3
1.0
0.4
Unit
mA
µA
V
V
µA
V
V
STK6036A.B_V1.0
太
太欣
欣半
半導
導體
體股
股份
份有
有限
限公
公司
司
SSYYN
NTTEEK
K SSEEM
MIIC
CO
ON
ND
DU
UC
CTTO
OR
RC
CO
O..,, LLTTD
D..
7 Package Outline
128-LQFP (14mm x 14mm x 1.4mm)
SYMBOL
1.
b
e
MILLIMETER.
NOM.
MAX.
MIN.
NOM.
MAX.
0.13
0.18
0.23
0.005
0.007
0.009
0.4 BSC.
Specification
INCH
MIN.
0.016 BSC.
34 / 35
STK6036A.B_V1.0
太
太欣
欣半
半導
導體
體股
股份
份有
有限
限公
公司
司
SSYYN
NTTEEK
K SSEEM
MIIC
CO
ON
ND
DU
UC
CTTO
OR
RC
CO
O..,, LLTTD
D..
Specification
35 / 35
STK6036A.B_V1.0